include/linux/mc146818rtc.h

/* */
   1 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
   2  * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
   3  * derived from Data Sheet, Copyright Motorola 1984 (!).
   4  * It was written to be part of the Linux operating system.
   5  */
   6 /* permission is hereby granted to copy, modify and redistribute this code
   7  * in terms of the GNU Library General Public License, Version 2 or later,
   8  * at your option.
   9  */
  10 
  11 #ifndef _MC146818RTC_H
  12 #define _MC146818RTC_H
  13 #include <asm/io.h>
  14 
  15 #define CMOS_READ(addr) ({ \
  16 outb_p(addr|0x80,0x70); \
  17 inb_p(0x71); \
  18 })
  19 #define CMOS_WRITE(val, addr) ({ \
  20 outb_p(addr|0x80,0x70); \
  21 outb_p(val,0x71); \
  22 })
  23 
  24 /**********************************************************************
  25  * register summary
  26  **********************************************************************/
  27 #define RTC_SECONDS             0
  28 #define RTC_SECONDS_ALARM       1
  29 #define RTC_MINUTES             2
  30 #define RTC_MINUTES_ALARM       3
  31 #define RTC_HOURS               4
  32 #define RTC_HOURS_ALARM         5
  33 /* RTC_*_alarm is always true if 2 MSBs are set */
  34 # define RTC_ALARM_DONT_CARE    0xC0
  35 
  36 #define RTC_DAY_OF_WEEK         6
  37 #define RTC_DAY_OF_MONTH        7
  38 #define RTC_MONTH               8
  39 #define RTC_YEAR                9
  40 
  41 /* control registers - Moto names
  42  */
  43 #define RTC_REG_A               10
  44 #define RTC_REG_B               11
  45 #define RTC_REG_C               12
  46 #define RTC_REG_D               13
  47 
  48 /**********************************************************************
  49  * register details
  50  **********************************************************************/
  51 #define RTC_FREQ_SELECT RTC_REG_A
  52 
  53 /* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
  54  * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
  55  * totalling to a max high interval of 2.228 ms.
  56  */
  57 # define RTC_UIP                0x80
  58 # define RTC_DIV_CTL            0x70
  59    /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
  60 #  define RTC_REF_CLCK_4MHZ     0x00
  61 #  define RTC_REF_CLCK_1MHZ     0x10
  62 #  define RTC_REF_CLCK_32KHZ    0x20
  63    /* 2 values for divider stage reset, others for "testing purposes only" */
  64 #  define RTC_DIV_RESET1        0x60
  65 #  define RTC_DIV_RESET2        0x70
  66   /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
  67 # define RTC_RATE_SELECT        0x0F
  68 
  69 /**********************************************************************/
  70 #define RTC_CONTROL     RTC_REG_B
  71 # define RTC_SET 0x80           /* disable updates for clock setting */
  72 # define RTC_PIE 0x40           /* periodic interrupt enable */
  73 # define RTC_AIE 0x20           /* alarm interrupt enable */
  74 # define RTC_UIE 0x10           /* update-finished interrupt enable */
  75 # define RTC_SQWE 0x08          /* enable square-wave output */
  76 # define RTC_DM_BINARY 0x04     /* all time/date values are BCD if clear */
  77 # define RTC_24H 0x02           /* 24 hour mode - else hours bit 7 means pm */
  78 # define RTC_DST_EN 0x01        /* auto switch DST - works f. USA only */
  79 
  80 /**********************************************************************/
  81 #define RTC_INTR_FLAGS  RTC_REG_C
  82 /* caution - cleared by read */
  83 # define RTC_IRQF 0x80          /* any of the following 3 is active */
  84 # define RTC_PF 0x40
  85 # define RTC_AF 0x20
  86 # define RTC_UF 0x10
  87 
  88 /**********************************************************************/
  89 #define RTC_VALID       RTC_REG_D
  90 # define RTC_VRT 0x80           /* valid RAM and time */
  91 /**********************************************************************/
  92 
  93 /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) 
  94  * determines if the following two #defines are needed
  95  */
  96 #ifndef BCD_TO_BIN
  97 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
  98 #endif
  99 
 100 #ifndef BIN_TO_BCD
 101 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
 102 #endif
 103 
 104 #endif /* _MC146818RTC_H */
/* */
root/include/linux/mc146818rtc.h

INCLUDED FROM
