drivers/scsi/aha152x.h

/* */
   1 #ifndef _AHA152X_H
   2 #define _AHA152X_H
   3 
   4 /*
   5  * $Id: aha152x.h,v 0.2 1993/10/03 00:58:03 root Exp $
   6  */
   7 
   8 #include "../block/blk.h"
   9 #include "scsi.h"
  10 #if defined(__KERNEL__)
  11 #include <asm/io.h>
  12 
  13 int        aha152x_detect(int);
  14 const char *aha152x_info(void);
  15 int        aha152x_command(Scsi_Cmnd *);
  16 int        aha152x_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  17 int        aha152x_abort(Scsi_Cmnd *, int);
  18 int        aha152x_reset(Scsi_Cmnd *);
  19 int        aha152x_biosparam(int, int, int*);
  20 
  21 /* number of queueable commands
  22    (unless we support more than 1 cmd_per_lun this should do) */
  23 #define AHA152X_MAXQUEUE        7               
  24 
  25 /* Initial value of Scsi_Host entry */
  26 #define AHA152X       { /* name */              "Adaptec 152x SCSI driver", \
  27                         /* detect */            aha152x_detect,             \
  28                         /* info */              aha152x_info,               \
  29                         /* command */           aha152x_command,            \
  30                         /* queuecommand */      aha152x_queue,              \
  31                         /* abort */             aha152x_abort,              \
  32                         /* reset */             aha152x_reset,              \
  33                         /* slave_attach */      /* NULL */  0,              \
  34                         /* bios_param */        aha152x_biosparam,          \
  35                         /* can_queue */         1,                          \
  36                         /* this_id */           7,                          \
  37                         /* sg_tablesize */      SG_ALL,                     \
  38                         /* cmd_per_lun */       1,                          \
  39                         /* present */           0,                          \
  40                         /* unchecked_isa_dma */ 0 }
  41 #endif
  42 
  43 
  44 /* port addresses */
  45 #define SCSISEQ         (port_base+0x00)        /* SCSI sequence control */
  46 #define SXFRCTL0        (port_base+0x01)        /* SCSI transfer control 0 */
  47 #define SXFRCTL1        (port_base+0x02)        /* SCSI transfer control 1 */
  48 #define SCSISIG         (port_base+0x03)        /* SCSI signal in/out */
  49 #define SCSIRATE        (port_base+0x04)        /* SCSI rate control */
  50 #define SELID           (port_base+0x05)        /* selection/reselection ID */
  51 #define SCSIID          SELID                   /* SCSI ID */
  52 #define SCSIDAT         (port_base+0x06)        /* SCSI latched data */
  53 #define SCSIBUS         (port_base+0x07)        /* SCSI data bus */
  54 #define STCNT0          (port_base+0x08)        /* SCSI transfer count 0 */
  55 #define STCNT1          (port_base+0x09)        /* SCSI transfer count 1 */
  56 #define STCNT2          (port_base+0x0a)        /* SCSI transfer count 2 */
  57 #define SSTAT0          (port_base+0x0b)        /* SCSI interrupt status 0 */
  58 #define SSTAT1          (port_base+0x0c)        /* SCSI interrupt status 1 */
  59 #define SSTAT2          (port_base+0x0d)        /* SCSI interrupt status 2 */
  60 #define SCSITEST        (port_base+0x0e)        /* SCSI test control */
  61 #define SSTAT4          (port_base+0x0f)        /* SCSI status 4 */
  62 #define SIMODE0         (port_base+0x10)        /* SCSI interrupt mode 0 */
  63 #define SIMODE1         (port_base+0x11)        /* SCSI interrupt mode 1 */
  64 #define DMACNTRL0       (port_base+0x12)        /* DMA control 0 */
  65 #define DMACNTRL1       (port_base+0x13)        /* DMA control 1 */
  66 #define DMASTAT         (port_base+0x14)        /* DMA status */
  67 #define FIFOSTAT        (port_base+0x15)        /* FIFO status */
  68 #define DATAPORT        (port_base+0x16)        /* DATA port */
  69 #define BRSTCNTRL       (port_base+0x18)        /* burst control */
  70 #define PORTA           (port_base+0x1a)        /* PORT A */
  71 #define PORTB           (port_base+0x1b)        /* PORT B */
  72 #define REV             (port_base+0x1c)        /* revision */
  73 #define STACK           (port_base+0x1d)        /* stack */
  74 #define TEST            (port_base+0x1e)        /* test register */
  75 
  76 
  77 /* bits and bitmasks to ports */
  78 
  79 /* SCSI sequence control */
  80 #define TEMODEO         0x80
  81 #define ENSELO          0x40
  82 #define ENSELI          0x20
  83 #define ENRESELI        0x10
  84 #define ENAUTOATNO      0x08
  85 #define ENAUTOATNI      0x04
  86 #define ENAUTOATNP      0x02
  87 #define SCSIRSTO        0x01
  88 
  89 /* SCSI transfer control 0 */
  90 #define SCSIEN          0x80
  91 #define DMAEN           0x40
  92 #define CH1             0x20
  93 #define CLRSTCNT        0x10
  94 #define SPIOEN          0x08
  95 #define CLRCH1          0x02
  96 
  97 /* SCSI transfer control 1 */
  98 #define BITBUCKET       0x80
  99 #define SWRAPEN         0x40
 100 #define ENSPCHK         0x20
 101 #define STIMESEL        0x18    /* mask */
 102 #define STIMESEL_       3
 103 #define ENSTIMER        0x04
 104 #define BYTEALIGN       0x02
 105 
 106 /* SCSI signal IN */
 107 #define CDI             0x80
 108 #define IOI             0x40
 109 #define MSGI            0x20
 110 #define ATNI            0x10
 111 #define SELI            0x08
 112 #define BSYI            0x04
 113 #define REQI            0x02
 114 #define ACKI            0x01
 115 
 116 /* SCSI Phases */
 117 #define P_MASK          (MSGI|CDI|IOI)
 118 #define P_DATAO         (0)
 119 #define P_DATAI         (IOI)
 120 #define P_CMD           (CDI)
 121 #define P_STATUS        (CDI|IOI)
 122 #define P_MSGO          (MSGI|CDI)
 123 #define P_MSGI          (MSGI|CDI|IOI)
 124 
 125 /* SCSI signal OUT */
 126 #define CDO             0x80
 127 #define IOO             0x40
 128 #define MSGO            0x20
 129 #define ATNO            0x10
 130 #define SELO            0x08
 131 #define BSYO            0x04
 132 #define REQO            0x02
 133 #define ACKO            0x01
 134 
 135 /* SCSI rate control */
 136 #define SXFR            0x70    /* mask */
 137 #define SXFR_           4
 138 #define SOFS            0x0f    /* mask */
 139 
 140 /* SCSI ID */
 141 #define OID             0x70
 142 #define OID_            4
 143 #define TID             0x07
 144 
 145 /* SCSI transfer count */
 146 #define GETSTCNT()   ( (GETPORT(STCNT2)<<16) \
 147                      + (GETPORT(STCNT1)<< 8) \
 148                      + GETPORT(STCNT0) )
 149 
 150 #define SETSTCNT(X)  { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
 151                        SETPORT(STCNT1, ((X) & 0x00FF00) >>  8); \
 152                        SETPORT(STCNT0, ((X) & 0x0000FF) ); }
 153 
 154 /* SCSI interrupt status */
 155 #define TARGET          0x80
 156 #define SELDO           0x40
 157 #define SELDI           0x20
 158 #define SELINGO         0x10
 159 #define SWRAP           0x08
 160 #define SDONE           0x04
 161 #define SPIORDY         0x02
 162 #define DMADONE         0x01
 163 
 164 #define SETSDONE        0x80
 165 #define CLRSELDO        0x40
 166 #define CLRSELDI        0x20
 167 #define CLRSELINGO      0x10
 168 #define CLRSWRAP        0x08
 169 #define CLRSDONE        0x04
 170 #define CLRSPIORDY      0x02
 171 #define CLRDMADONE      0x01
 172 
 173 /* SCSI status 1 */
 174 #define SELTO           0x80
 175 #define ATNTARG         0x40
 176 #define SCSIRSTI        0x20
 177 #define PHASEMIS        0x10
 178 #define BUSFREE         0x08
 179 #define SCSIPERR        0x04
 180 #define PHASECHG        0x02
 181 #define REQINIT         0x01
 182 
 183 #define CLRSELTIMO      0x80
 184 #define CLRATNO         0x40
 185 #define CLRSCSIRSTI     0x20
 186 #define CLRBUSFREE      0x08
 187 #define CLRSCSIPERR     0x04
 188 #define CLRPHASECHG     0x02
 189 #define CLRREQINIT      0x01
 190 
 191 /* SCSI status 2 */
 192 #define SOFFSET         0x20
 193 #define SEMPTY          0x10
 194 #define SFULL           0x08
 195 #define SFCNT           0x07    /* mask */
 196 
 197 /* SCSI status 3 */
 198 #define SCSICNT         0xf0    /* mask */
 199 #define SCSICNT_        4
 200 #define OFFCNT          0x0f    /* mask */
 201 
 202 /* SCSI TEST control */
 203 #define SCTESTU         0x08
 204 #define SCTESTD         0x04
 205 #define STCTEST         0x01
 206 
 207 /* SCSI status 4 */
 208 #define SYNCERR         0x04
 209 #define FWERR           0x02
 210 #define FRERR           0x01
 211 
 212 #define CLRSYNCERR      0x04
 213 #define CLRFWERR        0x02
 214 #define CLRFRERR        0x01
 215 
 216 /* SCSI interrupt mode 0 */
 217 #define ENSELDO         0x40
 218 #define ENSELDI         0x20
 219 #define ENSELINGO       0x10
 220 #define ENSWRAP         0x08
 221 #define ENSDONE         0x04
 222 #define ENSPIORDY       0x02
 223 #define ENDMADONE       0x01
 224 
 225 /* SCSI interrupt mode 1 */
 226 #define ENSELTIMO       0x80
 227 #define ENATNTARG       0x40
 228 #define ENSCSIRST       0x20
 229 #define ENPHASEMIS      0x10
 230 #define ENBUSFREE       0x08
 231 #define ENSCSIPERR      0x04
 232 #define ENPHASECHG      0x02
 233 #define ENREQINIT       0x01
 234 
 235 /* DMA control 0 */
 236 #define ENDMA           0x80
 237 #define _8BIT           0x40
 238 #define DMA             0x20
 239 #define WRITE_READ      0x08
 240 #define INTEN           0x04
 241 #define RSTFIFO         0x02
 242 #define SWINT           0x01
 243 
 244 /* DMA control 1 */
 245 #define PWRDWN          0x80
 246 #define STK             0x07    /* mask */
 247 
 248 /* DMA status */
 249 #define ATDONE          0x80
 250 #define WORDRDY         0x40
 251 #define INTSTAT         0x20
 252 #define DFIFOFULL       0x10
 253 #define DFIFOEMP        0x08
 254 
 255 /* BURST control */
 256 #define BON             0xf0
 257 #define BOFF            0x0f
 258 
 259 /* TEST REGISTER */
 260 #define BOFFTMR         0x40
 261 #define BONTMR          0x20
 262 #define STCNTH          0x10
 263 #define STCNTM          0x08
 264 #define STCNTL          0x04
 265 #define SCSIBLK         0x02
 266 #define DMABLK          0x01
 267 
 268 /* On the AHA-152x board PORTA and PORTB contain
 269    some information about the board's configuration. */
 270 typedef union {
 271   struct {
 272     unsigned reserved:2;        /* reserved */
 273     unsigned tardisc:1;         /* Target disconnect: 0=disabled, 1=enabled */
 274     unsigned syncneg:1;         /* Initial sync neg: 0=disabled, 1=enabled */
 275     unsigned msgclasses:2;      /* Message classes
 276                                    0=#4
 277                                    1=#0, #1, #2, #3, #4
 278                                    2=#0, #3, #4
 279                                    3=#0, #4
 280                                 */
 281     unsigned boot:1;            /* boot: 0=disabled, 1=enabled */
 282     unsigned dma:1;             /* Transfer mode: 0=PIO; 1=DMA */
 283     unsigned id:3;              /* SCSI-id */
 284     unsigned irq:2;             /* IRQ-Channel: 0,3=12, 1=10, 2=11 */
 285     unsigned dmachan:2;         /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */
 286     unsigned parity:1;          /* SCSI-parity: 1=enabled 0=disabled */
 287   } fields;
 288   unsigned short port;
 289 } aha152x_config ;
 290 
 291 #define cf_parity       fields.parity
 292 #define cf_dmachan      fields.dmachan
 293 #define cf_irq          fields.irq
 294 #define cf_id           fields.id
 295 #define cf_dma          fields.dma
 296 #define cf_boot         fields.boot
 297 #define cf_msgclasses   fields.msgclasses
 298 #define cf_syncneg      fields.syncneg
 299 #define cf_tardisc      fields.tardisc
 300 #define cf_port         port
 301 
 302 /* Some macros to manipulate ports and their bits */
 303 
 304 #define SETPORT(PORT, VAL)      \
 305         outb( (VAL), (PORT) )
 306 
 307 #define SETPORTP(PORT, VAL)     \
 308         outb_p( (VAL), (PORT) )
 309 
 310 #define SETPORTW(PORT, VAL)     \
 311         outw( (VAL), (PORT) )
 312 
 313 #define GETPORT(PORT)   \
 314         inb( PORT )
 315 
 316 #define GETPORTW(PORT)  \
 317         inw( PORT )
 318 
 319 #define SETBITS(PORT, BITS)     \
 320         outb( (inb(PORT) | (BITS)), (PORT) )
 321 
 322 #define CLRBITS(PORT, BITS)     \
 323         outb( (inb(PORT) & ~(BITS)), (PORT) )
 324 
 325 #define CLRSETBITS(PORT, CLR, SET)      \
 326         outb( (inb(PORT) & ~(CLR)) | (SET) , (PORT) )
 327 
 328 #define TESTHI(PORT, BITS)      \
 329         ((inb(PORT) & (BITS)) == BITS)
 330 
 331 #define TESTLO(PORT, BITS)      \
 332         ((inb(PORT) & (BITS)) == 0)
 333 
 334 #endif /* _AHA152X_H */
/* */
root/drivers/scsi/aha152x.h

INCLUDED FROM
