drivers/scsi/NCR5380.h

/* */
This source file includes following definitions.
NCR5380_i386_dma_setup
NCR5380_i386_dma_write_setup
NCR5380_i386_dma_read_setup
NCR5380_i386_dma_residual
   1 /* 
   2  * NCR 5380 defines
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 666-5836
   9  *
  10  * DISTRIBUTION RELEASE 4
  11  *
  12  * For more information, please consult 
  13  *
  14  * NCR 5380 Family
  15  * SCSI Protocol Controller
  16  * Databook
  17  * NCR Microelectronics
  18  * 1635 Aeroplaza Drive
  19  * Colorado Springs, CO 80916
  20  * 1+ (719) 578-3400
  21  * 1+ (800) 334-5454
  22  */
  23 
  24 /*
  25  * $Log: NCR5380.h,v $
  26  * Revision 1.3  1994/01/19  05:24:40  drew
  27  * Added support for TCR LAST_BYTE_SENT bit.
  28  *
  29  * Revision 1.3  1994/01/19  05:24:40  drew
  30  * Added support for TCR LAST_BYTE_SENT bit.
  31  *
  32  * Revision 1.2  1994/01/15  06:14:11  drew
  33  * REAL DMA support, bug fixes.
  34  *
  35  * Revision 1.1  1994/01/15  06:00:54  drew
  36  * Initial revision
  37  */
  38 
  39 #ifndef NCR5380_H
  40 #define NCR5380_H
  41 
  42 #define NCR5380_PUBLIC_RELEASE 4
  43 
  44 #define NDEBUG_ARBITRATION      0x1
  45 #define NDEBUG_AUTOSENSE        0x2
  46 #define NDEBUG_DMA              0x4
  47 #define NDEBUG_HANDSHAKE        0x8
  48 #define NDEBUG_INFORMATION      0x10
  49 #define NDEBUG_INIT             0x20
  50 #define NDEBUG_INTR             0x40
  51 #define NDEBUG_LINKED           0x80
  52 #define NDEBUG_MAIN             0x100
  53 #define NDEBUG_NO_DATAOUT       0x200
  54 #define NDEBUG_NO_WRITE         0x400
  55 #define NDEBUG_PIO              0x800
  56 #define NDEBUG_PSEUDO_DMA       0x1000
  57 #define NDEBUG_QUEUES           0x2000
  58 #define NDEBUG_RESELECTION      0x4000
  59 #define NDEBUG_SELECTION        0x8000
  60 #define NDEBUG_USLEEP           0x10000
  61 #define NDEBUG_LAST_BYTE_SENT   0x20000
  62 
  63 /* 
  64  * The contents of the OUTPUT DATA register are asserted on the bus when
  65  * either arbitration is occuring or the phase-indicating signals (
  66  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  67  * bit in the INTITIATOR COMMAND register is set.
  68  */
  69 
  70 #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  71 #define CURRENT_SCSI_DATA_REG   0       /* ro same */
  72 
  73 #define INITIATOR_COMMAND_REG   1       /* rw */
  74 #define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  75 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  76 #define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  77 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  78 #define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  79 #define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  80 #define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  81 #define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  82 #define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  83 #define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  84 
  85 #ifdef DIFFERENTIAL
  86 #define ICR_BASE                ICR_DIFF_ENABLE
  87 #else
  88 #define ICR_BASE                0
  89 #endif
  90 
  91 #define MODE_REG                2
  92 /*
  93  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
  94  * transfer, causing the chip to hog the bus.  You probably don't want 
  95  * this.
  96  */
  97 #define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
  98 #define MR_TARGET               0x40    /* rw target mode */
  99 #define MR_ENABLE_PAR_CHECK   0x20      /* rw enable parity checking */
 100 #define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
 101 #define MR_ENABLE_EOP_INTR      0x08    /* rw enabble eop interrupt */
 102 #define MR_MONITOR_BSY  0x04    /* rw enable int on unexpected bsy fail */
 103 #define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
 104 #define MR_ARBITRATE            0x01    /* rw start arbitration */
 105 
 106 #ifdef PARITY
 107 #define MR_BASE                 MR_ENABLE_PAR_CHECK
 108 #else
 109 #define MR_BASE                 0
 110 #endif
 111 
 112 #define TARGET_COMMAND_REG      3
 113 #define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 114 #define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 115 #define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 116 #define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 117 #define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 118 
 119 #define STATUS_REG              4       /* ro */
 120 /*
 121  * Note : a set bit indicates an active signal, driven by us or another 
 122  * device.
 123  */
 124 #define SR_RST                  0x80    
 125 #define SR_BSY                  0x40
 126 #define SR_REQ                  0x20
 127 #define SR_MSG                  0x10
 128 #define SR_CD                   0x08
 129 #define SR_IO                   0x04
 130 #define SR_SEL                  0x02
 131 #define SR_DBP                  0x01
 132 
 133 /*
 134  * Setting a bit in this register will cause an interrupt to be generated when 
 135  * BSY is false and SEL true and this bit is asserted  on the bus.
 136  */
 137 #define SELECT_ENABLE_REG       4       /* wo */
 138 
 139 #define BUS_AND_STATUS_REG      5       /* ro */
 140 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 141 #define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 142 #define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 143 #define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 144 #define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 145 #define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 146 #define BASR_ATN                0x02    /* ro BUS status */
 147 #define BASR_ACK                0x01    /* ro BUS status */
 148 
 149 /* Write any value to this register to start a DMA send */
 150 #define START_DMA_SEND_REG      5       /* wo */
 151 
 152 /* 
 153  * Used in DMA transfer mode, data is latched from the SCSI bus on
 154  * the falling edge of REQ (ini) or ACK (tgt)
 155  */
 156 #define INPUT_DATA_REG                  6       /* ro */
 157 
 158 /* Write any value to this register to start a DMA recieve */
 159 #define START_DMA_TARGET_RECIEVE_REG    6       /* wo */
 160 
 161 /* Read this register to clear interrupt conditions */
 162 #define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 163 
 164 /* Write any value to this register to start an ini mode DMA recieve */
 165 #define START_DMA_INITIATOR_RECIEVE_REG 7       /* wo */
 166 
 167 /* Note : PHASE_* macros are based on the values of the STATUS register */
 168 #define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 169 
 170 #define PHASE_DATAOUT   0
 171 #define PHASE_DATAIN    SR_IO
 172 #define PHASE_CMDOUT    SR_CD
 173 #define PHASE_STATIN    (SR_CD | SR_IO)
 174 #define PHASE_MSGOUT    (SR_MSG | SR_CD)
 175 #define PHASE_MSGIN     (SR_MSG | SR_CD | SR_IO)
 176 #define PHASE_UNKNOWN   0xff
 177 
 178 /* 
 179  * Convert status register phase to something we can use to set phase in 
 180  * the target register so we can get phase mismatch interrupts on DMA 
 181  * transfers.
 182  */
 183  
 184 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)   
 185 
 186 /*
 187  * The internal should_disconnect() function returns these based on the 
 188  * expected length of a disconnect if a device supports disconnect/
 189  * reconnect.
 190  */
 191 
 192 #define DISCONNECT_NONE         0
 193 #define DISCONNECT_TIME_TO_DATA 1
 194 #define DISCONNECT_LONG         2
 195 
 196 /* 
 197  * These are "special" values for the tag parameter passed to NCR5380_select.
 198  */
 199 
 200 #define TAG_NEXT        -1      /* Use next free tag */
 201 #define TAG_NONE        -2      /* 
 202                                  * Establish I_T_L nexus instead of I_T_L_Q
 203                                  * even on SCSI-II devices.
 204                                  */
 205 
 206 /*
 207  * These are "special" values for the irq and dma_channel fields of the 
 208  * Scsi_Host structure
 209  */
 210 
 211 #define IRQ_NONE        255
 212 #define DMA_NONE        255
 213 #define IRQ_AUTO        254
 214 #define DMA_AUTO        254
 215 
 216 #define FLAG_HAS_LAST_BYTE_SENT         1       /* NCR53c81 or better */
 217 #define FLAG_CHECK_LAST_BYTE_SENT       2       /* Only test once */
 218 
 219 #ifndef ASM
 220 struct NCR5380_hostdata {
 221     NCR5380_implementation_fields;              /* implmenentation specific */
 222     unsigned char id_mask, id_higher_mask;      /* 1 << id, all bits greater */
 223     volatile unsigned char busy[8];             /* index = target, bit = lun */
 224 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
 225     volatile int dma_len;                       /* requested length of DMA */
 226 #endif
 227     volatile unsigned char last_message;        /* last message OUT */
 228     volatile Scsi_Cmnd *connected;              /* currently connected command */
 229     volatile Scsi_Cmnd *issue_queue;            /* waiting to be issued */
 230     volatile Scsi_Cmnd *disconnected_queue;     /* waiting for reconnect */
 231     int flags;
 232 #ifdef USLEEP
 233     unsigned long time_expires;                 /* in jiffies, set prior to sleeping */
 234     struct Scsi_Host *next_timer;
 235 #endif
 236 };
 237 
 238 #ifdef __KERNEL__
 239 static struct Scsi_Host *first_instance;                /* linked list of 5380's */
 240 
 241 #if defined(AUTOPROBE_IRQ)
 242 static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
 243 #endif
 244 static void NCR5380_init (struct Scsi_Host *instance);
 245 static void NCR5380_information_transfer (struct Scsi_Host *instance);
 246 static void NCR5380_intr (int irq);
 247 static void NCR5380_main (void);
 248 static void NCR5380_print_options (struct Scsi_Host *instance);
 249 #ifndef NCR5380_abort
 250 static
 251 #endif
 252 int NCR5380_abort (Scsi_Cmnd *cmd, int code);
 253 #ifndef NCR5380_reset
 254 static
 255 #endif
 256 int NCR5380_reset (Scsi_Cmnd *cmd);
 257 #ifndef NCR5380_queue_command
 258 static 
 259 #endif
 260 int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
 261 
 262 
 263 static void NCR5380_reselect (struct Scsi_Host *instance);
 264 static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
 265 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
 266 static int NCR5380_transfer_dma (struct Scsi_Host *instance,
 267         unsigned char *phase, int *count, unsigned char **data);
 268 #endif
 269 static int NCR5380_transfer_pio (struct Scsi_Host *instance,
 270         unsigned char *phase, int *count, unsigned char **data);
 271 
 272 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) && defined(i386)
 273 static __inline__ int NCR5380_i386_dma_setup (struct Scsi_Host *instance,
     /*  */
 274         unsigned char *ptr, unsigned int count, unsigned char mode) {
 275     unsigned limit;
 276 
 277     if (instance->dma_channel <=3) {
 278         if (count > 65536)
 279             count = 65536;
 280         limit = 65536 - (((unsigned) ptr) & 0xFFFF);
 281     } else {
 282         if (count > 65536 * 2) 
 283             count = 65536 * 2;
 284         limit = 65536* 2 - (((unsigned) ptr) & 0x1FFFF);
 285     }
 286 
 287     if (count > limit) count = limit;
 288 
 289     if ((count & 1) || (((unsigned) ptr) & 1))
 290         panic ("scsi%d : attmpted unaligned DMA transfer\n", instance->host_no);
 291     cli();
 292     disable_dma(instance->dma_channel);
 293     clear_dma_ff(instance->dma_channel);
 294     set_dma_addr(instance->dma_channel, (unsigned int) ptr);
 295     set_dma_count(instance->dma_channel, count);
 296     set_dma_mode(instance->dma_channel, mode);
 297     enable_dma(instance->dma_channel);
 298     sti();
 299     return count;
 300 }
 301 
 302 static __inline__ int NCR5380_i386_dma_write_setup (struct Scsi_Host *instance,
     /*  */
 303     unsigned char *src, unsigned int count) {
 304     return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_WRITE);
 305 }
 306 
 307 static __inline__ int NCR5380_i386_dma_read_setup (struct Scsi_Host *instance,
     /*  */
 308     unsigned char *src, unsigned int count) {
 309     return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_READ);
 310 }
 311 
 312 static __inline__ int NCR5380_i386_dma_residual (struct Scsi_Host *instance) {
     /*  */
 313     register int tmp;
 314     cli();
 315     clear_dma_ff(instance->dma_channel);
 316     tmp = get_dma_residue(instance->dma_channel);
 317     sti();
 318     return tmp;
 319 }
 320 #endif /* defined(REAL_DMA) && defined(i386)  */
 321 #endif __KERNEL_
 322 #endif /* ndef ASM */
 323 #endif /* NCR5380_H */
/* */
root/drivers/scsi/NCR5380.h

INCLUDED FROM

DEFINITIONS
