root/include/asm/dma.h

/* [previous][next][first][last][top][bottom][index][help] */

INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. enable_dma
  2. disable_dma
  3. clear_dma_ff
  4. set_dma_mode
  5. set_dma_page
  6. set_dma_addr
  7. set_dma_count
  8. get_dma_residue

   1 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  */
   7 
   8 #ifndef _ASM_DMA_H
   9 #define _ASM_DMA_H
  10 
  11 #include <asm/io.h>             /* need byte IO */
  12 
  13 
  14 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  15 #define outb    outb_p
  16 #endif
  17 
  18 /*
  19  * NOTES about DMA transfers:
  20  *
  21  *  controller 1: channels 0-3, byte operations, ports 00-1F
  22  *  controller 2: channels 4-7, word operations, ports C0-DF
  23  *
  24  *  - ALL registers are 8 bits only, regardless of transfer size
  25  *  - channel 4 is not used - cascades 1 into 2.
  26  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  27  *  - channels 5-7 are word - addresses/counts are for physical words
  28  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  29  *  - transfer count loaded to registers is 1 less than actual count
  30  *  - controller 2 offsets are all even (2x offsets for controller 1)
  31  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  32  *  - page registers for 0-3 use bit 0, represent 64K pages
  33  *
  34  * DMA transfers are limited to the lower 16MB of _physical_ memory.  
  35  * Note that addresses loaded into registers must be _physical_ addresses,
  36  * not logical addresses (which may differ if paging is active).
  37  *
  38  *  Address mapping for channels 0-3:
  39  *
  40  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  41  *    |  ...  |   |  ... |   |  ... |
  42  *    |  ...  |   |  ... |   |  ... |
  43  *    |  ...  |   |  ... |   |  ... |
  44  *   P7  ...  P0  A7 ... A0  A7 ... A0   
  45  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  46  *
  47  *  Address mapping for channels 5-7:
  48  *
  49  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  50  *    |  ...  |   \   \   ... \  \  \  ... \  \
  51  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  52  *    |  ...  |     \   \   ... \  \  \  ... \
  53  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
  54  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  55  *
  56  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  57  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  58  * the hardware level, so odd-byte transfers aren't possible).
  59  *
  60  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  61  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  62  * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
  63  *
  64  */
  65 
  66 #define MAX_DMA_CHANNELS        8
  67 
  68 /* 8237 DMA controllers */
  69 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  70 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  71 
  72 /* DMA controller registers */
  73 #define DMA1_CMD_REG            0x08    /* command register (w) */
  74 #define DMA1_STAT_REG           0x08    /* status register (r) */
  75 #define DMA1_REQ_REG            0x09    /* request register (w) */
  76 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  77 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  78 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  79 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  80 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
  81 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
  82 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
  83 
  84 #define DMA2_CMD_REG            0xD0    /* command register (w) */
  85 #define DMA2_STAT_REG           0xD0    /* status register (r) */
  86 #define DMA2_REQ_REG            0xD2    /* request register (w) */
  87 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
  88 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
  89 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
  90 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
  91 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
  92 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
  93 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
  94 
  95 #define DMA_ADDR_0              0x00    /* DMA address registers */
  96 #define DMA_ADDR_1              0x02
  97 #define DMA_ADDR_2              0x04
  98 #define DMA_ADDR_3              0x06
  99 #define DMA_ADDR_4              0xC0
 100 #define DMA_ADDR_5              0xC4
 101 #define DMA_ADDR_6              0xC8
 102 #define DMA_ADDR_7              0xCC
 103 
 104 #define DMA_CNT_0               0x01    /* DMA count registers */
 105 #define DMA_CNT_1               0x03
 106 #define DMA_CNT_2               0x05
 107 #define DMA_CNT_3               0x07
 108 #define DMA_CNT_4               0xC2
 109 #define DMA_CNT_5               0xC6
 110 #define DMA_CNT_6               0xCA
 111 #define DMA_CNT_7               0xCE
 112 
 113 #define DMA_PAGE_0              0x87    /* DMA page registers */
 114 #define DMA_PAGE_1              0x83
 115 #define DMA_PAGE_2              0x81
 116 #define DMA_PAGE_3              0x82
 117 #define DMA_PAGE_5              0x8B
 118 #define DMA_PAGE_6              0x89
 119 #define DMA_PAGE_7              0x8A
 120 
 121 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 122 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 123 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 124 
 125 /* enable/disable a specific DMA channel */
 126 static __inline__ void enable_dma(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 127 {
 128         if (dmanr<=3)
 129                 outb(dmanr,  DMA1_MASK_REG);
 130         else
 131                 outb(dmanr & 3,  DMA2_MASK_REG);
 132 }
 133 
 134 static __inline__ void disable_dma(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 135 {
 136         if (dmanr<=3)
 137                 outb(dmanr | 4,  DMA1_MASK_REG);
 138         else
 139                 outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 140 }
 141 
 142 /* Clear the 'DMA Pointer Flip Flop'.
 143  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 144  * Use this once to initialize the FF to a know state.
 145  * After that, keep track of it. :-)
 146  * --- In order to do that, the DMA routines below should ---
 147  * --- only be used while interrupts are disbled! ---
 148  */
 149 static __inline__ void clear_dma_ff(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 150 {
 151         if (dmanr<=3)
 152                 outb(0,  DMA1_CLEAR_FF_REG);
 153         else
 154                 outb(0,  DMA2_CLEAR_FF_REG);
 155 }
 156 
 157 /* set mode (above) for a specific DMA channel */
 158 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
     /* [previous][next][first][last][top][bottom][index][help] */
 159 {
 160         if (dmanr<=3)
 161                 outb(mode | dmanr,  DMA1_MODE_REG);
 162         else
 163                 outb(mode | (dmanr&3),  DMA2_MODE_REG);
 164 }
 165 
 166 /* Set only the page register bits of the transfer address.
 167  * This is used for successive transfers when we know the contents of
 168  * the lower 16 bits of the DMA current address register, but a 64k boundary
 169  * may have been crossed.
 170  */
 171 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
     /* [previous][next][first][last][top][bottom][index][help] */
 172 {
 173         switch(dmanr) {
 174                 case 0:
 175                         outb(pagenr, DMA_PAGE_0);
 176                         break;
 177                 case 1:
 178                         outb(pagenr, DMA_PAGE_1);
 179                         break;
 180                 case 2:
 181                         outb(pagenr, DMA_PAGE_2);
 182                         break;
 183                 case 3:
 184                         outb(pagenr, DMA_PAGE_3);
 185                         break;
 186                 case 5:
 187                         outb(pagenr & 0xfe, DMA_PAGE_5);
 188                         break;
 189                 case 6:
 190                         outb(pagenr & 0xfe, DMA_PAGE_6);
 191                         break;
 192                 case 7:
 193                         outb(pagenr & 0xfe, DMA_PAGE_7);
 194                         break;
 195         }
 196 }
 197 
 198 
 199 /* Set transfer address & page bits for specific DMA channel.
 200  * Assumes dma flipflop is clear.
 201  */
 202 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
     /* [previous][next][first][last][top][bottom][index][help] */
 203 {
 204         set_dma_page(dmanr, a>>16);
 205         if (dmanr <= 3)  {
 206             outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 207             outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 208         }  else  {
 209             outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 210             outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 211         }
 212 }
 213 
 214 
 215 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 216  * a specific DMA channel.
 217  * You must ensure the parameters are valid.
 218  * NOTE: from a manual: "the number of transfers is one more
 219  * than the initial word count"! This is taken into account.
 220  * Assumes dma flip-flop is clear.
 221  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 222  */
 223 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
     /* [previous][next][first][last][top][bottom][index][help] */
 224 {
 225         count--;
 226         if (dmanr <= 3)  {
 227             outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 228             outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 229         } else {
 230             outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 231             outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 232         }
 233 }
 234 
 235 
 236 /* Get DMA residue count. After a DMA transfer, this
 237  * should return zero. Reading this while a DMA transfer is
 238  * still in progress will return unpredictable results.
 239  * If called before the channel has been used, it may return 1.
 240  * Otherwise, it returns the number of _bytes_ left to transfer.
 241  *
 242  * Assumes DMA flip-flop is clear.
 243  */
 244 static __inline__ int get_dma_residue(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 245 {
 246         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 247                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 248 
 249         /* using short to get 16-bit wrap around */
 250         unsigned short count;
 251 
 252         count = 1 + inb(io_port);
 253         count += inb(io_port) << 8;
 254         
 255         return (dmanr<=3)? count : (count<<1);
 256 }
 257 
 258 
 259 /* These are in kernel/dma.c: */
 260 extern int request_dma(unsigned int dmanr);     /* reserve a DMA channel */
 261 extern void free_dma(unsigned int dmanr);       /* release it again */
 262 
 263 
 264 #endif /* _ASM_DMA_H */

/* [previous][next][first][last][top][bottom][index][help] */