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1 /* $Id: dma.h,v 1.5 1992/11/18 02:37:20 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8 #ifndef _ASM_DMA_H
9 #define _ASM_DMA_H
10
11 #include <asm/io.h> /* need byte IO */
12 #include <linux/kernel.h> /* need panic() [FIXME] */
13
14
15 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
16 #define outb outb_p
17 #endif
18
19 /*
20 * NOTES about DMA transfers:
21 *
22 * controller 1: channels 0-3, byte operations, ports 00-1F
23 * controller 2: channels 4-7, word operations, ports C0-DF
24 *
25 * - ALL registers are 8 bits only, regardless of transfer size
26 * - channel 4 is not used - cascades 1 into 2.
27 * - channels 0-3 are byte - addresses/counts are for physical bytes
28 * - channels 5-7 are word - addresses/counts are for physical words
29 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
30 * - transfer count loaded to registers is 1 less than actual count
31 * - controller 2 offsets are all even (2x offsets for controller 1)
32 * - page registers for 5-7 don't use data bit 0, represent 128K pages
33 * - page registers for 0-3 use bit 0, represent 64K pages
34 *
35 * DMA transfers are limited to the lower 16MB of _physical_ memory.
36 * Note that addresses loaded into registers must be _physical_ addresses,
37 * not logical addresses (which may differ if paging is active).
38 *
39 * Address mapping for channels 0-3:
40 *
41 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
42 * | ... | | ... | | ... |
43 * | ... | | ... | | ... |
44 * | ... | | ... | | ... |
45 * P7 ... P0 A7 ... A0 A7 ... A0
46 * | Page | Addr MSB | Addr LSB | (DMA registers)
47 *
48 * Address mapping for channels 5-7:
49 *
50 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
51 * | ... | \ \ ... \ \ \ ... \ \
52 * | ... | \ \ ... \ \ \ ... \ (not used)
53 * | ... | \ \ ... \ \ \ ... \
54 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
55 * | Page | Addr MSB | Addr LSB | (DMA registers)
56 *
57 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
58 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
59 * the hardware level, so odd-byte transfers aren't possible).
60 *
61 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
62 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
63 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
64 *
65 */
66
67 #define MAX_DMA_CHANNELS 8
68
69 /* 8237 DMA controllers */
70 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
71 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
72
73 /* DMA controller registers */
74 #define DMA1_CMD_REG 0x08 /* command register (w) */
75 #define DMA1_STAT_REG 0x08 /* status register (r) */
76 #define DMA1_REQ_REG 0x09 /* request register (w) */
77 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
78 #define DMA1_MODE_REG 0x0B /* mode register (w) */
79 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
80 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
81 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
82 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
83 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
84
85 #define DMA2_CMD_REG 0xD0 /* command register (w) */
86 #define DMA2_STAT_REG 0xD0 /* status register (r) */
87 #define DMA2_REQ_REG 0xD2 /* request register (w) */
88 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
89 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
90 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
91 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
92 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
93 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
94 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
95
96 #define DMA_ADDR_0 0x00 /* DMA address registers */
97 #define DMA_ADDR_1 0x02
98 #define DMA_ADDR_2 0x04
99 #define DMA_ADDR_3 0x06
100 #define DMA_ADDR_4 0xC0
101 #define DMA_ADDR_5 0xC4
102 #define DMA_ADDR_6 0xC8
103 #define DMA_ADDR_7 0xCC
104
105 #define DMA_CNT_0 0x01 /* DMA count registers */
106 #define DMA_CNT_1 0x03
107 #define DMA_CNT_2 0x05
108 #define DMA_CNT_3 0x07
109 #define DMA_CNT_4 0xC2
110 #define DMA_CNT_5 0xC6
111 #define DMA_CNT_6 0xCA
112 #define DMA_CNT_7 0xCE
113
114 #define DMA_PAGE_0 0x87 /* DMA page registers */
115 #define DMA_PAGE_1 0x83
116 #define DMA_PAGE_2 0x81
117 #define DMA_PAGE_3 0x82
118 #define DMA_PAGE_5 0x8B
119 #define DMA_PAGE_6 0x89
120 #define DMA_PAGE_7 0x8A
121
122 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
123 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
124 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
125
126 /* enable/disable a specific DMA channel */
127 static __inline__ void enable_dma(unsigned int dmanr)
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*/
128 {
129 if (dmanr<=3)
130 outb(dmanr, DMA1_MASK_REG);
131 else
132 outb(dmanr & 3, DMA2_MASK_REG);
133 }
134
135 static __inline__ void disable_dma(unsigned int dmanr)
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*/
136 {
137 if (dmanr<=3)
138 outb(dmanr | 4, DMA1_MASK_REG);
139 else
140 outb((dmanr & 3) | 4, DMA2_MASK_REG);
141 }
142
143 /* Clear the 'DMA Pointer Flip Flop'.
144 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
145 * Use this once to initialize the FF to a know state.
146 * After that, keep track of it. :-) In order to do that,
147 * dma_set_addr() and dma_set_count() should only be used wile
148 * interrupts are disbled.
149 */
150 static __inline__ void clear_dma_ff(unsigned int dmanr)
/* */
151 {
152 if (dmanr<=3)
153 outb(0, DMA1_CLEAR_FF_REG);
154 else
155 outb(0, DMA2_CLEAR_FF_REG);
156 }
157
158 /* set mode (above) for a specific DMA channel */
159 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
/* */
160 {
161 if (dmanr<=3)
162 outb(mode | dmanr, DMA1_MODE_REG);
163 else
164 outb(mode | (dmanr&3), DMA2_MODE_REG);
165 }
166
167 /* Set only the page register bits of the transfer address.
168 * This is used for successive transfers when we know the contents of
169 * the lower 16 bits of the DMA current address register, but a 64k boundary
170 * may have been crossed.
171 */
172 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
/* */
173 {
174 switch(dmanr) {
175 case 0:
176 outb(pagenr, DMA_PAGE_0);
177 break;
178 case 1:
179 outb(pagenr, DMA_PAGE_1);
180 break;
181 case 2:
182 outb(pagenr, DMA_PAGE_2);
183 break;
184 case 3:
185 outb(pagenr, DMA_PAGE_3);
186 break;
187 case 5:
188 outb(pagenr & 0xfe, DMA_PAGE_5);
189 break;
190 case 6:
191 outb(pagenr & 0xfe, DMA_PAGE_6);
192 break;
193 case 7:
194 outb(pagenr & 0xfe, DMA_PAGE_7);
195 break;
196 }
197 }
198
199
200 /* Set transfer address & page bits for specific DMA channel.
201 * Assumes dma flipflop is clear.
202 */
203 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
/* */
204 {
205 set_dma_page(dmanr, a>>16);
206 if (dmanr <= 3) {
207 outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
208 outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
209 } else {
210 outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
211 outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
212 }
213 }
214
215
216 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
217 * a specific DMA channel.
218 * You must ensure the parameters are valid.
219 * NOTE: from a manual: "the number of transfers is one more
220 * than the initial word count"! This is taken into account.
221 * Assumes dma flip-flop is clear.
222 * NOTE 2: "count" must represent _words_ for channels 5-7.
223 */
224 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
/* */
225 {
226 count--;
227 if (dmanr <= 3) {
228 outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
229 outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
230 } else {
231 outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
232 outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
233 }
234 }
235
236
237 /* Get DMA residue count. After a DMA transfer, this
238 * should return zero. Reading this while a DMA transfer is
239 * should return zero. Reading this while a DMA transfer is
240 * still in progress will return unpredictable results.
241 * If called before the channel has been used, it may return 1.
242 * Otherwise, it returns the number of bytes (or words) left to
243 * transfer, minus 1, modulo 64k.
244 * Assumes DMA flip-flop is clear.
245 */
246 static __inline__ short int get_dma_residue(unsigned int dmanr)
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*/
247 {
248 if (dmanr <= 3) {
249 return 1 + inb( ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ) +
250 (inb( ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ) << 8);
251 } else {
252 return 1 + inb( ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ) +
253 (inb( ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ) << 8);
254 }
255 }
256
257 /* These are in kernel/dma.c: */
258 extern int request_dma(unsigned int dmanr); /* reserve a DMA channel */
259 extern void free_dma(unsigned int dmanr); /* release it again */
260
261
262 #endif /* _ASM_DMA_H */
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*/