drivers/net/depca.h

/* */
   1 /*
   2     Written 1994 by David C. Davies.
   3 
   4     Copyright 1994 David C. Davies. This software may be used and distributed
   5     according to the terms of the GNU Public License, incorporated herein by
   6     reference.
   7 */
   8 
   9 /*
  10 ** I/O addresses. Note that the 2k buffer option is not supported in
  11 ** this driver.
  12 */
  13 #define DEPCA_NICSR ioaddr+0x00   /* Network interface CSR */
  14 #define DEPCA_RBI   ioaddr+0x02   /* RAM buffer index (2k buffer mode) */
  15 #define DEPCA_DATA  ioaddr+0x04   /* LANCE registers' data port */
  16 #define DEPCA_ADDR  ioaddr+0x06   /* LANCE registers' address port */
  17 #define DEPCA_PROM  ioaddr+0x0c   /* Ethernet address ROM data port */
  18 #define DEPCA_RBSA  ioaddr+0x0e   /* RAM buffer starting address (2k buff.) */
  19 
  20 /*
  21 ** These are LANCE registers addressable through DEPCA_ADDR 
  22 */
  23 #define CSR0       0
  24 #define CSR1       1
  25 #define CSR2       2
  26 #define CSR3       3
  27 
  28 /* 
  29 ** NETWORK INTERFACE CSR (NI_CSR) bit definitions 
  30 */
  31  
  32 #define TO              0x0100  /* Time Out for remote boot */
  33 #define SHE             0x0080  /* SHadow memory Enable */
  34 #define BS              0x0040  /* Bank Select */
  35 #define BUF             0x0020  /* BUFfer size (1->32k, 0->64k) */
  36 #define RBE             0x0010  /* Remote Boot Enable (1->net boot) */
  37 #define AAC             0x0008  /* for DEPCA family compatability */
  38 #define IM              0x0004  /* Interrupt Mask (1->mask) */
  39 #define IEN             0x0002  /* Interrupt tristate ENable (1->enable) */
  40 #define LED             0x0001  /* LED control */
  41 
  42 /* 
  43 ** Control and Status Register 0 (CSR0) bit definitions 
  44 */
  45 
  46 #define ERR             0x8000  /* Error summary */
  47 #define BABL            0x4000  /* Babble transmitter timeout error  */
  48 #define CERR            0x2000  /* Collision Error */
  49 #define MISS            0x1000  /* Missed packet */
  50 #define MERR            0x0800  /* Memory Error */
  51 #define RINT            0x0400  /* Receiver Interrupt */
  52 #define TINT            0x0200  /* Transmit Interrupt */
  53 #define IDON            0x0100  /* Initialization Done */
  54 #define INTR            0x0080  /* Interrupt Flag */
  55 #define INEA            0x0040  /* Interrupt Enable */
  56 #define RXON            0x0020  /* Receiver on */
  57 #define TXON            0x0010  /* Transmitter on */
  58 #define TDMD            0x0008  /* Transmit Demand */
  59 #define STOP            0x0004  /* Stop */
  60 #define STRT            0x0002  /* Start */
  61 #define INIT            0x0001  /* Initialize */
  62 
  63 /*
  64 ** CONTROL AND STATUS REGISTER 3 (CSR3)
  65 */
  66 
  67 #define BSWP            0x0004  /* Byte SWaP */
  68 #define ACON            0x0002  /* ALE control */
  69 #define BCON            0x0001  /* Byte CONtrol */
  70 
  71 /*
  72 ** Initialization Block Mode Register 
  73 */
  74 
  75 #define PROM            0x8000  /* Promiscuous Mode */
  76 #define EMBA            0x0080  /* Enable Modified Back-off Algorithm */
  77 #define INTL            0x0040  /* Internal Loopback */
  78 #define DRTY            0x0020  /* Disable Retry */
  79 #define COLL            0x0010  /* Force Collision */
  80 #define DTCR            0x0008  /* Disable Transmit CRC */
  81 #define LOOP            0x0004  /* Loopback */
  82 #define DTX             0x0002  /* Disable the Transmitter */
  83 #define DRX             0x0001  /* Disable the Receiver */
  84 
  85 /*
  86 ** Receive Message Descriptor 1 (RMD1) bit definitions. 
  87 */
  88 
  89 #define R_OWN       0x80000000  /* Owner bit 0 = host, 1 = lance */
  90 #define R_ERR           0x4000  /* Error Summary */
  91 #define R_FRAM          0x2000  /* Framing Error */
  92 #define R_OFLO          0x1000  /* Overflow Error */
  93 #define R_CRC           0x0800  /* CRC Error */
  94 #define R_BUFF          0x0400  /* Buffer Error */
  95 #define R_STP           0x0200  /* Start of Packet */
  96 #define R_ENP           0x0100  /* End of Packet */
  97 
  98 /*
  99 ** Transmit Message Descriptor 1 (TMD1) bit definitions. 
 100 */
 101 
 102 #define T_OWN       0x80000000  /* Owner bit 0 = host, 1 = lance */
 103 #define T_ERR           0x4000  /* Error Summary */
 104 #define T_ADD_FCS       0x2000  /* More the 1 retry needed to Xmit */
 105 #define T_MORE          0x1000  /* >1 retry to transmit packet */
 106 #define T_ONE           0x0800  /* 1 try needed to transmit the packet */
 107 #define T_DEF           0x0400  /* Deferred */
 108 #define T_STP       0x02000000  /* Start of Packet */
 109 #define T_ENP       0x01000000  /* End of Packet */
 110 
 111 /*
 112 ** Transmit Message Descriptor 3 (TMD3) bit definitions.
 113 */
 114 
 115 #define TMD3_BUFF    0x8000     /* BUFFer error */
 116 #define TMD3_UFLO    0x4000     /* UnderFLOw error */
 117 #define TMD3_RES     0x2000     /* REServed */
 118 #define TMD3_LCOL    0x1000     /* Late COLlision */
 119 #define TMD3_LCAR    0x0800     /* Loss of CARrier */
 120 #define TMD3_RTRY    0x0400     /* ReTRY error */
 121 
 122 /*
 123 ** Miscellaneous
 124 */
 125 
 126 #define MASK_INTERRUPTS   1
 127 #define UNMASK_INTERRUPTS 0
 128
/* */
root/drivers/net/depca.h

INCLUDED FROM
