drivers/scsi/aha152x.h

/* */
   1 #ifndef _AHA152X_H
   2 #define _AHA152X_H
   3 
   4 /*
   5  * $Id: aha152x.h,v 1.2 1994/07/03 13:01:47 root Exp $
   6  */
   7 
   8 #include "../block/blk.h"
   9 #include "scsi.h"
  10 #if defined(__KERNEL__)
  11 #include <asm/io.h>
  12 
  13 int        aha152x_detect(Scsi_Host_Template *);
  14 const char *aha152x_info(void);
  15 int        aha152x_command(Scsi_Cmnd *);
  16 int        aha152x_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  17 int        aha152x_abort(Scsi_Cmnd *);
  18 int        aha152x_reset(Scsi_Cmnd *);
  19 int        aha152x_biosparam(Disk *, int, int*);
  20 
  21 /* number of queueable commands
  22    (unless we support more than 1 cmd_per_lun this should do) */
  23 #define AHA152X_MAXQUEUE        7               
  24 
  25 #define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 1.2 $"
  26 
  27 /* Initial value of Scsi_Host entry */
  28 #define AHA152X       { /* next */              NULL,                       \
  29                         /* name */              AHA152X_REVID,              \
  30                         /* detect */            aha152x_detect,             \
  31                         /* release */           NULL,                       \
  32                         /* info */              aha152x_info,               \
  33                         /* command */           aha152x_command,            \
  34                         /* queuecommand */      aha152x_queue,              \
  35                         /* abort */             aha152x_abort,              \
  36                         /* reset */             aha152x_reset,              \
  37                         /* slave_attach */      /* NULL */  0,              \
  38                         /* bios_param */        aha152x_biosparam,          \
  39                         /* can_queue */         1,                          \
  40                         /* this_id */           7,                          \
  41                         /* sg_tablesize */      SG_ALL,                     \
  42                         /* cmd_per_lun */       1,                          \
  43                         /* present */           0,                          \
  44                         /* unchecked_isa_dma */ 0,                          \
  45                         /* use_clustering */    DISABLE_CLUSTERING }
  46 #endif
  47 
  48 
  49 /* port addresses */
  50 #define SCSISEQ         (port_base+0x00)        /* SCSI sequence control */
  51 #define SXFRCTL0        (port_base+0x01)        /* SCSI transfer control 0 */
  52 #define SXFRCTL1        (port_base+0x02)        /* SCSI transfer control 1 */
  53 #define SCSISIG         (port_base+0x03)        /* SCSI signal in/out */
  54 #define SCSIRATE        (port_base+0x04)        /* SCSI rate control */
  55 #define SELID           (port_base+0x05)        /* selection/reselection ID */
  56 #define SCSIID          SELID                   /* SCSI ID */
  57 #define SCSIDAT         (port_base+0x06)        /* SCSI latched data */
  58 #define SCSIBUS         (port_base+0x07)        /* SCSI data bus */
  59 #define STCNT0          (port_base+0x08)        /* SCSI transfer count 0 */
  60 #define STCNT1          (port_base+0x09)        /* SCSI transfer count 1 */
  61 #define STCNT2          (port_base+0x0a)        /* SCSI transfer count 2 */
  62 #define SSTAT0          (port_base+0x0b)        /* SCSI interrupt status 0 */
  63 #define SSTAT1          (port_base+0x0c)        /* SCSI interrupt status 1 */
  64 #define SSTAT2          (port_base+0x0d)        /* SCSI interrupt status 2 */
  65 #define SCSITEST        (port_base+0x0e)        /* SCSI test control */
  66 #define SSTAT4          (port_base+0x0f)        /* SCSI status 4 */
  67 #define SIMODE0         (port_base+0x10)        /* SCSI interrupt mode 0 */
  68 #define SIMODE1         (port_base+0x11)        /* SCSI interrupt mode 1 */
  69 #define DMACNTRL0       (port_base+0x12)        /* DMA control 0 */
  70 #define DMACNTRL1       (port_base+0x13)        /* DMA control 1 */
  71 #define DMASTAT         (port_base+0x14)        /* DMA status */
  72 #define FIFOSTAT        (port_base+0x15)        /* FIFO status */
  73 #define DATAPORT        (port_base+0x16)        /* DATA port */
  74 #define BRSTCNTRL       (port_base+0x18)        /* burst control */
  75 #define PORTA           (port_base+0x1a)        /* PORT A */
  76 #define PORTB           (port_base+0x1b)        /* PORT B */
  77 #define REV             (port_base+0x1c)        /* revision */
  78 #define STACK           (port_base+0x1d)        /* stack */
  79 #define TEST            (port_base+0x1e)        /* test register */
  80 
  81 
  82 /* bits and bitmasks to ports */
  83 
  84 /* SCSI sequence control */
  85 #define TEMODEO         0x80
  86 #define ENSELO          0x40
  87 #define ENSELI          0x20
  88 #define ENRESELI        0x10
  89 #define ENAUTOATNO      0x08
  90 #define ENAUTOATNI      0x04
  91 #define ENAUTOATNP      0x02
  92 #define SCSIRSTO        0x01
  93 
  94 /* SCSI transfer control 0 */
  95 #define SCSIEN          0x80
  96 #define DMAEN           0x40
  97 #define CH1             0x20
  98 #define CLRSTCNT        0x10
  99 #define SPIOEN          0x08
 100 #define CLRCH1          0x02
 101 
 102 /* SCSI transfer control 1 */
 103 #define BITBUCKET       0x80
 104 #define SWRAPEN         0x40
 105 #define ENSPCHK         0x20
 106 #define STIMESEL        0x18    /* mask */
 107 #define STIMESEL_       3
 108 #define ENSTIMER        0x04
 109 #define BYTEALIGN       0x02
 110 
 111 /* SCSI signal IN */
 112 #define CDI             0x80
 113 #define IOI             0x40
 114 #define MSGI            0x20
 115 #define ATNI            0x10
 116 #define SELI            0x08
 117 #define BSYI            0x04
 118 #define REQI            0x02
 119 #define ACKI            0x01
 120 
 121 /* SCSI Phases */
 122 #define P_MASK          (MSGI|CDI|IOI)
 123 #define P_DATAO         (0)
 124 #define P_DATAI         (IOI)
 125 #define P_CMD           (CDI)
 126 #define P_STATUS        (CDI|IOI)
 127 #define P_MSGO          (MSGI|CDI)
 128 #define P_MSGI          (MSGI|CDI|IOI)
 129 
 130 /* SCSI signal OUT */
 131 #define CDO             0x80
 132 #define IOO             0x40
 133 #define MSGO            0x20
 134 #define ATNO            0x10
 135 #define SELO            0x08
 136 #define BSYO            0x04
 137 #define REQO            0x02
 138 #define ACKO            0x01
 139 
 140 /* SCSI rate control */
 141 #define SXFR            0x70    /* mask */
 142 #define SXFR_           4
 143 #define SOFS            0x0f    /* mask */
 144 
 145 /* SCSI ID */
 146 #define OID             0x70
 147 #define OID_            4
 148 #define TID             0x07
 149 
 150 /* SCSI transfer count */
 151 #define GETSTCNT()   ( (GETPORT(STCNT2)<<16) \
 152                      + (GETPORT(STCNT1)<< 8) \
 153                      + GETPORT(STCNT0) )
 154 
 155 #define SETSTCNT(X)  { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
 156                        SETPORT(STCNT1, ((X) & 0x00FF00) >>  8); \
 157                        SETPORT(STCNT0, ((X) & 0x0000FF) ); }
 158 
 159 /* SCSI interrupt status */
 160 #define TARGET          0x80
 161 #define SELDO           0x40
 162 #define SELDI           0x20
 163 #define SELINGO         0x10
 164 #define SWRAP           0x08
 165 #define SDONE           0x04
 166 #define SPIORDY         0x02
 167 #define DMADONE         0x01
 168 
 169 #define SETSDONE        0x80
 170 #define CLRSELDO        0x40
 171 #define CLRSELDI        0x20
 172 #define CLRSELINGO      0x10
 173 #define CLRSWRAP        0x08
 174 #define CLRSDONE        0x04
 175 #define CLRSPIORDY      0x02
 176 #define CLRDMADONE      0x01
 177 
 178 /* SCSI status 1 */
 179 #define SELTO           0x80
 180 #define ATNTARG         0x40
 181 #define SCSIRSTI        0x20
 182 #define PHASEMIS        0x10
 183 #define BUSFREE         0x08
 184 #define SCSIPERR        0x04
 185 #define PHASECHG        0x02
 186 #define REQINIT         0x01
 187 
 188 #define CLRSELTIMO      0x80
 189 #define CLRATNO         0x40
 190 #define CLRSCSIRSTI     0x20
 191 #define CLRBUSFREE      0x08
 192 #define CLRSCSIPERR     0x04
 193 #define CLRPHASECHG     0x02
 194 #define CLRREQINIT      0x01
 195 
 196 /* SCSI status 2 */
 197 #define SOFFSET         0x20
 198 #define SEMPTY          0x10
 199 #define SFULL           0x08
 200 #define SFCNT           0x07    /* mask */
 201 
 202 /* SCSI status 3 */
 203 #define SCSICNT         0xf0    /* mask */
 204 #define SCSICNT_        4
 205 #define OFFCNT          0x0f    /* mask */
 206 
 207 /* SCSI TEST control */
 208 #define SCTESTU         0x08
 209 #define SCTESTD         0x04
 210 #define STCTEST         0x01
 211 
 212 /* SCSI status 4 */
 213 #define SYNCERR         0x04
 214 #define FWERR           0x02
 215 #define FRERR           0x01
 216 
 217 #define CLRSYNCERR      0x04
 218 #define CLRFWERR        0x02
 219 #define CLRFRERR        0x01
 220 
 221 /* SCSI interrupt mode 0 */
 222 #define ENSELDO         0x40
 223 #define ENSELDI         0x20
 224 #define ENSELINGO       0x10
 225 #define ENSWRAP         0x08
 226 #define ENSDONE         0x04
 227 #define ENSPIORDY       0x02
 228 #define ENDMADONE       0x01
 229 
 230 /* SCSI interrupt mode 1 */
 231 #define ENSELTIMO       0x80
 232 #define ENATNTARG       0x40
 233 #define ENSCSIRST       0x20
 234 #define ENPHASEMIS      0x10
 235 #define ENBUSFREE       0x08
 236 #define ENSCSIPERR      0x04
 237 #define ENPHASECHG      0x02
 238 #define ENREQINIT       0x01
 239 
 240 /* DMA control 0 */
 241 #define ENDMA           0x80
 242 #define _8BIT           0x40
 243 #define DMA             0x20
 244 #define WRITE_READ      0x08
 245 #define INTEN           0x04
 246 #define RSTFIFO         0x02
 247 #define SWINT           0x01
 248 
 249 /* DMA control 1 */
 250 #define PWRDWN          0x80
 251 #define STK             0x07    /* mask */
 252 
 253 /* DMA status */
 254 #define ATDONE          0x80
 255 #define WORDRDY         0x40
 256 #define INTSTAT         0x20
 257 #define DFIFOFULL       0x10
 258 #define DFIFOEMP        0x08
 259 
 260 /* BURST control */
 261 #define BON             0xf0
 262 #define BOFF            0x0f
 263 
 264 /* TEST REGISTER */
 265 #define BOFFTMR         0x40
 266 #define BONTMR          0x20
 267 #define STCNTH          0x10
 268 #define STCNTM          0x08
 269 #define STCNTL          0x04
 270 #define SCSIBLK         0x02
 271 #define DMABLK          0x01
 272 
 273 /* On the AHA-152x board PORTA and PORTB contain
 274    some information about the board's configuration. */
 275 typedef union {
 276   struct {
 277     unsigned reserved:2;        /* reserved */
 278     unsigned tardisc:1;         /* Target disconnect: 0=disabled, 1=enabled */
 279     unsigned syncneg:1;         /* Initial sync neg: 0=disabled, 1=enabled */
 280     unsigned msgclasses:2;      /* Message classes
 281                                    0=#4
 282                                    1=#0, #1, #2, #3, #4
 283                                    2=#0, #3, #4
 284                                    3=#0, #4
 285                                 */
 286     unsigned boot:1;            /* boot: 0=disabled, 1=enabled */
 287     unsigned dma:1;             /* Transfer mode: 0=PIO; 1=DMA */
 288     unsigned id:3;              /* SCSI-id */
 289     unsigned irq:2;             /* IRQ-Channel: 0,3=12, 1=10, 2=11 */
 290     unsigned dmachan:2;         /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */
 291     unsigned parity:1;          /* SCSI-parity: 1=enabled 0=disabled */
 292   } fields;
 293   unsigned short port;
 294 } aha152x_config ;
 295 
 296 #define cf_parity       fields.parity
 297 #define cf_dmachan      fields.dmachan
 298 #define cf_irq          fields.irq
 299 #define cf_id           fields.id
 300 #define cf_dma          fields.dma
 301 #define cf_boot         fields.boot
 302 #define cf_msgclasses   fields.msgclasses
 303 #define cf_syncneg      fields.syncneg
 304 #define cf_tardisc      fields.tardisc
 305 #define cf_port         port
 306 
 307 /* Some macros to manipulate ports and their bits */
 308 
 309 #define SETPORT(PORT, VAL)      \
 310         outb( (VAL), (PORT) )
 311 
 312 #define SETPORTP(PORT, VAL)     \
 313         outb_p( (VAL), (PORT) )
 314 
 315 #define SETPORTW(PORT, VAL)     \
 316         outw( (VAL), (PORT) )
 317 
 318 #define GETPORT(PORT)   \
 319         inb( PORT )
 320 
 321 #define GETPORTW(PORT)  \
 322         inw( PORT )
 323 
 324 #define SETBITS(PORT, BITS)     \
 325         outb( (inb(PORT) | (BITS)), (PORT) )
 326 
 327 #define CLRBITS(PORT, BITS)     \
 328         outb( (inb(PORT) & ~(BITS)), (PORT) )
 329 
 330 #define CLRSETBITS(PORT, CLR, SET)      \
 331         outb( (inb(PORT) & ~(CLR)) | (SET) , (PORT) )
 332 
 333 #define TESTHI(PORT, BITS)      \
 334         ((inb(PORT) & (BITS)) == BITS)
 335 
 336 #define TESTLO(PORT, BITS)      \
 337         ((inb(PORT) & (BITS)) == 0)
 338 
 339 #endif /* _AHA152X_H */
/* */
root/drivers/scsi/aha152x.h

INCLUDED FROM
