include/linux/pci.h

/* */
   1 /*
   2  * PCI defines and function prototypes
   3  * Copyright 1994, Drew Eckhardt
   4  *
   5  * For more information, please consult 
   6  * 
   7  * PCI BIOS Specification Revision
   8  * PCI Local Bus Specification
   9  * PCI System Design Guide
  10  *
  11  * PCI Special Interest Group
  12  * M/S HF3-15A
  13  * 5200 N.E. Elam Young Parkway
  14  * Hillsboro, Oregon 97124-6497
  15  * +1 (503) 696-2000 
  16  * +1 (800) 433-5177
  17  * 
  18  * Manuals are $25 each or $50 for all three, plus $7 shipping 
  19  * within the United States, $35 abroad.
  20  */
  21 
  22 #ifndef PCI_H
  23 #define PCI_H
  24 
  25 /* Configuration method #1 */
  26 #define PCI_CONFIG1_ADDRESS_REG  0xcf8
  27 #define PCI_CONFIG1_ENABLE 0x80000000
  28 #define PCI_CONFIG1_TUPPLE (bus, device, function, register)    \
  29         (PCI_CONFIG1_ENABLE | ((bus) << 16) & 0xff0000 |        \
  30         ((device) << 11) & 0xf800 | ((function) << 8) & 0x700 | \
  31         ((register) << 2) & 0xfc)
  32 #define PCI_CONFIG1_DATA_REG     0xcfc
  33 
  34 /* Configuration method #2, deprecated */
  35 #define PCI_CONFIG2_ENABLE_REG  0xcf8
  36 #define PCI_CONFIG2_ENABLE      0xf0
  37 #define PCI_CONFIG2_TUPPLE (function)                           \
  38         (PCI_CONFIG2_ENABLE | ((function) << 1) & 0xe)
  39 #define PCI_CONFIG2_FORWARD_REG 0xcfa
  40 
  41 /*
  42  * Under PCI, each device has 256 bytes of configuration address space,
  43  * of which the first 64 bytes is standardized as follows : 
  44  */
  45 
  46 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  47 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  48 #define PCI_COMMAND             0x04    /* 16 bits */
  49 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  50 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in I/O space */
  51 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  52 #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  53 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  54 #define  PCI_COMMAND_VGA_PALETTE        0x20    /* Enable palette snooping */
  55 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  56 #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  57 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  58 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  59 
  60 #define PCI_STATUS              0x06    /* 16 bits */
  61 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  62 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  63 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  64 #define  PCI_STATUS_DEVSEL_FAST 0x000   
  65 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  66 #define  PCI_STATUS_DEVESEL_SLOW 0x400
  67 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  68 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  69 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  70 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  71 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  72 
  73 #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
  74                                            revision */
  75 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  76 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  77 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  78 #define PCI_BIST                0x0f    /* 8 bits */
  79 #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
  80 #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
  81 #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
  82 
  83 /*
  84  * Base addresses specify locations in memory or I/O space.
  85  * Decoded size can be determined by writing a value of 
  86  * 0xffffffff to the register, and reading it back.  Only 
  87  * 1 bits are decoded.
  88  */
  89 
  90 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  91 #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
  92 #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
  93 #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  94 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  95 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
  96 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
  97 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
  98 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  99 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 100 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
 101 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
 102 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 103 #define  PCI_BASE_ADDRESS_MEM_MASK      ~7
 104 #define  PCI_BASE_ADDRESS_IO_MASK       ~3
 105 /* bit 1 is reserved if address_space = 1 */
 106 
 107 /* 0x28-0x2f are reserved */
 108 #define PCI_ROM_ADDRESS         0x30    /* 32 bits */
 109 #define  PCI_ROM_ADDRESS_ENABLE 0x01    /* Write 1 to enable ROM,
 110                                            bits 31..11 are address,
 111                                            10..2 are reserved */
 112 /* 0x34-0x3b are reserved */
 113 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 114 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 115 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 116 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 117 
 118 #define PCI_VENDOR_ID_NCR               0x1000
 119 #define PCI_DEVICE_ID_NCR_53C810        0x0001
 120 #define PCI_DEVICE_ID_NCR_53C820        0x0002
 121 #define PCI_DEVICE_ID_NCR_53C825        0x0003
 122 
 123 /* PCI BIOS */
 124 
 125 extern int pcibios_present (void);
 126 
 127 #define PCIBIOS_SUCCESSFUL              0x00
 128 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
 129 #define PCIBIOS_BAD_VENDOR_ID           0x83
 130 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
 131 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
 132 
 133 /*
 134  * The PCIBIOS calls all bit-field the device_function variable such that 
 135  * the bit fielding matches that of the bl register used in the actual
 136  * calls.
 137  */
 138 
 139 extern int pcibios_find_class (unsigned long class_code, unsigned short index, 
 140     unsigned char *bus, unsigned char *device_fn);
 141 extern int pcibios_find_device (unsigned short vendor, unsigned short device_id, 
 142     unsigned short index, unsigned char *bus, unsigned char *device_fn);
 143 extern int pcibios_read_config_byte (unsigned char bus,
 144     unsigned char device_fn, unsigned char where, unsigned char *value);
 145 extern int pcibios_read_config_word (unsigned char bus,
 146     unsigned char device_fn, unsigned char where, unsigned short *value);
 147 extern int pcibios_read_config_dword (unsigned char bus,
 148     unsigned char device_fn, unsigned char where, unsigned long *value);
 149 extern char *pcibios_strerror (int error);
 150 extern int pcibios_write_config_byte (unsigned char bus,
 151     unsigned char device_fn, unsigned char where, unsigned char value);
 152 extern int pcibios_write_config_word (unsigned char bus,
 153     unsigned char device_fn, unsigned char where, unsigned short value);
 154 extern pcibios_write_config_dword (unsigned char bus,
 155     unsigned char device_fn, unsigned char where, unsigned long value);
 156 #endif /* ndef PCI_H */
/* */
root/include/linux/pci.h

INCLUDED FROM
