![[bottom]](../icons/bottom.png){kind=icon}
![[previous]](../icons/n_left.png){kind=icon}
![[next]](../icons/n_right.png){kind=icon}
![[first]](../icons/n_first.png){kind=icon}
![[last]](../icons/n_last.png){kind=icon}
![[top]](../icons/n_top.png){kind=icon}
![[index]](../icons/index.png){kind=icon}
![[help]](../icons/help.png){kind=icon}
*/
1 /*
2 * NCR 53c{7,8}0x0 driver, header file
3 *
4 * Sponsored by
5 * iX Multiuser Multitasking Magazine
6 * Hannover, Germany
7 * hm@ix.de
8 *
9 * Copyright 1993, Drew Eckhardt
10 * Visionary Computing
11 * (Unix and Linux consulting and custom programming)
12 * drew@Colorado.EDU
13 * +1 (303) 786-7975
14 *
15 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
16 *
17 * PRE-ALPHA
18 *
19 * For more information, please consult
20 *
21 * NCR 53C700/53C700-66
22 * SCSI I/O Processor
23 * Data Manual
24 *
25 * NCR 53C810
26 * PCI-SCSI I/O Processor
27 * Data Manual
28 *
29 * NCR Microelectronics
30 * 1635 Aeroplaza Drive
31 * Colorado Springs, CO 80916
32 * +1 (719) 578-3400
33 *
34 * Toll free literature number
35 * +1 (800) 334-5454
36 *
37 */
38
39 #ifndef NCR53c7x0_H
40 #define NCR53c7x0_H
41
42
43 /*
44 * Prevent name space pollution in hosts.c, and only provide the
45 * define we need to get the NCR53c7x0 driver into the host template
46 * array.
47 */
48
49 #ifdef HOSTS_C
50 #include <linux/scsicam.h>
51 extern int NCR53c7xx_abort(Scsi_Cmnd *);
52 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
53 extern const char *NCR53c7xx_info(void);
54 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
55 extern int NCR53c7xx_reset(Scsi_Cmnd *);
56
57 #define NCR53c7xx {NULL, "NCR53c{7,8}xx (rel 3)", NCR53c7xx_detect, \
58 NULL, NCR53c7xx_info, \
59 NULL, NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset,\
60 NULL, scsicam_bios_param, \
61 /* can queue */ 1, /* id */ 7, 255 /* old SG_ALL */, \
62 /* cmd per lun */ 1 , 0, 0, DISABLE_CLUSTERING}
63 #else
64 /* Register addresses, ordered numerically */
65
66
67 /* SCSI control 0 rw, default = 0xc0 */
68 #define SCNTL0_REG 0x00
69 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
70 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
71 #define SCNTL0_STRT 0x20 /* Start Sequence */
72 #define SCNTL0_WATN 0x10 /* Select with ATN */
73 #define SCNTL0_EPC 0x08 /* Enable parity checking */
74 /* Bit 2 is reserved on 800 series chips */
75 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
76 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
77 #define SCNTL0_TRG 0x01 /* Target mode */
78
79 /* SCSI control 1 rw, default = 0x00 */
80
81 #define SCNTL1_REG 0x01
82 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
83 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
84 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
85 and reselection */
86 #define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
87 target mode only */
88 #define SCNTL1_CON 0x10 /* Connected */
89 #define SCNTL1_RST 0x08 /* SCSI RST/ */
90 #define SCNTL1_AESP 0x04 /* Force bad parity */
91 #define SCNTL1_SND_700 0x02 /* Start SCSI send */
92 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
93 arbitration immediately after
94 busfree is detected */
95 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
96 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
97
98 /* SCSI control 2 rw, */
99
100 #define SCNTL2_REG_800 0x02
101 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
102
103 /* SCSI control 3 rw */
104
105 #define SCNTL3_REG_800 0x03
106 #define SCNTL3_800_SCF_SHIFT 4
107 #define SCNTL3_800_SCF_MASK 0x70
108 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
109 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
110 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
111 /* 0x20 = SCLK/1.5
112 0x30 = SCLK/2
113 0x40 = SCLK/3 */
114
115 #define SCNTL3_800_CCF_SHIFT 0
116 #define SCNTL3_800_CCF_MASK 0x07
117 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
118 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
119 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
120 0x03 37.51 - 50
121 0x04 50.01 - 66 */
122
123 /*
124 * SCSI destination ID rw - the appropriate bit is set for the selected
125 * target ID. This is written by the SCSI SCRIPTS processor.
126 * default = 0x00
127 */
128 #define SDID_REG_700 0x02
129 #define SDID_REG_800 0x06
130
131 #define GP_REG_800 0x07 /* General purpose IO */
132 #define GP_800_IO1 0x02
133 #define GP_800_IO2 0x01
134
135
136 /* SCSI interrupt enable rw, default = 0x00 */
137 #define SIEN_REG_700 0x03
138 #define SIEN0_REG_800 0x40
139 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
140 #define SIEN_FC 0x40 /* Function complete */
141 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
142 #define SIEN_800_SEL 0x20 /* Selected */
143 #define SIEN_700_SEL 0x10 /* Selected or reselected */
144 #define SIEN_800_RESEL 0x10 /* Reselected */
145 #define SIEN_SGE 0x08 /* SCSI gross error */
146 #define SIEN_UDC 0x04 /* Unexpected disconnect */
147 #define SIEN_RST 0x02 /* SCSI RST/ received */
148 #define SIEN_PAR 0x01 /* Parity error */
149
150 /*
151 * SCSI chip ID rw
152 * NCR53c700 :
153 * When arbitrating, the highest bit is used, when reselection or selection
154 * occurs, the chip responds to all IDs for which a bit is set.
155 * default = 0x00
156 * NCR53c810 :
157 * Uses bit mapping
158 */
159 #define SCID_REG 0x04
160 /* Bit 7 is reserved on 800 series chips */
161 #define SCID_800_RRE 0x40 /* Enable response to reselection */
162 #define SCID_800_SRE 0x20 /* Enable response to selection */
163 /* Bits four and three are reserved on 800 series chips */
164 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
165
166 /* SCSI transfer rw, default = 0x00 */
167 #define SXFER_REG 0x05
168 #define SXFER_DHP 0x80 /* Disable halt on parity */
169
170 #define SXFER_TP2 0x40 /* Transfer period msb */
171 #define SXFER_TP1 0x20
172 #define SXFER_TP0 0x10 /* lsb */
173 #define SXFER_TP_MASK 0x70
174 #define SXFER_TP_SHIFT 4
175 #define SXFER_TP_4 0x00 /* Divisors */
176 #define SXFER_TP_5 0x10
177 #define SXFER_TP_6 0x20
178 #define SXFER_TP_7 0x30
179 #define SXFER_TP_8 0x40
180 #define SXFER_TP_9 0x50
181 #define SXFER_TP_10 0x60
182 #define SXFER_TP_11 0x70
183
184 #define SXFER_MO3 0x08 /* Max offset msb */
185 #define SXFER_MO2 0x04
186 #define SXFER_MO1 0x02
187 #define SXFER_MO0 0x01 /* lsb */
188 #define SXFER_MO_MASK 0x0f
189 #define SXFER_MO_SHIFT 0
190
191 /*
192 * SCSI output data latch rw
193 * The contents of this register are driven onto the SCSI bus when
194 * the Assert Data Bus bit of the SCNTL1 register is set and
195 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
196 */
197 #define SODL_REG_700 0x06
198 #define SODL_REG_800 0x54
199
200
201 /*
202 * SCSI output control latch rw, default = 0
203 * Note that when the chip is being manually programmed as an initiator,
204 * the MSG, CD, and IO bits must be set correctly for the phase the target
205 * is driving the bus in. Otherwise no data transfer will occur due to
206 * phase mismatch.
207 */
208
209 #define SBCL_REG 0x0b
210 #define SBCL_REQ 0x80 /* REQ */
211 #define SBCL_ACK 0x40 /* ACK */
212 #define SBCL_BSY 0x20 /* BSY */
213 #define SBCL_SEL 0x10 /* SEL */
214 #define SBCL_ATN 0x08 /* ATN */
215 #define SBCL_MSG 0x04 /* MSG */
216 #define SBCL_CD 0x02 /* C/D */
217 #define SBCL_IO 0x01 /* I/O */
218 #define SBCL_PHASE_CMDOUT SBCL_CD
219 #define SBCL_PHASE_DATAIN SBCL_IO
220 #define SBCL_PHASE_DATAOUT 0
221 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
222 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
223 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
224 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
225
226 /*
227 * SCSI first byte received latch ro
228 * This register contains the first byte received during a block MOVE
229 * SCSI SCRIPTS instruction, including
230 *
231 * Initiator mode Target mode
232 * Message in Command
233 * Status Message out
234 * Data in Data out
235 *
236 * It also contains the selecting or reselecting device's ID and our
237 * ID.
238 *
239 * Note that this is the register the various IF conditionals can
240 * operate on.
241 */
242 #define SFBR_REG 0x08
243
244 /*
245 * SCSI input data latch ro
246 * In initiator mode, data is latched into this register on the rising
247 * edge of REQ/. In target mode, data is latched on the rising edge of
248 * ACK/
249 */
250 #define SIDL_REG_700 0x09
251 #define SIDL_REG_800 0x50
252
253 /*
254 * SCSI bus data lines ro
255 * This register reflects the instantaneous status of the SCSI data
256 * lines. Note that SCNTL0 must be set to disable parity checking,
257 * otherwise reading this register will latch new parity.
258 */
259 #define SBDL_REG_700 0x0a
260 #define SBDL_REG_800 0x58
261
262 #define SSID_REG_800 0x0a
263 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
264 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
265
266
267 /*
268 * SCSI bus control lines rw,
269 * instantaneous readout of control lines
270 */
271 #define SOCL_REG 0x0b
272 #define SOCL_REQ 0x80 /* REQ ro */
273 #define SOCL_ACK 0x40 /* ACK ro */
274 #define SOCL_BSY 0x20 /* BSY ro */
275 #define SOCL_SEL 0x10 /* SEL ro */
276 #define SOCL_ATN 0x08 /* ATN ro */
277 #define SOCL_MSG 0x04 /* MSG ro */
278 #define SOCL_CD 0x02 /* C/D ro */
279 #define SOCL_IO 0x01 /* I/O ro */
280 /*
281 * Synchronous SCSI Clock Control bits
282 * 0 - set by DCNTL
283 * 1 - SCLK / 1.0
284 * 2 - SCLK / 1.5
285 * 3 - SCLK / 2.0
286 */
287 #define SBCL_SSCF1 0x02 /* wo, -66 only */
288 #define SBCL_SSCF0 0x01 /* wo, -66 only */
289 #define SBCL_SSCF_MASK 0x03
290
291 /*
292 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
293 * insure that 10 clocks elapse between the two
294 */
295 /* DMA status ro */
296 #define DSTAT_REG 0x0c
297 #define DSTAT_DFE 0x80 /* DMA FIFO empty */
298 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
299 #define DSTAT_800_BF 0x20 /* Bus Fault */
300 #define DSTAT_ABRT 0x10 /* Aborted - set on error */
301 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
302 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
303 set when INT instruction is
304 executed */
305 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
306 #define DSTAT_OPC 0x01 /* Illegal instruction */
307 #define DSTAT_800_IID 0x01 /* Same thing, different name */
308
309
310 #define SSTAT0_REG 0x0d /* SCSI status 0 ro */
311 #define SIST0_REG_800 0x42
312 #define SSTAT0_MA 0x80 /* ini : phase mismatch,
313 * tgt : ATN/ asserted
314 */
315 #define SSTAT0_CMP 0x40 /* function complete */
316 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
317 #define SIST0_800_SEL 0x20 /* Selected */
318 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
319 #define SIST0_800_RSL 0x10 /* Reselected */
320 #define SSTAT0_SGE 0x08 /* SCSI gross error */
321 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
322 #define SSTAT0_RST 0x02 /* SCSI RST/ received */
323 #define SSTAT0_PAR 0x01 /* Parity error */
324
325 #define SSTAT1_REG 0x0e /* SCSI status 1 ro */
326 #define SSTAT1_ILF 0x80 /* SIDL full */
327 #define SSTAT1_ORF 0x40 /* SODR full */
328 #define SSTAT1_OLF 0x20 /* SODL full */
329 #define SSTAT1_AIP 0x10 /* Arbitration in progress */
330 #define SSTAT1_LOA 0x08 /* Lost arbitration */
331 #define SSTAT1_WOA 0x04 /* Won arbitration */
332 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
333 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
334
335 #define SSTAT2_REG 0x0f /* SCSI status 2 ro */
336 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
337 #define SSTAT2_FF2 0x40 /* data FIFO */
338 #define SSTAT2_FF1 0x20
339 #define SSTAT2_FF0 0x10
340 #define SSTAT2_FF_MASK 0xf0
341
342 /*
343 * Latched signals, latched on the leading edge of REQ/ for initiators,
344 * ACK/ for targets.
345 */
346 #define SSTAT2_SDP 0x08 /* SDP */
347 #define SSTAT2_MSG 0x04 /* MSG */
348 #define SSTAT2_CD 0x02 /* C/D */
349 #define SSTAT2_IO 0x01 /* I/O */
350
351
352 /* NCR53c700-66 only */
353 #define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
354 /* NCR53c710 and higher */
355 #define DSA_REG 0x10 /* DATA structure address */
356
357 #define CTEST0_REG_700 0x14 /* Chip test 0 ro */
358 #define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
359 /* 0x80 - 0x04 are reserved */
360 #define CTEST0_700_RTRG 0x02 /* Real target mode */
361 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
362 * SCSI bus to host, 0 =
363 * host to SCSI.
364 */
365
366 #define CTEST1_REG_700 0x15 /* Chip test 1 ro */
367 #define CTEST1_REG_800 0x19 /* Chip test 1 ro */
368 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
369 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
370 #define CTEST1_FMT1 0x20
371 #define CTEST1_FMT0 0x10
372
373 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
374 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
375 #define CTEST1_FFL1 0x02
376 #define CTEST1_FFL0 0x01
377
378 #define CTEST2_REG_700 0x16 /* Chip test 2 ro */
379 #define CTEST2_REG_800 0x1a /* Chip test 2 ro */
380
381 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
382 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
383 Reading this register clears */
384 #define CTEST2_800_CIO 0x20 /* Configured as IO */.
385 #define CTEST2_800_CM 0x10 /* Configured as memory */
386
387 /* 0x80 - 0x40 are reserved on 700 series chips */
388 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
389 * As an initiator, this bit is
390 * one when the synchronous offset
391 * is zero, as a target this bit
392 * is one when the synchronous
393 * offset is at the maximum
394 * defined in SXFER
395 */
396 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
397 * reading CTEST3 unloads a byte
398 * from the FIFO and sets this
399 */
400 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
401 * reading CTEST6 unloads a byte
402 * from the FIFO and sets this
403 */
404 #define CTEST2_TEOP 0x04 /* SCSI true end of process,
405 * indicates a totally finished
406 * transfer
407 */
408 #define CTEST2_DREQ 0x02 /* Data request signal */
409 /* 0x01 is reserved on 700 series chips */
410 #define CTEST2_800_DACK 0x01
411
412 /*
413 * Chip test 3 ro
414 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
415 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
416 * error results if a read is attempted on this register. Also note
417 * that 16 and 32 bit reads of this register will cause corruption.
418 */
419 #define CTEST3_REG_700 0x17
420 /* Chip test 3 rw */
421 #define CTEST3_REG_800 0x1b
422 #define CTEST3_800_V3 0x80 /* Chip revision */
423 #define CTEST3_800_V2 0x40
424 #define CTEST3_800_V1 0x20
425 #define CTEST3_800_V0 0x10
426 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
427 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
428 #define CTEST3_800_FM 0x02 /* Fetch mode pin */
429 /* bit 0 is reserved on 800 series chips */
430
431 #define CTEST4_REG_700 0x18 /* Chip test 4 rw */
432 #define CTEST4_REG_800 0x21 /* Chip test 4 rw */
433 /* 0x80 is reserved on 700 series chips */
434 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
435 #define CTEST4_ZMOD 0x40 /* High impedance mode */
436 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
437 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
438 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
439 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
440 * redirects writes from SODL
441 * to the SCSI FIFO.
442 */
443 #define CTEST4_800_MPEE 0x08 /* Enable parity checking
444 during master cycles on PCI
445 bus */
446
447 /*
448 * These bits send the contents of the CTEST6 register to the appropriate
449 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
450 * the high bit means the low two bits select the byte lane.
451 */
452 #define CTEST4_FBL2 0x04
453 #define CTEST4_FBL1 0x02
454 #define CTEST4_FBL0 0x01
455 #define CTEST4_FBL_MASK 0x07
456 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
457 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
458 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
459 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
460 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
461
462
463 #define CTEST5_REG_700 0x19 /* Chip test 5 rw */
464 #define CTEST5_REG_800 0x22 /* Chip test 5 rw */
465 /*
466 * Clock Address Incrementor. When set, it increments the
467 * DNAD register to the next bus size boundary. It automatically
468 * resets itself when the operation is complete.
469 */
470 #define CTEST5_ADCK 0x80
471 /*
472 * Clock Byte Counter. When set, it decrements the DBC register to
473 * the next bus size boundary.
474 */
475 #define CTEST5_BBCK 0x40
476 /*
477 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
478 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
479 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
480 * be cleared when a synchronous transfer fails. When written, it is
481 * automatically cleared after the SCSI synchronous offset counter is
482 * reset.
483 */
484 /* Bit 5 is reserved on 800 series chips */
485 #define CTEST5_700_ROFF 0x20
486 /*
487 * Master Control for Set or Reset pulses. When 1, causes the low
488 * four bits of register to set when set, 0 causes the low bits to
489 * clear when set.
490 */
491 #define CTEST5_MASR 0x10
492 #define CTEST5_DDIR 0x08 /* DMA direction */
493 /*
494 * Bits 2-0 are reserved on 800 series chips
495 */
496 #define CTEST5_700_EOP 0x04 /* End of process */
497 #define CTEST5_700_DREQ 0x02 /* Data request */
498 #define CTEST5_700_DACK 0x01 /* Data acknowledge */
499
500 /*
501 * Chip test 6 rw - writing to this register writes to the byte
502 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
503 * register.
504 */
505 #define CTEST6_REG_700 0x1a
506 #define CTEST6_REG_800 0x23
507
508 #define CTEST7_REG 0x1b /* Chip test 7 rw */
509 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
510 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
511 #define CTEST7_10_SC1 0x40 /* Snoop control bits */
512 #define CTEST7_10_SC0 0x20
513 #define CTEST7_10_SC_MASK 0x60
514 /* 0x20 is reserved on the NCR53c700 */
515 #define CTEST7_0060_FM 0x20 /* Fetch mode */
516 #define CTEST7_STD 0x10 /* Selection timeout disable */
517 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
518 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
519 #define CTEST7_10_TT1 0x02 /* Transfer type */
520 #define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
521 fetch */
522 #define CTEST7_DIFF 0x01 /* Differential mode */
523
524 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
525
526
527 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
528
529 #define DFIFO_REG 0x20 /* DMA FIFO rw */
530 /*
531 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
532 * moved into the CTEST8 register.
533 */
534 #define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
535 #define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
536 #define DFIFO_BO6 0x40
537 #define DFIFO_BO5 0x20
538 #define DFIFO_BO4 0x10
539 #define DFIFO_BO3 0x08
540 #define DFIFO_BO2 0x04
541 #define DFIFO_BO1 0x02
542 #define DFIFO_BO0 0x01
543 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
544 #define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
545
546 /*
547 * Interrupt status rw
548 * Note that this is the only register which can be read while SCSI
549 * SCRIPTS are being executed.
550 */
551 #define ISTAT_REG_700 0x21
552 #define ISTAT_REG_800 0x14
553 #define ISTAT_ABRT 0x80 /* Software abort, write
554 *1 to abort, wait for interrupt. */
555 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
556 #define ISTAT_10_SRST 0x40 /* software reset */
557 #define ISTAT_10_SIGP 0x20 /* signal script */
558 /* 0x10 is reserved on NCR53c700 series chips */
559 #define ISTAT_800_SEM 0x10 /* semaphore */
560 #define ISTAT_CON 0x08 /* 1 when connected */
561 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
562 #define ISTAT_700_PRE 0x04 /* Pointer register empty.
563 * Set to 1 when DSPS and DSP
564 * registers are empty in pipeline
565 * mode, always set otherwise.
566 */
567 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
568 * SCSI portion of SIOP see
569 * SSTAT0
570 */
571 #define ISTAT_DIP 0x01 /* DMA interrupt pending
572 * see DSTAT
573 */
574
575 /* NCR53c700-66 and NCR53c710 only */
576 #define CTEST8_REG 0x22 /* Chip test 8 rw */
577 #define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
578 * ie read from SCLK/ rather than CLK/
579 */
580 #define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
581 #define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
582 * pass through. This insures that
583 * bad parity won't reach the host
584 * bus.
585 */
586 #define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
587 * active negation, should only
588 * be used for slow SCSI
589 * non-differential.
590 */
591 #define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
592 #define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
593 * must be set for fast SCSI-II
594 * speeds.
595 */
596 #define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
597 * switching.
598 */
599 #define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
600 * The status of pending
601 * disconnect is maintained by
602 * the core, eliminating
603 * the possibility of missing a
604 * selection or reselection
605 * while waiting to fetch a
606 * WAIT DISCONNECT opcode.
607 */
608
609 #define CTEST8_10_V3 0x80 /* Chip revision */
610 #define CTEST8_10_V2 0x40
611 #define CTEST8_10_V1 0x20
612 #define CTEST8_10_V0 0x10
613 #define CTEST8_10_V_MASK 0xf0
614 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
615 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
616 #define CTEST8_10_FM 0x02 /* Fetch pin mode */
617 #define CTEST8_10_SM 0x01 /* Snoop pin mode */
618
619
620 /*
621 * The CTEST9 register may be used to differentiate between a
622 * NCR53c700 and a NCR53c710.
623 *
624 * Write 0xff to this register.
625 * Read it.
626 * If the contents are 0xff, it is a NCR53c700
627 * If the contents are 0x00, it is a NCR53c700-66 first revision
628 * If the contents are some other value, it is some other NCR53c700-66
629 */
630 #define CTEST9_REG_00 0x23 /* Chip test 9 ro */
631 #define LCRC_REG_10 0x23
632
633 /*
634 * 0x24 through 0x27 are the DMA byte counter register. Instructions
635 * write their high 8 bits into the DCMD register, the low 24 bits into
636 * the DBC register.
637 *
638 * Function is dependent on the command type being executed.
639 */
640
641
642 #define DBC_REG 0x24
643 /*
644 * For Block Move Instructions, DBC is a 24 bit quantity representing
645 * the number of bytes to transfer.
646 * For Transfer Control Instructions, DBC is bit fielded as follows :
647 */
648 /* Bits 20 - 23 should be clear */
649 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
650 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
651 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
652 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
653 /* Bits 8 - 15 are reserved on some implementations ? */
654 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
655 #define DBC_TCI_MASK_SHIFT 8
656 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
657 #define DBC_TCI_DATA_SHIFT 0
658
659 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
660 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
661 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
662 #define DBC_RWRI_ADDRESS_SHIFT 16
663
664
665 /*
666 * DMA command r/w
667 */
668 #define DCMD_REG 0x27
669 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
670 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
671 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
672 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
673 #define DCMD_BMI_MSG 0x04 /* instruction */
674
675 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
676 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
677 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
678
679 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
680
681 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
682 instruction */
683 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
684 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
685 #define DCMD_TCI_MSG 0x04 /* instruction */
686 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
687 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
688 #define DCMD_TCI_OP_CALL 0x08 /* CALL */
689 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
690 #define DCMD_TCI_OP_INT 0x18 /* INT */
691
692 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
693 instruction */
694 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
695 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
696 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
697 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
698
699 #define DCMD_RWRI_OP_MASK 0x07
700 #define DCMD_RWRI_OP_MOVE 0x00
701 #define DCMD_RWRI_OP_SHL 0x01
702 #define DCMD_RWRI_OP_OR 0x02
703 #define DCMD_RWRI_OP_XOR 0x03
704 #define DCMD_RWRI_OP_AND 0x04
705 #define DCMD_RWRI_OP_SHR 0x05
706 #define DCMD_RWRI_OP_ADD 0x06
707 #define DCMD_RWRI_OP_ADDC 0x07
708
709 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
710 (three longs) */
711
712
713 #define DNAD_REG 0x28 /* through 0x2b DMA next address for
714 data */
715 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
716 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
717 save rw */
718 #define DMODE_REG_00 0x34 /* DMA mode rw */
719 #define DMODE_00_BL1 0x80 /* Burst length bits */
720 #define DMODE_00_BL0 0x40
721 #define DMODE_BL_MASK 0xc0
722 /* Burst lengths (800) */
723 #define DMODE_BL_2 0x00 /* 2 transfer */
724 #define DMODE_BL_4 0x40 /* 4 transfers */
725 #define DMODE_BL_8 0x80 /* 8 transfers */
726 #define DMODE_BL_16 0xc0 /* 16 transfers */
727
728 #define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
729 #define DMODE_700_286 0x10 /* 286 mode */
730 #define DMODE_700_IOM 0x08 /* Transfer to IO port */
731 #define DMODE_700_FAM 0x04 /* Fixed address mode */
732 #define DMODE_700_PIPE 0x02 /* Pipeline mode disables
733 * automatic fetch / exec
734 */
735 #define DMODE_MAN 0x01 /* Manual start mode,
736 * requires a 1 to be written
737 * to the start DMA bit in the DCNTL
738 * register to run scripts
739 */
740
741 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
742
743 /* NCR53c800 series only */
744 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
745 /* NCR53c710 only */
746 #define SCRATCB_REG_10 0x34 /* through 0x37 scratch B rw */
747
748 #define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
749 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
750 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
751 #define DMODE_800_ERL 0x08 /* Enable Read Line */
752
753 /* 35-38 are reserved on 700 and 700-66 series chips */
754 #define DIEN_REG 0x39 /* DMA interrupt enable rw */
755 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
756 #define DIEN_800_MDPE 0x40 /* Master data parity error */
757 #define DIEN_800_BF 0x20 /* BUS fault */
758 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
759 #define DIEN_SSI 0x08 /* Enable single step interrupt */
760 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
761 * interrupt
762 */
763 /* 0x02 is reserved on 800 series chips */
764 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
765 #define DIEN_700_OPC 0x01 /* Enable illegal instruction
766 * interrupt
767 */
768 #define DIEN_800_IID 0x01 /* Same meaning, different name */
769
770 /*
771 * DMA watchdog timer rw
772 * set in 16 CLK input periods.
773 */
774 #define DWT_REG 0x3a
775
776 /* DMA control rw */
777 #define DCNTL_REG 0x3b
778 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
779 #define DCNTL_700_CF0 0x40
780 #define DCNTL_700_CF_MASK 0xc0
781 /* Clock divisors Divisor SCLK range (MHZ) */
782 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
783 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
784 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
785 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
786
787 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
788 #define DCNTL_SSM 0x10 /* Single step mode */
789 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
790 * after selection */
791 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
792 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
793 /* 0x02 is reserved */
794 #define DCNTL_00_RST 0x01 /* Software reset, resets everything
795 * but 286 mode bit in DMODE. On the
796 * NCR53c710, this bit moved to CTEST8
797 */
798 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
799
800 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
801
802
803 /* NCR53c700-66 only */
804 #define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
805 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
806 /* NCR53c710 only */
807 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
808
809 #define SIEN1_REG_800 0x41
810 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
811 #define SIEN1_800_GEN 0x02 /* general purpose timer */
812 #define SIEN1_800_HTH 0x01 /* handshake to handshake */
813
814 #define SIST1_REG_800 0x43
815 #define SIST1_800_STO 0x04 /* selection/reselection timeout */
816 #define SIST1_800_GEN 0x02 /* general purpose timer */
817 #define SIST1_800_HTH 0x01 /* handshake to handshake */
818
819 #define SLPAR_REG_800 0x44 /* Parity */
820
821 #define MACNTL_REG_800 0x46 /* Memory access control */
822 #define MACNTL_800_TYP3 0x80
823 #define MACNTL_800_TYP2 0x40
824 #define MACNTL_800_TYP1 0x20
825 #define MACNTL_800_TYP0 0x10
826 #define MACNTL_800_DWR 0x08
827 #define MACNTL_800_DRD 0x04
828 #define MACNTL_800_PSCPT 0x02
829 #define MACNTL_800_SCPTS 0x01
830
831 #define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
832
833 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
834 #define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
835 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
836 #define STIME0_800_HTH_SHIFT 4
837 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
838 #define STIME0_800_SEL_SHIFT 0
839
840 #define STIME1_REG_800 0x49
841 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
842
843 #define RESPID_REG_800 0x4a /* Response ID, bit fielded */
844
845 #define STEST0_REG_800 0x4c
846 #define STEST0_800_SLT 0x08 /* Selection response logic test */
847 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
848 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
849 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
850
851 #define STEST1_REG_800 0x4d
852 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
853
854 #define STEST2_REG_800 0x4e
855 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
856 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
857 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
858 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
859 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
860 #define STEST2_800_LOW 0x01 /* SCSI low level mode */
861
862 #define STEST3_REG_800 0x4f
863 #define STEST3_800_TE 0x80 /* Enable active negation */
864 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
865 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
866 #define STEST3_800_DSI 0x10 /* Disable single initiator response */
867 #define STEST3_800_TTM 0x04 /* Time test mode */
868 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
869 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
870
871
872
873
874
875 #define OPTION_PARITY 0x1 /* Enable parity checking */
876 #define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
877 #define OPTION_700 0x8 /* Always run NCR53c700 scripts */
878 #define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
879 #define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
880 #define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
881 simple test code, return
882 DID_NO_CONNECT if any SCSI
883 commands are attempted. */
884 #define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
885 SCSI write is attempted */
886 #define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
887 each address and instruction
888 executed to debug buffer. */
889 #define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
890 instruction */
891 #define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
892 #define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
893 memory mapping */
894 #define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
895 I/O mapping */
896 #define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
897 #define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
898
899 #define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
900 #define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
901 #define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
902
903 #define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
904 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
905 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
906 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
907 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
908 #define OPTION_DEBUG_DSA 0x800000
909 #define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
910
911 #if !defined(PERM_OPTIONS)
912 #define PERM_OPTIONS 0
913 #endif
914
915 struct NCR53c7x0_synchronous {
916 unsigned long select_indirect; /* Value used for indirect selection */
917 unsigned long script[6]; /* Size ?? Script used when target is
918 reselected */
919 unsigned renegotiate:1; /* Force renegotiation on next
920 select */
921 };
922
923 #define CMD_FLAG_SDTR 1 /* Initiating synchronous
924 transfer negotiation */
925 #define CMD_FLAG_WDTR 2 /* Initiating wide transfer
926 negotiation */
927 #define CMD_FLAG_DID_SDTR 4 /* did SDTR */
928
929 struct NCR53c7x0_table_indirect {
930 unsigned long count;
931 void *address;
932 };
933
934 struct NCR53c7x0_cmd {
935 void *real; /* Real, unaligned address */
936 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
937 structure, Scsi_Cmnd points
938 at NCR53c7x0_cmd using
939 host_scribble structure */
940
941 int size; /* scsi_malloc'd size of this
942 structure */
943
944 int flags;
945
946 unsigned char select[11]; /* Select message, includes
947 IDENTIFY
948 (optional) QUEUE TAG
949 (optional) SDTR or WDTR
950 */
951
952
953 struct NCR53c7x0_cmd *next, *prev; /* Linux maintained lists */
954
955
956 unsigned long *data_transfer_start; /* Start of data transfer routines */
957 unsigned long *data_transfer_end; /* Address after end of data transfer o
958 routines */
959
960 unsigned long residual[8]; /* Residual data transfer
961 shadow of data_transfer code.
962
963 Has instruction with modified
964 DBC field followed by jump to
965 CALL routine following command.
966 */
967
968 unsigned long dsa[0]; /* Variable length (depending
969 on host type, number of scatter /
970 gather buffers, etc). */
971 };
972
973 struct NCR53c7x0_break {
974 unsigned long *address, old_instruction[2];
975 struct NCR53c7x0_break *next;
976 unsigned char old_size; /* Size of old instruction */
977 };
978
979 /* Indicates that the NCR is not executing code */
980 #define STATE_HALTED 0
981 /*
982 * Indicates that the NCR is executing the wait for select / reselect
983 * script. Only used when running NCR53c700 compatible scripts, only
984 * state during which an ABORT is _not_ considered an error condition.
985 */
986 #define STATE_WAITING 1
987 /* Indicates that the NCR is executing other code. */
988 #define STATE_RUNNING 2
989 /*
990 * Indicates that the NCR was being aborted. Only used when running
991 * NCR53c700 compatible scripts.
992 */
993 #define STATE_ABORTING 3
994
995
996 /*
997 * Where knowledge of SCSI SCRIPT(tm) specified values are needed
998 * in an interrupt handler, an interrupt handler exists for each
999 * different SCSI script so we don't have name space problems.
1000 *
1001 * Return values of these handlers are as follows :
1002 */
1003 #define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1004 #define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1005 #define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1006 #define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1007 #define SPECIFIC_INT_DONE 4 /* normal command completion */
1008 #define SPECIFIC_INT_BREAK 5 /* break point encountered */
1009
1010 struct NCR53c7x0_hostdata {
1011 int size; /* Size of entire Scsi_Host
1012 structure */
1013 struct Scsi_Host *next; /* next of this type */
1014 int board; /* set to board type, useful if
1015 we have host specific things,
1016 ie, a general purpose I/O
1017 bit is being used to enable
1018 termination, etc. */
1019
1020 int chip; /* set to chip type */
1021 /*
1022 * NCR53c700 = 700
1023 * NCR53c700-66 = 70066
1024 * NCR53c710 = 710
1025 * NCR53c720 = 720
1026 * NCR53c810 = 810
1027 */
1028
1029 /*
1030 * PCI bus, device, function, only for NCR53c8x0 chips.
1031 * pci_valid indicates that the PCI configuration information
1032 * is valid, and we can twiddle MAX_LAT, etc. as recommended
1033 * for maximum performance in the NCR documentation.
1034 */
1035 unsigned char pci_bus, pci_device_fn;
1036 unsigned pci_valid:1;
1037
1038 unsigned long *dsp; /* dsp to restart with after
1039 all stacked interrupts are
1040 handled. */
1041
1042 unsigned dsp_changed:1; /* Has dsp changed within this
1043 set of stacked interrupts ? */
1044
1045 unsigned char dstat; /* Most recent value of dstat */
1046 unsigned dstat_valid:1;
1047
1048 unsigned expecting_iid:1; /* Expect IID interrupt */
1049 unsigned expecting_sto:1; /* Expect STO interrupt */
1050
1051 /*
1052 * The code stays cleaner if we use variables with function
1053 * pointers and offsets that are unique for the different
1054 * scripts rather than having a slew of switch(hostdata->chip)
1055 * statements.
1056 *
1057 * It also means that the #defines from the SCSI SCRIPTS(tm)
1058 * don't have to be visible outside of the script-specific
1059 * instructions, preventing name space pollution.
1060 */
1061
1062 void (* init_fixup)(struct Scsi_Host *host);
1063 void (* init_save_regs)(struct Scsi_Host *host);
1064 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1065 void (* soft_reset)(struct Scsi_Host *host);
1066 int (* run_tests)(struct Scsi_Host *host);
1067
1068 /*
1069 * Called when DSTAT_SIR is set, indicating an interrupt generated
1070 * by the INT instruction, where values are unique for each SCSI
1071 * script. Should return one of the SPEC_* values.
1072 */
1073
1074 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1075
1076
1077 /*
1078 * Location of DSA fields for the SCSI SCRIPT corresponding to this
1079 * chip.
1080 */
1081
1082 long dsa_start;
1083 long dsa_end;
1084 long dsa_next;
1085 long dsa_prev;
1086 long dsa_cmnd;
1087 long dsa_select;
1088 long dsa_msgout;
1089 long dsa_cmdout;
1090 long dsa_dataout;
1091 long dsa_datain;
1092 long dsa_msgin;
1093 long dsa_msgout_other;
1094 long dsa_write_sync;
1095 long dsa_write_resume;
1096 long dsa_jump_resume;
1097 long dsa_check_reselect;
1098 long dsa_status;
1099
1100 /*
1101 * Important entry points that generic fixup code needs
1102 * to know about, fixed up.
1103 */
1104
1105 long E_accept_message;
1106 long E_dsa_code_template;
1107 long E_dsa_code_template_end;
1108 long E_command_complete;
1109 long E_msg_in;
1110 long E_initiator_abort;
1111 long E_other_transfer;
1112 long E_target_abort;
1113 long E_schedule;
1114 long E_debug_break;
1115 long E_reject_message;
1116 long E_respond_message;
1117 long E_select;
1118 long E_select_msgout;
1119 long E_test_0;
1120 long E_test_1;
1121 long E_test_2;
1122 long E_test_3;
1123 long E_dsa_zero;
1124 long E_dsa_jump_resume;
1125
1126 int options; /* Bitfielded set of options enabled */
1127 long test_completed; /* Test completed */
1128 int test_running; /* Test currently running */
1129 int test_source;
1130 volatile int test_dest;
1131
1132 volatile int state; /* state of driver, only used for
1133 OPTION_700 */
1134
1135 unsigned char dmode; /*
1136 * set to the address of the DMODE
1137 * register for this chip.
1138 */
1139 unsigned char istat; /*
1140 * set to the address of the ISTAT
1141 * register for this chip.
1142 */
1143
1144 int scsi_clock; /*
1145 * SCSI clock in HZ. 0 may be used
1146 * for unknown, although this will
1147 * disable synchronous negotiation.
1148 */
1149
1150 volatile int intrs; /* Number of interrupts */
1151 unsigned char saved_dmode;
1152 unsigned char saved_ctest4;
1153 unsigned char saved_ctest7;
1154 unsigned char saved_dcntl;
1155 unsigned char saved_scntl3;
1156
1157 unsigned char this_id_mask;
1158
1159 /* Debugger information */
1160 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1161 *breakpoint_current; /* Current breakpoint being stepped
1162 through, NULL if we are running
1163 normally. */
1164 int debug_size; /* Size of debug buffer */
1165 volatile int debug_count; /* Current data count */
1166 volatile char *debug_buf; /* Output ring buffer */
1167 volatile char *debug_write; /* Current write pointer */
1168 volatile char *debug_read; /* Current read pointer */
1169
1170 /* XXX - primitive debugging junk, remove when working ? */
1171 int debug_print_limit; /* Number of commands to print
1172 out exhaustive debugging
1173 information for if
1174 OPTION_DEBUG_DUMP is set */
1175
1176 unsigned char debug_lun_limit[8]; /* If OPTION_DEBUG_TARGET_LIMIT
1177 set, puke if commands are sent
1178 to other target/lun combinations */
1179
1180 int debug_count_limit; /* Number of commands to execute
1181 before puking to limit debugging
1182 output */
1183
1184
1185 volatile unsigned idle:1; /* set to 1 if idle */
1186
1187 /*
1188 * Table of synchronous transfer parameters set on a per-target
1189 * basis.
1190 *
1191 * XXX - do we need to increase this to 16 for the WIDE-SCSI
1192 * flavors of the board?
1193 */
1194
1195 volatile struct NCR53c7x0_synchronous sync[8];
1196
1197 volatile struct NCR53c7x0_cmd *issue_queue;
1198 /* waiting to be issued by
1199 Linux driver */
1200 volatile struct NCR53c7x0_cmd *running_list;
1201 /* commands running, maintained
1202 by Linux driver */
1203 volatile struct NCR53c7x0_cmd *current; /* currently connected
1204 nexus, ONLY valid for
1205 NCR53c700/NCR53c700-66
1206 */
1207 volatile unsigned char busy[8][8]; /* number of commands
1208 executing on each target
1209 */
1210 /*
1211 * Eventually, I'll switch to a coroutine for calling
1212 * cmd->done(cmd), etc. so that we can overlap interrupt
1213 * processing with this code for maximum performance.
1214 */
1215
1216 volatile struct NCR53c7x0_cmd *finished_queue;
1217
1218
1219 /* Shared variables between SCRIPT and host driver */
1220 volatile unsigned char *issue_dsa_head;
1221 /* commands waiting to be
1222 issued, insertions are
1223 done by Linux driver,
1224 deletions are done by
1225 NCR */
1226 volatile unsigned char *issue_dsa_tail;
1227 volatile unsigned char msg_buf[16]; /* buffer for messages
1228 other than the command
1229 complete message */
1230 volatile struct NCR53c7x0_cmd *reconnect_dsa_head;
1231 /* disconnected commands,
1232 maintained by NCR */
1233 /* Data identifying nexus we are trying to match during reselection */
1234 volatile unsigned char reselected_identify; /* IDENTIFY message */
1235 volatile unsigned char reselected_tag; /* second byte of queue tag
1236 message or 0 */
1237 int script_count; /* Size of script in longs */
1238 unsigned long script[0]; /* Relocated SCSI script */
1239
1240 };
1241
1242 #define IRQ_NONE 255
1243 #define DMA_NONE 255
1244 #define IRQ_AUTO 254
1245 #define DMA_AUTO 254
1246
1247 #define BOARD_GENERIC 0
1248
1249 #define NCR53c7x0_insn_size(insn) \
1250 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1251
1252
1253 #define NCR53c7x0_local_declare() \
1254 volatile unsigned char *NCR53c7x0_address_memory; \
1255 unsigned short NCR53c7x0_address_io; \
1256 int NCR53c7x0_memory_mapped
1257
1258 #define NCR53c7x0_local_setup(host) \
1259 NCR53c7x0_address_memory = (void *) (host)->base; \
1260 NCR53c7x0_address_io = (unsigned short) (host)->io_port; \
1261 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1262 host->hostdata)-> options & OPTION_MEMORY_MAPPED
1263
1264 #define NCR53c7x0_read8(address) \
1265 (NCR53c7x0_memory_mapped ? \
1266 *( (NCR53c7x0_address_memory) + (address)) : \
1267 inb(NCR53c7x0_address_io + (address)))
1268
1269 #define NCR53c7x0_read16(address) \
1270 (NCR53c7x0_memory_mapped ? \
1271 *((unsigned short *) (NCR53c7x0_address_memory) + (address)) : \
1272 inw(NCR53c7x0_address_io + (address)))
1273
1274 #define NCR53c7x0_read32(address) \
1275 (NCR53c7x0_memory_mapped ? \
1276 *((unsigned long *) (NCR53c7x0_address_memory) + (address)) : \
1277 inl(NCR53c7x0_address_io + (address)))
1278
1279 #define NCR53c7x0_write8(address,value) \
1280 (NCR53c7x0_memory_mapped ? \
1281 *((unsigned char *) (NCR53c7x0_address_memory) + (address)) = \
1282 (value) : \
1283 outb((value), NCR53c7x0_address_io + (address)))
1284
1285 #define NCR53c7x0_write16(address,value) \
1286 (NCR53c7x0_memory_mapped ? \
1287 *((unsigned short *) (NCR53c7x0_address_memory) + (address)) = \
1288 (value) : \
1289 outw((value), NCR53c7x0_address_io + (address)))
1290
1291 #define NCR53c7x0_write32(address,value) \
1292 (NCR53c7x0_memory_mapped ? \
1293 *((unsigned long *) (NCR53c7x0_address_memory) + (address)) = \
1294 (value) : \
1295 outl((value), NCR53c7x0_address_io + (address)))
1296
1297 #define patch_abs_32(script, offset, symbol, value) \
1298 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1299 (unsigned long)); ++i) { \
1300 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1301 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1302 printk("scsi%d : %s reference %d at 0x%lx in %s is now 0x%lx\n",\
1303 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1304 (offset), #script, (script)[A_##symbol##_used[i] - \
1305 (offset)]); \
1306 }
1307
1308 #define patch_abs_rwri_data(script, offset, symbol, value) \
1309 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1310 (unsigned long)); ++i) \
1311 (script)[A_##symbol##_used[i] - (offset)] = \
1312 ((script)[A_##symbol##_used[i] - (offset)] & \
1313 ~DBC_RWRI_IMMEDIATE_MASK) | \
1314 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1315 DBC_RWRI_IMMEDIATE_MASK)
1316
1317 #define patch_dsa_32(dsa, symbol, word, value) \
1318 { \
1319 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(long) \
1320 + (word)] = (unsigned long) (value); \
1321 if (hostdata->options & OPTION_DEBUG_DSA) \
1322 printk("scsi : dsa %s symbol %s(%ld) word %d now 0x%lx\n", \
1323 #dsa, #symbol, (long) hostdata->##symbol, \
1324 (int) (word), (long) (value)); \
1325 }
1326
1327
1328
1329 #endif /* NCR53c7x0_C */
1330 #endif /* NCR53c7x0_H */
![[top]](../icons/top.png){kind=icon}
![[bottom]](../icons/n_bottom.png){kind=icon}
*/