drivers/scsi/NCR5380.h

/* */
This source file includes following definitions.
NCR5380_i386_dma_setup
NCR5380_i386_dma_write_setup
NCR5380_i386_dma_read_setup
NCR5380_i386_dma_residual
   1 /* 
   2  * NCR 5380 defines
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 666-5836
   9  *
  10  * DISTRIBUTION RELEASE 6
  11  *
  12  * For more information, please consult 
  13  *
  14  * NCR 5380 Family
  15  * SCSI Protocol Controller
  16  * Databook
  17  * NCR Microelectronics
  18  * 1635 Aeroplaza Drive
  19  * Colorado Springs, CO 80916
  20  * 1+ (719) 578-3400
  21  * 1+ (800) 334-5454
  22  */
  23 
  24 /*
  25  * $Log: NCR5380.h,v $
  26  */
  27 
  28 #ifndef NCR5380_H
  29 #define NCR5380_H
  30 
  31 #define NCR5380_PUBLIC_RELEASE 6
  32 #ifdef NCR53C400
  33 #define NCR53C400_PUBLIC_RELEASE 1
  34 #endif
  35 
  36 #define NDEBUG_ARBITRATION      0x1
  37 #define NDEBUG_AUTOSENSE        0x2
  38 #define NDEBUG_DMA              0x4
  39 #define NDEBUG_HANDSHAKE        0x8
  40 #define NDEBUG_INFORMATION      0x10
  41 #define NDEBUG_INIT             0x20
  42 #define NDEBUG_INTR             0x40
  43 #define NDEBUG_LINKED           0x80
  44 #define NDEBUG_MAIN             0x100
  45 #define NDEBUG_NO_DATAOUT       0x200
  46 #define NDEBUG_NO_WRITE         0x400
  47 #define NDEBUG_PIO              0x800
  48 #define NDEBUG_PSEUDO_DMA       0x1000
  49 #define NDEBUG_QUEUES           0x2000
  50 #define NDEBUG_RESELECTION      0x4000
  51 #define NDEBUG_SELECTION        0x8000
  52 #define NDEBUG_USLEEP           0x10000
  53 #define NDEBUG_LAST_BYTE_SENT   0x20000
  54 #define NDEBUG_RESTART_SELECT   0x40000
  55 #define NDEBUG_EXTENDED         0x80000
  56 
  57 /* 
  58  * The contents of the OUTPUT DATA register are asserted on the bus when
  59  * either arbitration is occurring or the phase-indicating signals (
  60  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  61  * bit in the INITIATOR COMMAND register is set.
  62  */
  63 
  64 #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  65 #define CURRENT_SCSI_DATA_REG   0       /* ro same */
  66 
  67 #define INITIATOR_COMMAND_REG   1       /* rw */
  68 #define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  69 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  70 #define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  71 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  72 #define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  73 #define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  74 #define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  75 #define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  76 #define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  77 #define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  78 
  79 #ifdef DIFFERENTIAL
  80 #define ICR_BASE                ICR_DIFF_ENABLE
  81 #else
  82 #define ICR_BASE                0
  83 #endif
  84 
  85 #define MODE_REG                2
  86 /*
  87  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
  88  * transfer, causing the chip to hog the bus.  You probably don't want 
  89  * this.
  90  */
  91 #define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
  92 #define MR_TARGET               0x40    /* rw target mode */
  93 #define MR_ENABLE_PAR_CHECK   0x20      /* rw enable parity checking */
  94 #define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
  95 #define MR_ENABLE_EOP_INTR      0x08    /* rw enable eop interrupt */
  96 #define MR_MONITOR_BSY  0x04    /* rw enable int on unexpected bsy fail */
  97 #define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
  98 #define MR_ARBITRATE            0x01    /* rw start arbitration */
  99 
 100 #ifdef PARITY
 101 #define MR_BASE                 MR_ENABLE_PAR_CHECK
 102 #else
 103 #define MR_BASE                 0
 104 #endif
 105 
 106 #define TARGET_COMMAND_REG      3
 107 #define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 108 #define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 109 #define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 110 #define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 111 #define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 112 
 113 #define STATUS_REG              4       /* ro */
 114 /*
 115  * Note : a set bit indicates an active signal, driven by us or another 
 116  * device.
 117  */
 118 #define SR_RST                  0x80    
 119 #define SR_BSY                  0x40
 120 #define SR_REQ                  0x20
 121 #define SR_MSG                  0x10
 122 #define SR_CD                   0x08
 123 #define SR_IO                   0x04
 124 #define SR_SEL                  0x02
 125 #define SR_DBP                  0x01
 126 
 127 /*
 128  * Setting a bit in this register will cause an interrupt to be generated when 
 129  * BSY is false and SEL true and this bit is asserted  on the bus.
 130  */
 131 #define SELECT_ENABLE_REG       4       /* wo */
 132 
 133 #define BUS_AND_STATUS_REG      5       /* ro */
 134 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 135 #define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 136 #define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 137 #define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 138 #define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 139 #define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 140 #define BASR_ATN                0x02    /* ro BUS status */
 141 #define BASR_ACK                0x01    /* ro BUS status */
 142 
 143 /* Write any value to this register to start a DMA send */
 144 #define START_DMA_SEND_REG      5       /* wo */
 145 
 146 /* 
 147  * Used in DMA transfer mode, data is latched from the SCSI bus on
 148  * the falling edge of REQ (ini) or ACK (tgt)
 149  */
 150 #define INPUT_DATA_REG                  6       /* ro */
 151 
 152 /* Write any value to this register to start a DMA receive */
 153 #define START_DMA_TARGET_RECEIVE_REG    6       /* wo */
 154 
 155 /* Read this register to clear interrupt conditions */
 156 #define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 157 
 158 /* Write any value to this register to start an ini mode DMA receive */
 159 #define START_DMA_INITIATOR_RECEIVE_REG 7       /* wo */
 160 
 161 #ifdef NCR53C400
 162 #define C400_CONTROL_STATUS_REG                -8      /* rw */
 163 
 164 #define CSR_RESET              0x80    /* wo  Resets 53c400 */
 165 #define CSR_53C80_REG          0x80    /* ro  5380 registers busy */
 166 #define CSR_TRANS_DIR          0x40    /* rw  Data transfer direction */
 167 #define CSR_SCSI_BUFF_INTR     0x20    /* rw  Enable int on transfer ready */
 168 #define CSR_53C80_INTR         0x10    /* rw  Enable 53c80 interrupts */
 169 #define CSR_SHARED_INTR                0x08    /* rw  Interrupt sharing */
 170 #define CSR_HOST_BUF_NOT_RDY   0x04    /* ro  Is Host buffer ready */
 171 #define CSR_SCSI_BUF_RDY       0x02    /* ro  SCSI buffer read */
 172 #define CSR_GATED_53C80_IRQ    0x01    /* ro  Last block xferred */
 173 
 174 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
 175 
 176 /* Number of 128-byte blocks to be transferred */
 177 #define C400_CLOCK_COUNTER_REG         -7      /* rw */
 178 
 179 /* Resume transfer after disconnect */
 180 #define C400_RESUME_TRANSFER_REG       -6      /* wo */
 181 
 182 /* Access to host buffer stack */
 183 #define C400_HOST_BUFFER                       -4      /* rw */
 184 
 185 #endif /* NCR53C400 */
 186 
 187 
 188 /* Note : PHASE_* macros are based on the values of the STATUS register */
 189 #define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 190 
 191 #define PHASE_DATAOUT           0
 192 #define PHASE_DATAIN            SR_IO
 193 #define PHASE_CMDOUT            SR_CD
 194 #define PHASE_STATIN            (SR_CD | SR_IO)
 195 #define PHASE_MSGOUT            (SR_MSG | SR_CD)
 196 #define PHASE_MSGIN             (SR_MSG | SR_CD | SR_IO)
 197 #define PHASE_UNKNOWN           0xff
 198 
 199 /* 
 200  * Convert status register phase to something we can use to set phase in 
 201  * the target register so we can get phase mismatch interrupts on DMA 
 202  * transfers.
 203  */
 204  
 205 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)   
 206 
 207 /*
 208  * The internal should_disconnect() function returns these based on the 
 209  * expected length of a disconnect if a device supports disconnect/
 210  * reconnect.
 211  */
 212 
 213 #define DISCONNECT_NONE         0
 214 #define DISCONNECT_TIME_TO_DATA 1
 215 #define DISCONNECT_LONG         2
 216 
 217 /* 
 218  * These are "special" values for the tag parameter passed to NCR5380_select.
 219  */
 220 
 221 #define TAG_NEXT        -1      /* Use next free tag */
 222 #define TAG_NONE        -2      /* 
 223                                  * Establish I_T_L nexus instead of I_T_L_Q
 224                                  * even on SCSI-II devices.
 225                                  */
 226 
 227 /*
 228  * These are "special" values for the irq and dma_channel fields of the 
 229  * Scsi_Host structure
 230  */
 231 
 232 #define IRQ_NONE        255
 233 #define DMA_NONE        255
 234 #define IRQ_AUTO        254
 235 #define DMA_AUTO        254
 236 
 237 #define FLAG_HAS_LAST_BYTE_SENT         1       /* NCR53c81 or better */
 238 #define FLAG_CHECK_LAST_BYTE_SENT       2       /* Only test once */
 239 #define FLAG_NCR53C400                  4       /* NCR53c400 */
 240 
 241 #ifndef ASM
 242 struct NCR5380_hostdata {
 243     NCR5380_implementation_fields;              /* implementation specific */
 244     unsigned char id_mask, id_higher_mask;      /* 1 << id, all bits greater */
 245     unsigned char targets_present;              /* targets we have connected
 246                                                    to, so we can call a select
 247                                                    failure a retryable condition */
 248     volatile unsigned char busy[8];             /* index = target, bit = lun */
 249 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
 250     volatile int dma_len;                       /* requested length of DMA */
 251 #endif
 252     volatile unsigned char last_message;        /* last message OUT */
 253     volatile Scsi_Cmnd *connected;              /* currently connected command */
 254     volatile Scsi_Cmnd *issue_queue;            /* waiting to be issued */
 255     volatile Scsi_Cmnd *disconnected_queue;     /* waiting for reconnect */
 256     volatile int restart_select;                /* we have disconnected,
 257                                                    used to restart 
 258                                                    NCR5380_select() */
 259     volatile unsigned aborted:1;                /* flag, says aborted */
 260     int flags;
 261 #ifdef USLEEP
 262     unsigned long time_expires;                 /* in jiffies, set prior to sleeping */
 263     struct Scsi_Host *next_timer;
 264 #endif
 265 };
 266 
 267 #ifdef __KERNEL__
 268 static struct Scsi_Host *first_instance;                /* linked list of 5380's */
 269 
 270 #if defined(AUTOPROBE_IRQ)
 271 static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
 272 #endif
 273 static void NCR5380_init (struct Scsi_Host *instance, int flags);
 274 static void NCR5380_information_transfer (struct Scsi_Host *instance);
 275 static void NCR5380_intr (int irq);
 276 static void NCR5380_main (void);
 277 static void NCR5380_print_options (struct Scsi_Host *instance);
 278 #ifndef NCR5380_abort
 279 static
 280 #endif
 281 int NCR5380_abort (Scsi_Cmnd *cmd);
 282 #ifndef NCR5380_reset
 283 static
 284 #endif
 285 int NCR5380_reset (Scsi_Cmnd *cmd);
 286 #ifndef NCR5380_queue_command
 287 static 
 288 #endif
 289 int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
 290 
 291 
 292 static void NCR5380_reselect (struct Scsi_Host *instance);
 293 static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
 294 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
 295 static int NCR5380_transfer_dma (struct Scsi_Host *instance,
 296         unsigned char *phase, int *count, unsigned char **data);
 297 #endif
 298 static int NCR5380_transfer_pio (struct Scsi_Host *instance,
 299         unsigned char *phase, int *count, unsigned char **data);
 300 
 301 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) && defined(i386)
 302 static __inline__ int NCR5380_i386_dma_setup (struct Scsi_Host *instance,
     /*  */
 303         unsigned char *ptr, unsigned int count, unsigned char mode) {
 304     unsigned limit;
 305 
 306     if (instance->dma_channel <=3) {
 307         if (count > 65536)
 308             count = 65536;
 309         limit = 65536 - (((unsigned) ptr) & 0xFFFF);
 310     } else {
 311         if (count > 65536 * 2) 
 312             count = 65536 * 2;
 313         limit = 65536* 2 - (((unsigned) ptr) & 0x1FFFF);
 314     }
 315 
 316     if (count > limit) count = limit;
 317 
 318     if ((count & 1) || (((unsigned) ptr) & 1))
 319         panic ("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
 320     cli();
 321     disable_dma(instance->dma_channel);
 322     clear_dma_ff(instance->dma_channel);
 323     set_dma_addr(instance->dma_channel, (unsigned int) ptr);
 324     set_dma_count(instance->dma_channel, count);
 325     set_dma_mode(instance->dma_channel, mode);
 326     enable_dma(instance->dma_channel);
 327     sti();
 328     return count;
 329 }
 330 
 331 static __inline__ int NCR5380_i386_dma_write_setup (struct Scsi_Host *instance,
     /*  */
 332     unsigned char *src, unsigned int count) {
 333     return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_WRITE);
 334 }
 335 
 336 static __inline__ int NCR5380_i386_dma_read_setup (struct Scsi_Host *instance,
     /*  */
 337     unsigned char *src, unsigned int count) {
 338     return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_READ);
 339 }
 340 
 341 static __inline__ int NCR5380_i386_dma_residual (struct Scsi_Host *instance) {
     /*  */
 342     register int tmp;
 343     cli();
 344     clear_dma_ff(instance->dma_channel);
 345     tmp = get_dma_residue(instance->dma_channel);
 346     sti();
 347     return tmp;
 348 }
 349 #endif /* defined(REAL_DMA) && defined(i386)  */
 350 #endif __KERNEL_
 351 #endif /* ndef ASM */
 352 #endif /* NCR5380_H */
/* */
root/drivers/scsi/NCR5380.h

INCLUDED FROM

DEFINITIONS
