root/include/asm-sparc/psr.h

/* */

   1 /* psr.h: This file holds the macros for masking off various parts of
   2           the processor status register on the Sparc. This is valid
   3           for Version 8. On the V9 this is renamed to the PSTATE
   4           register and it's members are accessed as fields like
   5           PSTATE.PRIV for the current CPU privilege level.
   6 
   7    Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
   8 */
   9 
  10 #ifndef __LINUX_SPARC_PSR_H
  11 #define __LINUX_SPARC_PSR_H
  12 
  13 
  14 #ifdef __LINUX_SPARC_V8
  15 
  16 /* The Sparc PSR fields are laid out as the following:
  17 
  18     ------------------------------------------------------------------------
  19     | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
  20 bits| 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
  21     ------------------------------------------------------------------------
  22 
  23    The PSR can only be directly be written/read by the privileged instructions
  24    'rd' and 'wr'. Certain fields are changed as a side effect due to the 'Ticc',
  25    'save', 'restore', and 'rett' instructions. Also the integer condition codes
  26    'icc' are modified by various arithmetic instructions.
  27 
  28    For example:  wr  %o2, or'd_bit_pattern, %psr
  29                  rd  %psr, %o3
  30 
  31 */
  32 
  33 #define PSR_CWP     0x0000001f         /* current window pointer     */
  34 #define PSR_ET      0x00000020         /* enable traps field         */
  35 #define PSR_PS      0x00000040         /* previous privilege level   */
  36 #define PSR_S       0x00000080         /* current privilege level    */
  37 #define PSR_PIL     0x00000f00         /* processor interrupt level  */
  38 #define PSR_EF      0x00001000         /* enable floating point      */
  39 #define PSR_EC      0x00002000         /* enable co-processor        */
  40 #define PSR_ICC     0x00f00000         /* integer condition codes    */
  41 #define PSR_C       0x00100000         /* carry bit                  */
  42 #define PSR_V       0x00200000         /* overflow bit               */
  43 #define PSR_Z       0x00400000         /* zero bit                   */
  44 #define PSR_N       0x00800000         /* negative bit               */
  45 #define PSR_VERS    0x0f000000         /* cpu-version field          */
  46 #define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
  47 
  48 #endif /* !(__LINUX_SPARC_V8) */
  49 
  50 #ifdef __LINUX_SPARC_V9
  51 
  52 /* The information available in the %psr on the V8 is spread amongst
  53    a whole bunch of registers on the V9. The main one being PSTATE.
  54 
  55      --------------------------------------------------------
  56      |  CLE  | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
  57 bits |   9   |  8  |  7-6 |  5  |  4  |  3 |   2  |  1 |  0 |
  58      --------------------------------------------------------
  59 
  60    Writes and reads to PSTATE are done via 'wrpr' and 'rdpr' instructions.
  61 
  62    For example:  wrpr %o2, or'd_bit_pattern, %pstate
  63                  rdpr %pstate, %o3
  64 */
  65 
  66 #define PSTATE_AG    0x001   /* Alternate Globals             */
  67 #define PSTATE_IE    0x002   /* Interrupt Enable              */
  68 #define PSTATE_PRIV  0x004   /* Current privilege level       */
  69 #define PSTATE_AM    0x008   /* Address mask (data reads can  */
  70                              /* be chosen to be either big or */
  71                              /* little endian on V9).         */
  72 #define PSTATE_PEF   0x010   /* enable floating point         */
  73 #define PSTATE_RED   0x020   /* RED trap state (set if trap   */
  74                              /* trap_level == max_tl).        */
  75 #define PSTATE_MM    0x0c0   /* Memory model (Total Store     */
  76                              /* Order=0, Partial Store Order  */
  77                              /* =1 or Relaxed Memory Order=2) */
  78 #define PSTATE_TLE   0x100   /* Trap Little Endian            */
  79 #define PSTATE_CLE   0x200   /* Current Little Endian         */
  80 
  81 
  82 /* The Version Register holds vendor information for the chip:
  83 
  84     ---------------------------------------------------------------------------
  85     | manufacturer | implementation | mask | reserved | maxtl | resv | maxwin |
  86 bits|  63-48       |   47-32        | 31-24|   23-16  | 15-8  | 7-5  |  4-0   |
  87     ---------------------------------------------------------------------------
  88 
  89 */
  90 
  91 #define VERS_MAXWIN  0x000000000000001f     /* 'nwindows' on this chip       */
  92 #define VERS_MAXTL   0x00000000000ff000     /* Maximum Trap-level supported  */
  93 #define VERS_MASK    0x0000000ff0000000     /* impl. dep. chip mask revision */
  94 #define VERS_MANUF   0xffff000000000000     /* Manufacturer ID code          */
  95 
  96 #endif /* !(__LINUX_SPARC_V9) */
  97 
  98 #endif /* !(__LINUX_SPARC_PSR_H) */

/* */