include/asm-sparc/system.h

/* */
This source file includes following definitions.
get_psr
put_psr
xchg_u32
xchg_ptr
   1 #ifndef __SPARC_SYSTEM_H
   2 #define __SPARC_SYSTEM_H
   3 
   4 /*
   5  * System defines.. Note that this is included both from .c and .S
   6  * files, so it does only defines, not any C code.
   7  */
   8 
   9 /*
  10  * I wish the boot time image was as beautiful as the Alpha's
  11  * but no such luck. The icky PROM loads us at 0x0, and jumps
  12  * to magic address 0x4000 to start thing going. This means that
  13  * I can stick the pcb and user/kernel stacks in the area from
  14  * 0x0-0x4000 and be reasonably sure that this is sane.
  15  *
  16  * Sorry, I can't impress people with cool looking 64-bit values
  17  * yet. ;-)
  18  */
  19 
  20 #include <asm/openprom.h>
  21 #include <asm/psr.h>
  22 
  23 #define INIT_PCB        0x00011fe0
  24 #define INIT_STACK      0x00013fe0
  25 #define START_ADDR      0x00004000
  26 #define START_SIZE      (32*1024)
  27 #define EMPTY_PGT       0x00001000
  28 #define EMPTY_PGE       0x00001000
  29 #define ZERO_PGE        0x00001000
  30 
  31 #define IRQ_ENA_ADR     0x2000        /* This is a bitmap of all activated IRQ's
  32                                        * which is mapped in head.S during boot.
  33                                        */
  34 
  35 #ifndef __ASSEMBLY__
  36 
  37 extern void wrent(void *, unsigned long);
  38 extern void wrkgp(unsigned long);
  39 extern struct linux_romvec *romvec;
  40 
  41 #define halt() { romvec->pv_halt(); }
  42 #define move_to_user_mode() halt()
  43 #define switch_to(x) halt()
  44 
  45 #ifndef stbar  /* store barrier Sparc insn to synchronize stores in PSO */
  46 #define stbar() __asm__ __volatile__("stbar": : :"memory")
  47 #endif
  48 
  49 /* Changing the PIL on the sparc is a bit hairy. I'll figure out some
  50  * more optimized way of doing this soon. This is bletcherous code.
  51  */
  52 
  53 #define swpipl(__new_ipl) \
  54 ({ unsigned long psr, retval; \
  55 __asm__ __volatile__( \
  56         "rd %%psr, %0\n\t" : "=&r" (psr)); \
  57 retval = psr; \
  58 psr = (psr & ~(PSR_PIL)); \
  59 psr |= ((__new_ipl << 8) & PSR_PIL); \
  60 __asm__ __volatile__( \
  61         "wr  %0, 0x0, %%psr\n\t" \
  62         : : "r" (psr)); \
  63 retval = ((retval>>8)&15); \
  64 retval; })
  65 
  66 #define cli()                   swpipl(15)  /* 15 = no int's except nmi's */
  67 #define sti()                   swpipl(0)   /* same as alpha */
  68 #define save_flags(flags)       do { flags = swpipl(15); } while (0)
  69 #define restore_flags(flags)    swpipl(flags)
  70 
  71 #define iret() __asm__ __volatile__ ("jmp %%l1\n\t" \
  72                                      "rett %%l2\n\t": : :"memory")
  73 
  74 #define _set_gate(gate_addr,type,dpl,addr) \
  75 __asm__ __volatile__ ("nop\n\t")
  76 
  77 #define set_intr_gate(n,addr) \
  78         _set_gate(&idt[n],14,0,addr)
  79 
  80 #define set_trap_gate(n,addr) \
  81         _set_gate(&idt[n],15,0,addr)
  82 
  83 #define set_system_gate(n,addr) \
  84         _set_gate(&idt[n],15,3,addr)
  85 
  86 #define set_call_gate(a,addr) \
  87         _set_gate(a,12,3,addr)
  88 
  89 
  90 extern inline unsigned int get_psr(void)
     /*  */
  91 {
  92   unsigned int ret_val;
  93   __asm__("rd %%psr, %0\n\t" :
  94           "=r" (ret_val));
  95   return ret_val;
  96 }
  97 
  98 extern inline void put_psr(unsigned int new_psr)
     /*  */
  99 {
 100   __asm__("wr %0, 0x0, %%psr\n\t" : :
 101           "r" (new_psr));
 102 }
 103 
 104 /* Must this be atomic? */
 105 
 106 extern inline void *xchg_u32(int * m, unsigned long val)
     /*  */
 107 {
 108         unsigned long dummy;
 109 
 110         __asm__ __volatile__(
 111                 "ld [%1],%2\n\t"
 112                 "st %0, [%1]\n\t"
 113                 "or %%g0, %2, %0"
 114                 : "=r" (val), "=r" (m), "=r" (dummy)
 115                 : "0" (val));
 116         return (void *)val;
 117 }
 118 
 119 
 120 /* pointers are 32 bits on the sparc (at least the v8, and they'll work
 121  * on the V9 none the less). I don't need the xchg_u64 routine for now.
 122  */
 123 
 124 extern inline void *xchg_ptr(void *m, void *val)
     /*  */
 125 {
 126         return (void *) xchg_u32((int *) m, (unsigned long) val);
 127 }
 128 
 129 
 130 
 131 #endif /* __ASSEMBLY__ */
 132 
 133 #endif
/* */
root/include/asm-sparc/system.h

INCLUDED FROM

DEFINITIONS
