drivers/net/3c503.h

/* */
   1 /* Definitions for the 3Com 3c503 Etherlink 2. */
   2 /* This file is distributed under the GPL.
   3    Many of these names and comments are directly from the Crynwr packet
   4    drivers, which are released under the GPL. */
   5 
   6 #define EL2H (dev->base_addr + 0x400)
   7 #define EL2L (dev->base_addr)
   8 
   9 /* Shared memory management parameters */
  10 
  11 #define EL2SM_START_PG  (0x20)  /* First page of TX buffer */
  12 #define EL2SM_STOP_PG   (0x40)  /* Last page +1 of RX ring */
  13 
  14 /* 3Com 3c503 ASIC registers */
  15 #define E33G_STARTPG    (EL2H+0)        /* Start page, matching EN0_STARTPG */
  16 #define E33G_STOPPG     (EL2H+1)        /* Stop page, must match EN0_STOPPG */
  17 #define E33G_DRQCNT     (EL2H+2)        /* DMA burst count */
  18 #define E33G_IOBASE     (EL2H+3)        /* Read of I/O base jumpers. */
  19         /* (non-useful, but it also appears at the end of EPROM space) */
  20 #define E33G_ROMBASE    (EL2H+4)        /* Read of memory base jumpers. */
  21 #define E33G_GACFR      (EL2H+5)        /* Config/setup bits for the ASIC GA */
  22 #define E33G_CNTRL      (EL2H+6)        /* Board's main control register */
  23 #define E33G_STATUS     (EL2H+7)        /* Status on completions. */
  24 #define E33G_IDCFR      (EL2H+8)        /* Interrupt/DMA config register */
  25                                 /* (Which IRQ to assert, DMA chan to use) */
  26 #define E33G_DMAAH      (EL2H+9)        /* High byte of DMA address reg */
  27 #define E33G_DMAAL      (EL2H+10)       /* Low byte of DMA address reg */
  28 /* "Vector pointer" - if this address matches a read, the EPROM (rather than
  29    shared RAM) is mapped into memory space. */
  30 #define E33G_VP2        (EL2H+11)
  31 #define E33G_VP1        (EL2H+12)
  32 #define E33G_VP0        (EL2H+13)
  33 #define E33G_FIFOH      (EL2H+14)       /* FIFO for programmed I/O moves */
  34 #define E33G_FIFOL      (EL2H+15)       /* ... low byte of above. */
  35 
  36 /* Bits in E33G_CNTRL register: */
  37 
  38 #define ECNTRL_RESET    (0x01)  /* Software reset of the ASIC and 8390 */
  39 #define ECNTRL_THIN     (0x02)  /* Onboard xcvr enable, AUI disable */
  40 #define ECNTRL_AUI      (0x00)  /* Onboard xcvr disable, AUI enable */
  41 #define ECNTRL_SAPROM   (0x04)  /* Map the station address prom */
  42 #define ECNTRL_DBLBFR   (0x20)  /* FIFO configuration bit */
  43 #define ECNTRL_OUTPUT   (0x40)  /* PC-to-3C503 direction if 1 */
  44 #define ECNTRL_INPUT    (0x00)  /* 3C503-to-PC direction if 0 */
  45 #define ECNTRL_START    (0x80)  /* Start the DMA logic */
  46 
  47 /* Bits in E33G_STATUS register: */
  48 
  49 #define ESTAT_DPRDY     (0x80)  /* Data port (of FIFO) ready */
  50 #define ESTAT_UFLW      (0x40)  /* Tried to read FIFO when it was empty */
  51 #define ESTAT_OFLW      (0x20)  /* Tried to write FIFO when it was full */
  52 #define ESTAT_DTC       (0x10)  /* Terminal Count from PC bus DMA logic */
  53 #define ESTAT_DIP       (0x08)  /* DMA In Progress */
  54 
  55 /* Bits in E33G_GACFR register: */
  56 
  57 #define EGACFR_NORM     (0x49)  /* Enable 8K shared mem, no DMA TC int */
  58 #define EGACFR_IRQOFF   (0xc9)  /* Above, and disable 8390 IRQ line */
  59 
  60 /* End of 3C503 parameter definitions */
/* */
root/drivers/net/3c503.h

INCLUDED FROM
