include/asm-sparc/system.h

/* */
This source file includes following definitions.
get_psr
put_psr
xchg_u32
xchg_ptr
   1 #ifndef __SPARC_SYSTEM_H
   2 #define __SPARC_SYSTEM_H
   3 
   4 #include <asm/segment.h>
   5 
   6 /*
   7  * System defines.. Note that this is included both from .c and .S
   8  * files, so it does only defines, not any C code.
   9  */
  10 
  11 /*
  12  * I wish the boot time image was as beautiful as the Alpha's
  13  * but no such luck. The icky PROM loads us at 0x0, and jumps
  14  * to magic address 0x4000 to start thing going. This means that
  15  * I can stick the pcb and user/kernel stacks in the area from
  16  * 0x0-0x4000 and be reasonably sure that this is sane.
  17  *
  18  * Sorry, I can't impress people with cool looking 64-bit values
  19  * yet. ;-)
  20  */
  21 
  22 #include <asm/openprom.h>
  23 #include <asm/psr.h>
  24 
  25 #define INIT_PCB        0x00011fe0
  26 #define INIT_STACK      0x00013fe0
  27 #define START_ADDR      0x00004000
  28 #define START_SIZE      (32*1024)
  29 #define EMPTY_PGT       0x00001000
  30 #define EMPTY_PGE       0x00001000
  31 #define ZERO_PGE        0x00001000
  32 
  33 #define IRQ_ENA_ADR     0x2000        /* This is a bitmap of all activated IRQ's
  34                                        * which is mapped in head.S during boot.
  35                                        */
  36 
  37 #ifndef __ASSEMBLY__
  38 
  39 extern void wrent(void *, unsigned long);
  40 extern void wrkgp(unsigned long);
  41 extern struct linux_romvec *romvec;
  42 
  43 #define halt() { romvec->pv_halt(); }
  44 #define move_to_user_mode() halt()
  45 #define switch_to(x) halt()
  46 
  47 #ifndef stbar  /* store barrier Sparc insn to synchronize stores in PSO */
  48 #define stbar() __asm__ __volatile__("stbar": : :"memory")
  49 #endif
  50 
  51 /* Changing the PIL on the sparc is a bit hairy. I'll figure out some
  52  * more optimized way of doing this soon. This is bletcherous code.
  53  */
  54 
  55 #define swpipl(__new_ipl) \
  56 ({ unsigned long psr, retval; \
  57 __asm__ __volatile__( \
  58         "rd %%psr, %0\n\t" : "=&r" (psr)); \
  59 retval = psr; \
  60 psr = (psr & ~(PSR_PIL)); \
  61 psr |= ((__new_ipl << 8) & PSR_PIL); \
  62 __asm__ __volatile__( \
  63         "wr  %0, 0x0, %%psr\n\t" \
  64         : : "r" (psr)); \
  65 retval = ((retval>>8)&15); \
  66 retval; })
  67 
  68 #define cli()                   swpipl(15)  /* 15 = no int's except nmi's */
  69 #define sti()                   swpipl(0)   /* I'm scared */
  70 #define save_flags(flags)       do { flags = swpipl(15); } while (0)
  71 #define restore_flags(flags)    swpipl(flags)
  72 
  73 #define iret() __asm__ __volatile__ ("jmp %%l1\n\t" \
  74                                      "rett %%l2\n\t": : :"memory")
  75 
  76 #define _set_gate(gate_addr,type,dpl,addr) \
  77 __asm__ __volatile__ ("nop\n\t")
  78 
  79 #define set_intr_gate(n,addr) \
  80         _set_gate(&idt[n],14,0,addr)
  81 
  82 #define set_trap_gate(n,addr) \
  83         _set_gate(&idt[n],15,0,addr)
  84 
  85 #define set_system_gate(n,addr) \
  86         _set_gate(&idt[n],15,3,addr)
  87 
  88 #define set_call_gate(a,addr) \
  89         _set_gate(a,12,3,addr)
  90 
  91 
  92 extern inline unsigned int get_psr(void)
     /*  */
  93 {
  94   unsigned int ret_val;
  95   __asm__("rd %%psr, %0\n\t" :
  96           "=r" (ret_val));
  97   return ret_val;
  98 }
  99 
 100 extern inline void put_psr(unsigned int new_psr)
     /*  */
 101 {
 102   __asm__("wr %0, 0x0, %%psr\n\t" : :
 103           "r" (new_psr));
 104 }
 105 
 106 /* Must this be atomic? */
 107 
 108 extern inline void *xchg_u32(int * m, unsigned long val)
     /*  */
 109 {
 110         unsigned long dummy;
 111 
 112         __asm__ __volatile__(
 113                 "ld %1,%2   ! xchg_u32() is here\n\t"
 114                 "st %0, %1\n\t"
 115                 "or %%g0, %2, %0"
 116                 : "=r" (val), "=m" (*m), "=r" (dummy)
 117                 : "0" (val));
 118         return (void *) val;
 119 }
 120 
 121 
 122 /* pointers are 32 bits on the sparc (at least the v8, and they'll work
 123  * on the V9 none the less). I don't need the xchg_u64 routine for now.
 124  */
 125 
 126 extern inline void *xchg_ptr(void *m, void *val)
     /*  */
 127 {
 128         return (void *) xchg_u32((int *) m, (unsigned long) val);
 129 }
 130 
 131 
 132 
 133 #endif /* __ASSEMBLY__ */
 134 
 135 #endif
/* */
root/include/asm-sparc/system.h

INCLUDED FROM

DEFINITIONS
