root/arch/mips/kernel/head.S

/* */

   1 /*
   2  *  mips/head.S
   3  *
   4  *  Copyright (C) 1994 Waldorf Electronics
   5  *  Written by Ralf Baechle and Andreas Busse
   6  *
   7  *  Head.S contains the MIPS exception handler and startup code.
   8  */
   9 
  10 #undef DEBUGPICA /* undef this if you have a different system */
  11 
  12 #include <linux/tasks.h>
  13 
  14 #include <asm/segment.h>
  15 #include <asm/cachectl.h>
  16 #include <asm/mipsregs.h>
  17 #include <asm/mipsconfig.h>
  18 #include <asm/stackframe.h>
  19 #include <asm/regdef.h>
  20 #include <asm/bootinfo.h>
  21 #include <asm/segment.h>
  22 
  23 #define PAGE_SIZE       0x1000
  24 
  25 /*
  26  * For now we can't enable write caching. This would cause trouble
  27  * with the page aliases used by the memory management.
  28  * The page table's aliases even have to be uncachable, but that
  29  * doesn't hurt much anyway.
  30  */
  31 #define PAGE_TABLE      0x0580  /* uncachable */
  32 #define PAGE_SHARED     0x0580  /* cachable, writethrough, no write allocate */
  33 #define MODE_ALIAS      0x0016  /* uncachable */
  34 
  35                 .globl  _empty_bad_page
  36                 .globl  _empty_bad_page_table
  37                 .globl  _pg0
  38                 .globl  _empty_zero_page
  39                 .globl  _swapper_pg_dir
  40 
  41                 .text
  42                 .globl  _kernelbase
  43 _kernelbase:
  44 
  45 /*
  46  * This is space for the interrupt handlers.
  47  * They are located at virtual address KSEG[01] (physical 0x0)
  48  */
  49                 /*
  50                  * TLB refill, EXL == 0
  51                  */
  52                 .set    noreorder
  53                 .set    noat
  54 except_vec0:
  55 #if KERNELBASE == KSEG1
  56                 la      k0,1f
  57                 jr      k0
  58                 nop
  59 1:
  60 #endif
  61                 dmfc0   k1,CP0_CONTEXT
  62                 dsra    k1,k1,1
  63                 lwu     k0,(k1)                 # May cause another exception
  64                 lwu     k1,4(k1)
  65                 dsrl    k0,k0,6                 # Convert to EntryLo format
  66                 dsrl    k1,k1,6                 # Convert to EntryLo format
  67                 dmtc0   k0,CP0_ENTRYLO0
  68                 dmtc0   k1,CP0_ENTRYLO1
  69                 tlbwr
  70                 eret
  71 
  72                 /*
  73                  * XTLB refill, EXL == 0
  74                  * Should never be reached
  75                  */
  76                 .org    except_vec0+0x80
  77 except_vec1:    
  78 #if KERNELBASE == KSEG1
  79                 la      k0,1f
  80                 jr      k0
  81                 nop
  82 1:
  83 #endif
  84                 la      a0,xtlb_text
  85                 jal     _panic
  86                 nop
  87 1:              j       1b
  88                 nop
  89 xtlb_text:      .asciz  "XTLB Refill exception.\n"
  90 
  91                 /*
  92                  * Cache Error
  93                  */
  94                 .org    except_vec1+0x80
  95 except_vec2:
  96 #if KERNELBASE == KSEG1
  97                 la      k0,1f
  98                 jr      k0
  99                 nop
 100 1:
 101 #endif
 102                 /*
 103                  * Should never be reached
 104                  */
 105                 la      a0,xtlb_text
 106                 jal     _panic
 107                 nop
 108 1:              j       1b
 109                 nop
 110 cache_text:     .asciz  "Cache error exception\n"
 111 
 112                 /*
 113                  * General exception vector.
 114                  */
 115                 .org    except_vec2+0x80
 116 except_vec3:    /*
 117                  * Register saving is delayed as long as we don't know
 118                  * which registers really need to be saved.
 119                  */
 120 #if KERNELBASE == KSEG1
 121                 la      k0,1f
 122                 jr      k0
 123                 nop
 124 1:
 125 #endif
 126                 .set    noat
 127                 mfc0    k1,CP0_CAUSE
 128                 la      k0,_exception_handlers
 129                 /*
 130                  * Next lines assumes that the used CPU type has max.
 131                  * 32 different types of exceptions. We might use this
 132                  * to implement software exceptions in the future.
 133                  */
 134                 andi    k1,k1,0x7c
 135                 addu    k0,k0,k1
 136                 lw      k0,(k0)
 137                 FILL_LDS
 138                 jr      k0
 139                 nop
 140 
 141 /******************************************************************************/
 142 
 143 /*
 144  * Kernel entry
 145  */
 146                 .set    noreorder
 147                 .set    at
 148 kernel_entry:
 149                 jal     refill
 150                 nop
 151 
 152                 /*
 153                  * Clear BSS first so that there are no surprises...
 154                  */
 155                 la      t0,__edata
 156                 la      t1,__end
 157                 sw      zero,(t0)
 158 1:              addiu   t0,t0,4
 159                 bnel    t0,t1,1b
 160                 sw      zero,(t0)
 161 
 162 #ifdef DEBUGPICA
 163                 la      t0,_boot_info
 164                 lw      t0,OFFSET_BOOTINFO_VRAM_BASE(t0)
 165                 li      t1,0x0f00 + '3'
 166                 sh      t1,4(t0)
 167 #endif
 168 
 169                 .set    noreorder
 170                 jal     _tlbflush
 171                 mtc0    zero,CP0_WIRED
 172                 /*
 173                  * Spread some mines...
 174                  */
 175                 la      t0,_end
 176                 la      t1,0x003ffffc
 177                 la      t2,KERNELBASE
 178                 or      t1,t2
 179                 li      t2,0xdeadbeef
 180 1:              sw      t2,(t0)
 181                 bne     t0,t1,1b
 182                 addiu   t0,t0,4
 183                 /*
 184                  * Initialize memory management, map lowest 4MB
 185                  */
 186                 .set    reorder
 187                 jal     setup_paging
 188 #if KERNELBASE == KSEG0
 189                 jal     _sys_cacheflush
 190 #endif
 191 
 192 #ifdef DEBUGPICA
 193                 la      t0,_boot_info
 194                 lw      t0,OFFSET_BOOTINFO_VRAM_BASE(t0)
 195                 li      t1,0x0f00 + '4'
 196                 sh      t1,6(t0)
 197 #endif
 198                 /*
 199                  * Stack for kernel and init
 200                  */
 201                 la      sp,_init_user_stack+PAGE_SIZE-24
 202                 sw      sp,_kernelsp
 203 
 204 1:              jal     _start_kernel
 205                 /*
 206                  * Main should never return here, but
 207                  * just in case, we know what happens.
 208                  */
 209                 j       1b
 210 
 211 /*
 212  * Setup_paging
 213  *
 214  * Wire mappings for page_tables.
 215  * The page tables are set up, identity-mapping
 216  * the first 4MB.  The rest are initialized later.
 217  */
 218                 .set    noreorder
 219 setup_paging:
 220                 /*
 221                  * get base address of map0 table for the
 222                  * the board we're running on
 223                  */
 224                 la      t0,_boot_info
 225                 lw      t1,OFFSET_BOOTINFO_MACHTYPE(t0)
 226                 sll     t1,t1,2                 # machtype used as index
 227                 la      t0,map0table
 228                 addu    t0,t0,t1
 229                 lw      t0,(t0)                 # get base address
 230 
 231                 /*
 232                  * Get number of wired TLB entries and
 233                  * loop over selected map0 table.
 234                  */
 235                 lw      t1,(t0)                 # number of wired TLB entries
 236                 move    t2,zero                 # TLB entry counter
 237                 addiu   t3,t1,1                 # wire one additional entry
 238                 beqz    t1,2f                   # null, exit
 239                 mtc0    t3,CP0_WIRED            # delay slot
 240                 addiu   t0,t0,8
 241 1:              lw      t4,24(t0)               # PageMask
 242                 ld      t5,0(t0)                # entryHi
 243                 ld      t6,8(t0)                # entryLo0
 244                 ld      t7,16(t0)               # entryLo1
 245                 addiu   t2,t2,1                 # increment ctr
 246                 mtc0    t2,CP0_INDEX            # set TLB entry
 247                 mtc0    t4,CP0_PAGEMASK
 248                 dmtc0   t5,CP0_ENTRYHI
 249                 dmtc0   t6,CP0_ENTRYLO0
 250                 dmtc0   t7,CP0_ENTRYLO1
 251                 tlbwi 
 252                 bne     t1,t2,1b                # next TLB entry
 253                 addiu   t0,t0,32                # delay slot
 254 
 255                 /*
 256                  * We use only 4k pages. Therefore the PageMask register
 257                  * is expected to be setup for 4k pages.
 258                  */
 259 2:              li      t0,PM_4K
 260                 mtc0    t0,CP0_PAGEMASK
 261 
 262                 la      t1,_swapper_pg_dir      # swapper_pg_dir is at 0x1000
 263                 la      t2,_swapper_pg_dir+(PAGE_SIZE-4)
 264 1:              sw      zero,(t1)
 265                 bne     t1,t2,1b
 266                 addiu   t1,t1,4                 # delay slot
 267 
 268                 /*
 269                  * Setup invalid_pg_table and
 270                  * clear page table for the first 4MB
 271                  */
 272                 la      t0,_pg0                 # swapper_pg_dir is at 0x1000
 273                 la      t1,_pg0+PAGE_SIZE
 274                 li      t2,KERNELBASE
 275                 addu    t0,t2
 276                 addu    t1,t2
 277 1:              sw      zero,(t0)
 278                 addiu   t0,t0,4
 279                 bne     t0,t1,1b
 280                 addiu   t2,t2,4                 # delay slot
 281 
 282                 /*
 283                  * Identity-map the kernel in low 4MB memory for ease
 284                  * of transition. Unlike the Intel version the kernel
 285                  * code/data is automagically being mapped by kseg0.
 286                  */
 287                 la      t0,_pg0+PAGE_TABLE      # set valid bit/user r/w
 288                 sw      t0,_swapper_pg_dir
 289 
 290                 li      t0,PAGE_SHARED          # set valid bit/user r/w
 291                 la      t1,_pg0
 292                 la      t2,_pg0+PAGE_SIZE
 293                 li      t3,KERNELBASE
 294                 addu    t1,t3
 295                 addu    t2,t3
 296 1:              sw      t0,(t1)
 297                 addiu   t1,t1,4
 298                 bne     t1,t2,1b
 299                 addiu   t0,t0,PAGE_SIZE         # delay slot
 300 
 301                 /*
 302                  * Now map the pagetables
 303                  */
 304                 mtc0    zero,CP0_INDEX
 305                 la      t0,TLB_ROOT
 306                 dmtc0   t0,CP0_ENTRYHI
 307                 la      t0,_swapper_pg_dir
 308                 srl     t0,t0,6
 309                 ori     t0,t0,MODE_ALIAS        # uncachable, dirty, valid
 310                 dmtc0   t0,CP0_ENTRYLO0
 311                 dmtc0   zero,CP0_ENTRYLO1
 312                 tlbwi
 313                 /*
 314                  * Make page zero unaccessible to catch zero references
 315                  */
 316                 la      t0,_pg0
 317                 li      t0,KERNELBASE
 318                 addu    t0,t1
 319                 sw      zero,(t0)
 320                 /*
 321                  * Load the context register with a value that allows
 322                  * it to be used as fast as possible in tlb exceptions.
 323                  * It is expected that this register's content never
 324                  * will be changed.
 325                  */
 326                 li      t0,TLBMAP
 327                 dsll    t0,t0,1
 328                 jr      ra
 329                 dmtc0   t0,CP0_CONTEXT          # delay slot
 330 
 331                 /*
 332                  * Flush the TLB
 333                  *
 334                  * FIXME: knows only how to handle R4x00
 335                  * Read appendix f of the R4000 manual before you change
 336                  * something!
 337                  */
 338                 .globl  _tlbflush
 339 _tlbflush:      li      t0,PM_4K
 340                 mtc0    t0,CP0_PAGEMASK
 341                 lw      t0,_boot_info+OFFSET_BOOTINFO_TLB_ENTRIES(t0)
 342                 dmtc0   zero,CP0_ENTRYLO0
 343                 dmtc0   zero,CP0_ENTRYLO1
 344                 mfc0    t2,CP0_WIRED
 345 1:              subu    t0,t0,1
 346                 mtc0    t0,CP0_INDEX
 347                 lui     t1,0x0008
 348                 or      t1,t0,t1
 349                 dsll    t1,t1,13
 350                 dmtc0   t1,CP0_ENTRYHI
 351                 bne     t2,t0,1b
 352                 tlbwi                                   # delay slot
 353                 jr      ra
 354                 nop
 355 
 356 /*
 357  * Refill icache
 358  */
 359 #include <asm/mipsconfig.h>
 360 #include <asm/regdef.h>
 361 #include <asm/segment.h>
 362 
 363 #define PAGE_SIZE       0x1000
 364 
 365 #define CACHELINES      512             /* number of cachelines    */
 366 
 367                 .set    noreorder
 368                 .text
 369 refill:
 370                 /*
 371                  * Refill icache with cache fill command
 372                  */
 373                 li      t0,KSEG0
 374                 li      t1,CACHELINES
 375 1:              cache   21,0(t0)
 376                 cache   21,32(t0)
 377                 cache   21,64(t0)
 378                 cache   21,96(t0)
 379                 cache   21,128(t0)
 380                 cache   21,160(t0)
 381                 cache   21,192(t0)
 382                 cache   21,224(t0)
 383                 cache   21,256(t0)
 384                 cache   21,288(t0)
 385                 cache   21,320(t0)
 386                 cache   21,352(t0)
 387                 cache   21,384(t0)
 388                 cache   21,416(t0)
 389                 cache   21,448(t0)
 390                 cache   21,480(t0)
 391                 subu    t1,t1,1
 392                 bnez    t1,1b
 393                 addiu   t0,t0,512                       # delay slot
 394 
 395                 jr      ra
 396                 nop
 397 
 398 /*
 399  * Just for debugging...
 400  */
 401                 .globl  _beep
 402 _beep:          lw      t0,beepflag
 403                 nop
 404                 bnez    t0,1f
 405                 lbu     t0,0xe0000061
 406                 xori    t0,t0,3
 407                 sb      t0,0xe0000061
 408                 li      t0,1
 409                 sw      t0,beepflag
 410 1:              jr      ra
 411                 nop
 412 
 413 /*
 414  * Compute kernel code checksum to check kernel code against corruption
 415  */
 416                 .globl  _csum
 417 #if 0
 418 _csum:          jal     _sys_cacheflush
 419                 move    t8,ra                   # delay slot
 420 #else
 421 _csum:          move    t8,ra
 422 #endif
 423                 li      t0,KSEG1
 424                 la      t1,final
 425                 li      t2,KSEG1
 426                 or      t0,t2
 427                 or      t1,t2
 428                 move    v0,zero
 429 1:              lw      t2,(t0)
 430                 addiu   t0,t0,4
 431                 bne     t0,t1,1b
 432                 xor     v0,v0,t2
 433                 jr      t8
 434                 nop
 435 final:
 436 
 437                 .data
 438 /*
 439  * Initial mapping tables for supported Mips boards.
 440  * First item is always the number of wired TLB entries,
 441  * following by EntryHi/EntryLo pairs and page mask.
 442  * Since everything must be quad-aligned (8) we insert
 443  * some dummy zeros.
 444  */
 445 
 446 /*
 447  * Address table of mapping tables for supported Mips boards.
 448  * Add your own stuff here but don't forget to define your
 449  * target system in bootinfo.h
 450  */
 451 
 452 map0table:      .word   map0_dummy              # machtype = unknown
 453                 .word   map0_tyne               # Deskstation Tyne
 454                 .word   map0_pica61             # Acer Pica-61
 455 
 456 map0_dummy:     .word   0                       # 0 entries
 457 
 458 /*
 459  * Initial mappings for Deskstation Tyne boards.
 460  */
 461                 .align  8
 462 
 463 map0_tyne:      .word   3                       # no. of wired TLB entries
 464                 .word   0                       # pad for alignment
 465 
 466 # TLB entry 1: ISA I/O
 467 
 468                 .quad   0xffffffffe0000000      # TLB #0 EntryHi
 469                 .quad   0x24000017              # TLB #0 EntryLo0
 470                 .quad   0                       # TLB #0 EntryLo1
 471                 .word   PM_64K                  # page mask
 472                 .word   0                       # pad for alignment
 473 
 474 # TLB entry 2: ISA memory space
 475 
 476                 .quad   0xffffffffe1000000      # TLB #1 EntryHi
 477                 .quad   0x04000017              # TLB #1 EntryLo0
 478                 .quad   0                       # TLB #1 EntryLo1
 479                 .word   PM_1M
 480                 .word   0                       # pad for alignment
 481 
 482 # TLB entry 3: ISA DMA cache
 483 
 484                 .quad   0xffffffffe2000000      # TLB #2 EntryHi
 485                 .quad   0x04020017              # TLB #2 EntryLo0
 486                 .quad   0                       # TLB #2 EntryLo1
 487                 .word   PM_1M
 488                 .word   0                       # pad for alignment
 489 
 490 /*
 491  * Initial mapping for ACER PICA-61 boards.
 492  * FIXME: These are rather preliminary since many drivers,
 493  * such as serial, parallel, scsi and ethernet need some
 494  * changes to distinguish between "local" (built-in) and
 495  * "optional" (ISA/PCI) I/O hardware.
 496  * Local video ram is mapped to the same location as the
 497  * bios maps it to. Console driver has been changed
 498  * accordingly (new video type: VIDEO_TYPE_PICA_S3).
 499  */
 500 
 501 map0_pica61:    .word   9                       # no. wired TLB entries
 502                 .word   0                       # dummy
 503 
 504 # TLB entry 1: PROM
 505 
 506 #               .quad   0xffffffffe1000000      # BIOS mapping
 507                 .quad   0xffffffffe4000000      # new mapping
 508                 .quad   0x03ffc013
 509                 .quad   0x00000001              # global, not valid
 510                 .word   PM_256K
 511                 .word   0
 512 
 513 # TLB entry 2: local I/O space
 514 
 515                 .quad   0xffffffffe0000000
 516                 .quad   0x02000017
 517                 .quad   0x00000001              # global, not valid
 518                 .word   PM_64K
 519                 .word   0
 520 
 521 # TLB entry 3: DRAM config register
 522 
 523                 .quad   0xffffffffe00e0000
 524                 .quad   0x02003817
 525                 .quad   0x02003c17
 526                 .word   PM_64K
 527                 .word   0
 528 
 529 # TLB entry 4: Interrupt source register
 530 
 531                 .quad   0xffffffffe0100000
 532                 .quad   0x03c00017
 533                 .quad   0x00000001              # global, not valid
 534                 .word   PM_4K
 535                 .word   0
 536 
 537 # TLB entry 5: Local video control
 538 
 539                 .quad   0xffffffffe0200000
 540                 .quad   0x01800017
 541                 .quad   0x01804017
 542                 .word   PM_1M
 543                 .word   0
 544 
 545 # TLB entry 6: Extended video control
 546 
 547                 .quad   0xffffffffe0400000
 548                 .quad   0x01808017
 549                 .quad   0x0180c017
 550                 .word   PM_1M
 551                 .word   0
 552 
 553 # TLB entry 7: Local video memory (BIOS mapping)
 554 
 555                 .quad   0xffffffffe0800000
 556                 .quad   0x01000017
 557                 .quad   0x01010017
 558                 .word   PM_4M
 559                 .word   0
 560 
 561 # TLB entry 8: Local video memory (mapped to where Linux expects it)
 562 # not needed anymore
 563 #               .quad   0xffffffffe1000000
 564 #               .quad   0x01000017
 565 #               .quad   0x01010017
 566 #               .word   PM_4M
 567 #               .word   0
 568 
 569 # TLB entry 9: ISA I/O and ISA memory space (both 16M)
 570 
 571                 .quad   0xffffffffe2000000
 572                 .quad   0x02400017
 573                 .quad   0x02440017
 574                 .word   PM_16M
 575                 .word   0
 576 
 577 # TLB entry 10: PCR (???)
 578 
 579                 .quad   0xffffffffffffe000
 580                 .quad   0x00000001              # nonsense...
 581                 .quad   0x0001ffd7
 582                 .word   PM_4K
 583                 .word   0
 584 
 585 
 586 /* ------------------------------------------------
 587  * Mapping as presented by the PICA BIOS.
 588  * This table works. Please leave unmodified!
 589  * ------------------------------------------------ */
 590 #if 0
 591 map0_pica61:    .word   11                      # no. wired TLB entries
 592                 .word   0                       # dummy
 593 
 594 # TLB entry 0: Don't know what this is good for...
 595 
 596                 .quad   0xfffffffffffe2000
 597                 .quad   0x0000029e
 598                 .quad   0x00000000
 599                 .word   PM_4K
 600                 .word   0
 601 
 602 # TLB entry 1: PROM
 603 
 604                 .quad   0xffffffffe1000000
 605                 .quad   0x03ffc013
 606                 .quad   0x00000001              # nonsense ...
 607                 .word   PM_256K
 608                 .word   0
 609 
 610 # TLB entry 2: local I/O space
 611 
 612                 .quad   0xffffffffe0000000
 613                 .quad   0x02000017
 614                 .quad   0x00000001              # nonsense ...
 615                 .word   PM_64K
 616                 .word   0
 617 
 618 # TLB entry 3: DRAM config register
 619 
 620                 .quad   0xffffffffe00e0000
 621                 .quad   0x02003817
 622                 .quad   0x02003c17
 623                 .word   PM_64K
 624                 .word   0
 625 
 626 # TLB entry 4: Interrupt source register
 627 
 628                 .quad   0xffffffffe0100000
 629                 .quad   0x03c00017
 630                 .quad   0x00000001              # nonsense ...
 631                 .word   PM_4K
 632                 .word   0
 633 
 634 # TLB entry 5: Local video control
 635 
 636                 .quad   0xffffffffe0200000
 637                 .quad   0x01800017
 638                 .quad   0x01804017
 639                 .word   PM_1M
 640                 .word   0
 641 
 642 # TLB entry 6: Extended video control
 643 
 644                 .quad   0xffffffffe0400000
 645                 .quad   0x01808017
 646                 .quad   0x0180c017
 647                 .word   PM_1M
 648                 .word   0
 649 
 650 # TLB entry 7: Local video memory
 651 
 652                 .quad   0xffffffffe0800000
 653                 .quad   0x01000017
 654                 .quad   0x01010017
 655                 .word   PM_4M
 656                 .word   0
 657 
 658 # TLB entry 8: ISA I/O space
 659 
 660                 .quad   0xffffffffe2000000
 661                 .quad   0x02400017
 662                 .quad   0x02440017
 663                 .word   PM_16M
 664                 .word   0
 665 
 666 # TLB entry 9: PCR (???)
 667 
 668                 .quad   0xffffffffffffe000
 669                 .quad   0x00000001              # nonsense...
 670                 .quad   0x0001ffd7
 671                 .word   PM_4K
 672                 .word   0
 673 
 674 # TLB entry 10: Extended video prom
 675 
 676                 .quad   0xffffffff10000000
 677                 .quad   0x0000141f
 678                 .quad   0x00000001              # nonsense
 679                 .word   PM_64K
 680                 .word   0
 681 #endif
 682 
 683 /*
 684  * page 0 is made non-existent, so that kernel NULL pointer references get
 685  * caught. Thus the swapper page directory has been moved to 0x1000
 686  *
 687  * XXX Actually, the swapper page directory is at 0x1000 plus 1 megabyte,
 688  * with the introduction of the compressed boot code.  Theoretically,
 689  * the original design of overlaying the startup code with the swapper
 690  * page directory is still possible --- it would reduce the size of the kernel
 691  * by 2-3k.  This would be a good thing to do at some point.....
 692  */
 693                         .text
 694 
 695                         .org    0x1000
 696 _swapper_pg_dir         =       0x1000
 697 /*
 698  * The page tables are initialized to only 4MB here - the final page
 699  * tables are set up later depending on memory size.
 700  */
 701                         .org    0x2000
 702 _pg0                    =       0x2000
 703 
 704                         .org    0x3000
 705 _empty_bad_page         =       0x3000
 706 
 707                         .org    0x4000
 708 _empty_bad_page_table   =       0x4000
 709 
 710                         .org    0x5000
 711 _empty_zero_page        =       0x5000
 712 
 713                         .org    0x6000
 714 
 715 #if defined (CONFIG_DESKSTATION_TYNE) && !defined (CONFIG_ACER_PICA_61)
 716 #if 0
 717 /*
 718  * tmp_floppy_area is used by the floppy-driver when DMA cannot
 719  * reach to a buffer-block. It needs to be aligned, so that it isn't
 720  * on a 64kB border.
 721  */
 722                         .globl  _tmp_floppy_area
 723 _tmp_floppy_area:       .fill   1024,1,0
 724 #endif
 725 /*
 726  * floppy_track_buffer is used to buffer one track of floppy data: it
 727  * has to be separate from the tmp_floppy area, as otherwise a single-
 728  * sector read/write can mess it up. It can contain one full cylinder (sic) of
 729  * data (36*2*512 bytes).
 730  */
 731                         .globl  _floppy_track_buffer
 732 _floppy_track_buffer:   .fill   512*2*36,1,0
 733 #endif /* defined (CONFIG_DESKSTATION_TYNE) && !defined (CONFIG_ACER_PICA_61) */
 734                         .globl  _kernelsp
 735 _kernelsp:              .word   0
 736 beepflag:               .word   0

/* */