drivers/net/8390.h

/* */
   1 /* Generic NS8390 register definitions. */
   2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
   3    under the same license.
   4    Some of these names and comments originated from the Crynwr
   5    packet drivers, which are distributed under the GPL. */
   6 
   7 #ifndef _8390_h
   8 #define _8390_h
   9 
  10 #include <linux/if_ether.h>
  11 #include <linux/ioport.h>
  12 
  13 #define TX_2X_PAGES 12
  14 #define TX_1X_PAGES 6
  15 #define TX_PAGES (ei_status.pingpong ? TX_2X_PAGES : TX_1X_PAGES)
  16 
  17 #define ETHER_ADDR_LEN 6
  18 
  19 /* From 8390.c */
  20 extern int ei_debug;
  21 extern struct sigaction ei_sigaction;
  22 
  23 extern int ethif_init(struct device *dev);
  24 extern int ethdev_init(struct device *dev);
  25 extern void NS8390_init(struct device *dev, int startp);
  26 extern int ei_open(struct device *dev);
  27 extern void ei_interrupt(int irq, struct pt_regs *regs);
  28 
  29 #ifndef HAVE_AUTOIRQ
  30 /* From auto_irq.c */
  31 extern struct device *irq2dev_map[16];
  32 extern void autoirq_setup(int waittime);
  33 extern int autoirq_report(int waittime);
  34 #endif
  35 
  36 /* Most of these entries should be in 'struct device' (or most of the
  37    things in there should be here!) */
  38 /* You have one of these per-board */
  39 struct ei_device {
  40   char *name;
  41   void (*reset_8390)(struct device *);
  42   void (*block_output)(struct device *, int, const unsigned char *, int);
  43   int  (*block_input)(struct device *, int, char *, int);
  44   unsigned open:1;
  45   unsigned word16:1;  /* We have the 16-bit (vs 8-bit) version of the card. */
  46   unsigned txing:1;             /* Transmit Active */
  47   unsigned irqlock:1;           /* 8390's intrs disabled when '1'. */
  48   unsigned pingpong:1;          /* Using the ping-pong driver */
  49   unsigned char tx_start_page, rx_start_page, stop_page;
  50   unsigned char current_page;   /* Read pointer in buffer  */
  51   unsigned char interface_num;  /* Net port (AUI, 10bT.) to use. */
  52   unsigned char txqueue;        /* Tx Packet buffer queue length. */
  53   unsigned char dmaing;         /* Remote DMA (Tx/Rx/Active) */
  54   short tx1, tx2;               /* Packet lengths for ping-pong tx. */
  55   short lasttx;                 /* Alpha version consistency check. */
  56   unsigned char reg0;           /* Register '0' in a WD8013 */
  57   unsigned char reg5;           /* Register '5' in a WD8013 */
  58   unsigned char saved_irq;      /* Original dev->irq value. */
  59   /* The new statistics table. */
  60   struct enet_statistics stat;
  61 };
  62 
  63 /* The maximum number of 8390 interrupt serivce routines called per IRQ. */
  64 #define MAX_SERVICE 12
  65 
  66 /* The maximum number of jiffies waited before assuming a Tx failed. */
  67 #define TX_TIMEOUT 20 
  68 
  69 #define ei_status (*(struct ei_device *)(dev->priv))
  70 
  71 /* Some generic ethernet register configurations. */
  72 #define E8390_TX_IRQ_MASK 0xa   /* For register EN0_ISR */
  73 #define E8390_RX_IRQ_MASK  0x5
  74 #define E8390_RXCONFIG 0x4      /* EN0_RXCR: broadcasts, no multicast,errors */
  75 #define E8390_RXOFF 0x20        /* EN0_RXCR: Accept no packets */
  76 #define E8390_TXCONFIG 0x00     /* EN0_TXCR: Normal transmit mode */
  77 #define E8390_TXOFF 0x02        /* EN0_TXCR: Transmitter off */
  78 
  79 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  80 #define E8390_STOP      0x01    /* Stop and reset the chip */
  81 #define E8390_START     0x02    /* Start the chip, clear reset */
  82 #define E8390_TRANS     0x04    /* Transmit a frame */
  83 #define E8390_RREAD     0x08    /* Remote read */
  84 #define E8390_RWRITE    0x10    /* Remote write  */
  85 #define E8390_NODMA     0x20    /* Remote DMA */
  86 #define E8390_PAGE0     0x00    /* Select page chip registers */
  87 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  88 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  89 
  90 #define E8390_CMD       0x00    /* The command register (for all pages) */
  91 /* Page 0 register offsets. */
  92 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  93 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  94 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  95 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  96 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  97 #define EN0_TSR         0x04    /* Transmit status reg RD */
  98 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  99 #define EN0_NCR         0x05    /* Number of collision reg RD */
 100 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
 101 #define EN0_FIFO        0x06    /* FIFO RD */
 102 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
 103 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
 104 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
 105 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
 106 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
 107 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
 108 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
 109 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
 110 #define EN0_RSR         0x0c    /* rx status reg RD */
 111 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
 112 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
 113 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
 114 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
 115 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
 116 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
 117 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
 118 
 119 /* Bits in EN0_ISR - Interrupt status register */
 120 #define ENISR_RX        0x01    /* Receiver, no error */
 121 #define ENISR_TX        0x02    /* Transmitter, no error */
 122 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
 123 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
 124 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
 125 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
 126 #define ENISR_RDC       0x40    /* remote dma complete */
 127 #define ENISR_RESET     0x80    /* Reset completed */
 128 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 129 
 130 /* Bits in EN0_DCFG - Data config register */
 131 #define ENDCFG_WTS      0x01    /* word transfer mode selection */
 132 
 133 /* Page 1 register offsets. */
 134 #define EN1_PHYS   0x01 /* This board's physical enet addr RD WR */
 135 #define EN1_CURPAG 0x07 /* Current memory page RD WR */
 136 #define EN1_MULT   0x08 /* Multicast filter mask array (8 bytes) RD WR */
 137 
 138 /* Bits in received packet status byte and EN0_RSR*/
 139 #define ENRSR_RXOK      0x01    /* Received a good packet */
 140 #define ENRSR_CRC       0x02    /* CRC error */
 141 #define ENRSR_FAE       0x04    /* frame alignment error */
 142 #define ENRSR_FO        0x08    /* FIFO overrun */
 143 #define ENRSR_MPA       0x10    /* missed pkt */
 144 #define ENRSR_PHY       0x20    /* physical/multicase address */
 145 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 146 #define ENRSR_DEF       0x80    /* deferring */
 147 
 148 /* Transmitted packet status, EN0_TSR. */
 149 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 150 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 151 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 152 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 153 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 154 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 155 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 156 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 157 
 158 /* The per-packet-header format. */
 159 struct e8390_pkt_hdr {
 160   unsigned char status; /* status */
 161   unsigned char next;   /* pointer to next packet. */
 162   unsigned short count; /* header + packet length in bytes */
 163 };
 164 #endif /* _8390_h */
/* */
root/drivers/net/8390.h

INCLUDED FROM
