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*/
1 /*
2 * NCR 53c{7,8}0x0 driver, header file
3 *
4 * Sponsored by
5 * iX Multiuser Multitasking Magazine
6 * Hannover, Germany
7 * hm@ix.de
8 *
9 * Copyright 1993, Drew Eckhardt
10 * Visionary Computing
11 * (Unix and Linux consulting and custom programming)
12 * drew@Colorado.EDU
13 * +1 (303) 786-7975
14 *
15 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
16 *
17 * PRE-ALPHA
18 *
19 * For more information, please consult
20 *
21 * NCR 53C700/53C700-66
22 * SCSI I/O Processor
23 * Data Manual
24 *
25 * NCR 53C810
26 * PCI-SCSI I/O Processor
27 * Data Manual
28 *
29 * NCR Microelectronics
30 * 1635 Aeroplaza Drive
31 * Colorado Springs, CO 80916
32 * +1 (719) 578-3400
33 *
34 * Toll free literature number
35 * +1 (800) 334-5454
36 *
37 */
38
39 #ifndef NCR53c7x0_H
40 #define NCR53c7x0_H
41
42
43 /*
44 * Prevent name space pollution in hosts.c, and only provide the
45 * define we need to get the NCR53c7x0 driver into the host template
46 * array.
47 */
48
49 #if defined(HOSTS_C) || defined(MODULE)
50 #include <linux/scsicam.h>
51 extern int NCR53c7xx_abort(Scsi_Cmnd *);
52 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
53 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
54 extern int NCR53c7xx_reset(Scsi_Cmnd *);
55 #ifdef MODULE
56 extern int NCR53c7xx_release(struct Scsi_Host *);
57 #else
58 #define NCR53c7xx_release NULL
59 #endif
60
61 #define NCR53c7xx {NULL, NULL, "NCR53c{7,8}xx (rel 4)", NCR53c7xx_detect, \
62 NULL, /* info */ NULL, /* command, deprecated */ NULL, \
63 NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
64 NULL /* slave attach */, scsicam_bios_param, /* can queue */ 1, \
65 /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 1 , \
66 /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
67 #endif /* defined(HOSTS_C) || defined(MODULE) */
68
69 #ifndef HOSTS_C
70 /* Register addresses, ordered numerically */
71
72
73 /* SCSI control 0 rw, default = 0xc0 */
74 #define SCNTL0_REG 0x00
75 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
76 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
77 #define SCNTL0_STRT 0x20 /* Start Sequence */
78 #define SCNTL0_WATN 0x10 /* Select with ATN */
79 #define SCNTL0_EPC 0x08 /* Enable parity checking */
80 /* Bit 2 is reserved on 800 series chips */
81 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
82 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
83 #define SCNTL0_TRG 0x01 /* Target mode */
84
85 /* SCSI control 1 rw, default = 0x00 */
86
87 #define SCNTL1_REG 0x01
88 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
89 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
90 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
91 and reselection */
92 #define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
93 target mode only */
94 #define SCNTL1_CON 0x10 /* Connected */
95 #define SCNTL1_RST 0x08 /* SCSI RST/ */
96 #define SCNTL1_AESP 0x04 /* Force bad parity */
97 #define SCNTL1_SND_700 0x02 /* Start SCSI send */
98 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
99 arbitration immediately after
100 busfree is detected */
101 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
102 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
103
104 /* SCSI control 2 rw, */
105
106 #define SCNTL2_REG_800 0x02
107 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
108
109 /* SCSI control 3 rw */
110
111 #define SCNTL3_REG_800 0x03
112 #define SCNTL3_800_SCF_SHIFT 4
113 #define SCNTL3_800_SCF_MASK 0x70
114 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
115 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
116 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
117 /* 0x20 = SCLK/1.5
118 0x30 = SCLK/2
119 0x40 = SCLK/3 */
120
121 #define SCNTL3_800_CCF_SHIFT 0
122 #define SCNTL3_800_CCF_MASK 0x07
123 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
124 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
125 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
126 0x03 37.51 - 50
127 0x04 50.01 - 66 */
128
129 /*
130 * SCSI destination ID rw - the appropriate bit is set for the selected
131 * target ID. This is written by the SCSI SCRIPTS processor.
132 * default = 0x00
133 */
134 #define SDID_REG_700 0x02
135 #define SDID_REG_800 0x06
136
137 #define GP_REG_800 0x07 /* General purpose IO */
138 #define GP_800_IO1 0x02
139 #define GP_800_IO2 0x01
140
141
142 /* SCSI interrupt enable rw, default = 0x00 */
143 #define SIEN_REG_700 0x03
144 #define SIEN0_REG_800 0x40
145 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
146 #define SIEN_FC 0x40 /* Function complete */
147 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
148 #define SIEN_800_SEL 0x20 /* Selected */
149 #define SIEN_700_SEL 0x10 /* Selected or reselected */
150 #define SIEN_800_RESEL 0x10 /* Reselected */
151 #define SIEN_SGE 0x08 /* SCSI gross error */
152 #define SIEN_UDC 0x04 /* Unexpected disconnect */
153 #define SIEN_RST 0x02 /* SCSI RST/ received */
154 #define SIEN_PAR 0x01 /* Parity error */
155
156 /*
157 * SCSI chip ID rw
158 * NCR53c700 :
159 * When arbitrating, the highest bit is used, when reselection or selection
160 * occurs, the chip responds to all IDs for which a bit is set.
161 * default = 0x00
162 * NCR53c810 :
163 * Uses bit mapping
164 */
165 #define SCID_REG 0x04
166 /* Bit 7 is reserved on 800 series chips */
167 #define SCID_800_RRE 0x40 /* Enable response to reselection */
168 #define SCID_800_SRE 0x20 /* Enable response to selection */
169 /* Bits four and three are reserved on 800 series chips */
170 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
171
172 /* SCSI transfer rw, default = 0x00 */
173 #define SXFER_REG 0x05
174 #define SXFER_DHP 0x80 /* Disable halt on parity */
175
176 #define SXFER_TP2 0x40 /* Transfer period msb */
177 #define SXFER_TP1 0x20
178 #define SXFER_TP0 0x10 /* lsb */
179 #define SXFER_TP_MASK 0x70
180 #define SXFER_TP_SHIFT 4
181 #define SXFER_TP_4 0x00 /* Divisors */
182 #define SXFER_TP_5 0x10
183 #define SXFER_TP_6 0x20
184 #define SXFER_TP_7 0x30
185 #define SXFER_TP_8 0x40
186 #define SXFER_TP_9 0x50
187 #define SXFER_TP_10 0x60
188 #define SXFER_TP_11 0x70
189
190 #define SXFER_MO3 0x08 /* Max offset msb */
191 #define SXFER_MO2 0x04
192 #define SXFER_MO1 0x02
193 #define SXFER_MO0 0x01 /* lsb */
194 #define SXFER_MO_MASK 0x0f
195 #define SXFER_MO_SHIFT 0
196
197 /*
198 * SCSI output data latch rw
199 * The contents of this register are driven onto the SCSI bus when
200 * the Assert Data Bus bit of the SCNTL1 register is set and
201 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
202 */
203 #define SODL_REG_700 0x06
204 #define SODL_REG_800 0x54
205
206
207 /*
208 * SCSI output control latch rw, default = 0
209 * Note that when the chip is being manually programmed as an initiator,
210 * the MSG, CD, and IO bits must be set correctly for the phase the target
211 * is driving the bus in. Otherwise no data transfer will occur due to
212 * phase mismatch.
213 */
214
215 #define SBCL_REG 0x0b
216 #define SBCL_REQ 0x80 /* REQ */
217 #define SBCL_ACK 0x40 /* ACK */
218 #define SBCL_BSY 0x20 /* BSY */
219 #define SBCL_SEL 0x10 /* SEL */
220 #define SBCL_ATN 0x08 /* ATN */
221 #define SBCL_MSG 0x04 /* MSG */
222 #define SBCL_CD 0x02 /* C/D */
223 #define SBCL_IO 0x01 /* I/O */
224 #define SBCL_PHASE_CMDOUT SBCL_CD
225 #define SBCL_PHASE_DATAIN SBCL_IO
226 #define SBCL_PHASE_DATAOUT 0
227 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
228 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
229 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
230 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
231
232 /*
233 * SCSI first byte received latch ro
234 * This register contains the first byte received during a block MOVE
235 * SCSI SCRIPTS instruction, including
236 *
237 * Initiator mode Target mode
238 * Message in Command
239 * Status Message out
240 * Data in Data out
241 *
242 * It also contains the selecting or reselecting device's ID and our
243 * ID.
244 *
245 * Note that this is the register the various IF conditionals can
246 * operate on.
247 */
248 #define SFBR_REG 0x08
249
250 /*
251 * SCSI input data latch ro
252 * In initiator mode, data is latched into this register on the rising
253 * edge of REQ/. In target mode, data is latched on the rising edge of
254 * ACK/
255 */
256 #define SIDL_REG_700 0x09
257 #define SIDL_REG_800 0x50
258
259 /*
260 * SCSI bus data lines ro
261 * This register reflects the instantaneous status of the SCSI data
262 * lines. Note that SCNTL0 must be set to disable parity checking,
263 * otherwise reading this register will latch new parity.
264 */
265 #define SBDL_REG_700 0x0a
266 #define SBDL_REG_800 0x58
267
268 #define SSID_REG_800 0x0a
269 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
270 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
271
272
273 /*
274 * SCSI bus control lines rw,
275 * instantaneous readout of control lines
276 */
277 #define SOCL_REG 0x0b
278 #define SOCL_REQ 0x80 /* REQ ro */
279 #define SOCL_ACK 0x40 /* ACK ro */
280 #define SOCL_BSY 0x20 /* BSY ro */
281 #define SOCL_SEL 0x10 /* SEL ro */
282 #define SOCL_ATN 0x08 /* ATN ro */
283 #define SOCL_MSG 0x04 /* MSG ro */
284 #define SOCL_CD 0x02 /* C/D ro */
285 #define SOCL_IO 0x01 /* I/O ro */
286 /*
287 * Synchronous SCSI Clock Control bits
288 * 0 - set by DCNTL
289 * 1 - SCLK / 1.0
290 * 2 - SCLK / 1.5
291 * 3 - SCLK / 2.0
292 */
293 #define SBCL_SSCF1 0x02 /* wo, -66 only */
294 #define SBCL_SSCF0 0x01 /* wo, -66 only */
295 #define SBCL_SSCF_MASK 0x03
296
297 /*
298 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
299 * insure that 10 clocks elapse between the two
300 */
301 /* DMA status ro */
302 #define DSTAT_REG 0x0c
303 #define DSTAT_DFE 0x80 /* DMA FIFO empty */
304 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
305 #define DSTAT_800_BF 0x20 /* Bus Fault */
306 #define DSTAT_ABRT 0x10 /* Aborted - set on error */
307 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
308 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
309 set when INT instruction is
310 executed */
311 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
312 #define DSTAT_OPC 0x01 /* Illegal instruction */
313 #define DSTAT_800_IID 0x01 /* Same thing, different name */
314
315
316 #define SSTAT0_REG 0x0d /* SCSI status 0 ro */
317 #define SIST0_REG_800 0x42
318 #define SSTAT0_MA 0x80 /* ini : phase mismatch,
319 * tgt : ATN/ asserted
320 */
321 #define SSTAT0_CMP 0x40 /* function complete */
322 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
323 #define SIST0_800_SEL 0x20 /* Selected */
324 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
325 #define SIST0_800_RSL 0x10 /* Reselected */
326 #define SSTAT0_SGE 0x08 /* SCSI gross error */
327 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
328 #define SSTAT0_RST 0x02 /* SCSI RST/ received */
329 #define SSTAT0_PAR 0x01 /* Parity error */
330
331 #define SSTAT1_REG 0x0e /* SCSI status 1 ro */
332 #define SSTAT1_ILF 0x80 /* SIDL full */
333 #define SSTAT1_ORF 0x40 /* SODR full */
334 #define SSTAT1_OLF 0x20 /* SODL full */
335 #define SSTAT1_AIP 0x10 /* Arbitration in progress */
336 #define SSTAT1_LOA 0x08 /* Lost arbitration */
337 #define SSTAT1_WOA 0x04 /* Won arbitration */
338 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
339 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
340
341 #define SSTAT2_REG 0x0f /* SCSI status 2 ro */
342 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
343 #define SSTAT2_FF2 0x40 /* data FIFO */
344 #define SSTAT2_FF1 0x20
345 #define SSTAT2_FF0 0x10
346 #define SSTAT2_FF_MASK 0xf0
347
348 /*
349 * Latched signals, latched on the leading edge of REQ/ for initiators,
350 * ACK/ for targets.
351 */
352 #define SSTAT2_SDP 0x08 /* SDP */
353 #define SSTAT2_MSG 0x04 /* MSG */
354 #define SSTAT2_CD 0x02 /* C/D */
355 #define SSTAT2_IO 0x01 /* I/O */
356
357
358 /* NCR53c700-66 only */
359 #define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
360 /* NCR53c710 and higher */
361 #define DSA_REG 0x10 /* DATA structure address */
362
363 #define CTEST0_REG_700 0x14 /* Chip test 0 ro */
364 #define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
365 /* 0x80 - 0x04 are reserved */
366 #define CTEST0_700_RTRG 0x02 /* Real target mode */
367 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
368 * SCSI bus to host, 0 =
369 * host to SCSI.
370 */
371
372 #define CTEST1_REG_700 0x15 /* Chip test 1 ro */
373 #define CTEST1_REG_800 0x19 /* Chip test 1 ro */
374 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
375 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
376 #define CTEST1_FMT1 0x20
377 #define CTEST1_FMT0 0x10
378
379 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
380 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
381 #define CTEST1_FFL1 0x02
382 #define CTEST1_FFL0 0x01
383
384 #define CTEST2_REG_700 0x16 /* Chip test 2 ro */
385 #define CTEST2_REG_800 0x1a /* Chip test 2 ro */
386
387 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
388 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
389 Reading this register clears */
390 #define CTEST2_800_CIO 0x20 /* Configured as IO */.
391 #define CTEST2_800_CM 0x10 /* Configured as memory */
392
393 /* 0x80 - 0x40 are reserved on 700 series chips */
394 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
395 * As an initiator, this bit is
396 * one when the synchronous offset
397 * is zero, as a target this bit
398 * is one when the synchronous
399 * offset is at the maximum
400 * defined in SXFER
401 */
402 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
403 * reading CTEST3 unloads a byte
404 * from the FIFO and sets this
405 */
406 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
407 * reading CTEST6 unloads a byte
408 * from the FIFO and sets this
409 */
410 #define CTEST2_TEOP 0x04 /* SCSI true end of process,
411 * indicates a totally finished
412 * transfer
413 */
414 #define CTEST2_DREQ 0x02 /* Data request signal */
415 /* 0x01 is reserved on 700 series chips */
416 #define CTEST2_800_DACK 0x01
417
418 /*
419 * Chip test 3 ro
420 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
421 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
422 * error results if a read is attempted on this register. Also note
423 * that 16 and 32 bit reads of this register will cause corruption.
424 */
425 #define CTEST3_REG_700 0x17
426 /* Chip test 3 rw */
427 #define CTEST3_REG_800 0x1b
428 #define CTEST3_800_V3 0x80 /* Chip revision */
429 #define CTEST3_800_V2 0x40
430 #define CTEST3_800_V1 0x20
431 #define CTEST3_800_V0 0x10
432 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
433 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
434 #define CTEST3_800_FM 0x02 /* Fetch mode pin */
435 /* bit 0 is reserved on 800 series chips */
436
437 #define CTEST4_REG_700 0x18 /* Chip test 4 rw */
438 #define CTEST4_REG_800 0x21 /* Chip test 4 rw */
439 /* 0x80 is reserved on 700 series chips */
440 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
441 #define CTEST4_ZMOD 0x40 /* High impedance mode */
442 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
443 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
444 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
445 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
446 * redirects writes from SODL
447 * to the SCSI FIFO.
448 */
449 #define CTEST4_800_MPEE 0x08 /* Enable parity checking
450 during master cycles on PCI
451 bus */
452
453 /*
454 * These bits send the contents of the CTEST6 register to the appropriate
455 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
456 * the high bit means the low two bits select the byte lane.
457 */
458 #define CTEST4_FBL2 0x04
459 #define CTEST4_FBL1 0x02
460 #define CTEST4_FBL0 0x01
461 #define CTEST4_FBL_MASK 0x07
462 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
463 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
464 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
465 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
466 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
467
468
469 #define CTEST5_REG_700 0x19 /* Chip test 5 rw */
470 #define CTEST5_REG_800 0x22 /* Chip test 5 rw */
471 /*
472 * Clock Address Incrementor. When set, it increments the
473 * DNAD register to the next bus size boundary. It automatically
474 * resets itself when the operation is complete.
475 */
476 #define CTEST5_ADCK 0x80
477 /*
478 * Clock Byte Counter. When set, it decrements the DBC register to
479 * the next bus size boundary.
480 */
481 #define CTEST5_BBCK 0x40
482 /*
483 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
484 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
485 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
486 * be cleared when a synchronous transfer fails. When written, it is
487 * automatically cleared after the SCSI synchronous offset counter is
488 * reset.
489 */
490 /* Bit 5 is reserved on 800 series chips */
491 #define CTEST5_700_ROFF 0x20
492 /*
493 * Master Control for Set or Reset pulses. When 1, causes the low
494 * four bits of register to set when set, 0 causes the low bits to
495 * clear when set.
496 */
497 #define CTEST5_MASR 0x10
498 #define CTEST5_DDIR 0x08 /* DMA direction */
499 /*
500 * Bits 2-0 are reserved on 800 series chips
501 */
502 #define CTEST5_700_EOP 0x04 /* End of process */
503 #define CTEST5_700_DREQ 0x02 /* Data request */
504 #define CTEST5_700_DACK 0x01 /* Data acknowledge */
505
506 /*
507 * Chip test 6 rw - writing to this register writes to the byte
508 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
509 * register.
510 */
511 #define CTEST6_REG_700 0x1a
512 #define CTEST6_REG_800 0x23
513
514 #define CTEST7_REG 0x1b /* Chip test 7 rw */
515 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
516 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
517 #define CTEST7_10_SC1 0x40 /* Snoop control bits */
518 #define CTEST7_10_SC0 0x20
519 #define CTEST7_10_SC_MASK 0x60
520 /* 0x20 is reserved on the NCR53c700 */
521 #define CTEST7_0060_FM 0x20 /* Fetch mode */
522 #define CTEST7_STD 0x10 /* Selection timeout disable */
523 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
524 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
525 #define CTEST7_10_TT1 0x02 /* Transfer type */
526 #define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
527 fetch */
528 #define CTEST7_DIFF 0x01 /* Differential mode */
529
530 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
531
532
533 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
534
535 #define DFIFO_REG 0x20 /* DMA FIFO rw */
536 /*
537 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
538 * moved into the CTEST8 register.
539 */
540 #define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
541 #define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
542 #define DFIFO_BO6 0x40
543 #define DFIFO_BO5 0x20
544 #define DFIFO_BO4 0x10
545 #define DFIFO_BO3 0x08
546 #define DFIFO_BO2 0x04
547 #define DFIFO_BO1 0x02
548 #define DFIFO_BO0 0x01
549 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
550 #define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
551
552 /*
553 * Interrupt status rw
554 * Note that this is the only register which can be read while SCSI
555 * SCRIPTS are being executed.
556 */
557 #define ISTAT_REG_700 0x21
558 #define ISTAT_REG_800 0x14
559 #define ISTAT_ABRT 0x80 /* Software abort, write
560 *1 to abort, wait for interrupt. */
561 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
562 #define ISTAT_10_SRST 0x40 /* software reset */
563 #define ISTAT_10_SIGP 0x20 /* signal script */
564 /* 0x10 is reserved on NCR53c700 series chips */
565 #define ISTAT_800_SEM 0x10 /* semaphore */
566 #define ISTAT_CON 0x08 /* 1 when connected */
567 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
568 #define ISTAT_700_PRE 0x04 /* Pointer register empty.
569 * Set to 1 when DSPS and DSP
570 * registers are empty in pipeline
571 * mode, always set otherwise.
572 */
573 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
574 * SCSI portion of SIOP see
575 * SSTAT0
576 */
577 #define ISTAT_DIP 0x01 /* DMA interrupt pending
578 * see DSTAT
579 */
580
581 /* NCR53c700-66 and NCR53c710 only */
582 #define CTEST8_REG 0x22 /* Chip test 8 rw */
583 #define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
584 * ie read from SCLK/ rather than CLK/
585 */
586 #define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
587 #define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
588 * pass through. This insures that
589 * bad parity won't reach the host
590 * bus.
591 */
592 #define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
593 * active negation, should only
594 * be used for slow SCSI
595 * non-differential.
596 */
597 #define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
598 #define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
599 * must be set for fast SCSI-II
600 * speeds.
601 */
602 #define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
603 * switching.
604 */
605 #define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
606 * The status of pending
607 * disconnect is maintained by
608 * the core, eliminating
609 * the possibility of missing a
610 * selection or reselection
611 * while waiting to fetch a
612 * WAIT DISCONNECT opcode.
613 */
614
615 #define CTEST8_10_V3 0x80 /* Chip revision */
616 #define CTEST8_10_V2 0x40
617 #define CTEST8_10_V1 0x20
618 #define CTEST8_10_V0 0x10
619 #define CTEST8_10_V_MASK 0xf0
620 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
621 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
622 #define CTEST8_10_FM 0x02 /* Fetch pin mode */
623 #define CTEST8_10_SM 0x01 /* Snoop pin mode */
624
625
626 /*
627 * The CTEST9 register may be used to differentiate between a
628 * NCR53c700 and a NCR53c710.
629 *
630 * Write 0xff to this register.
631 * Read it.
632 * If the contents are 0xff, it is a NCR53c700
633 * If the contents are 0x00, it is a NCR53c700-66 first revision
634 * If the contents are some other value, it is some other NCR53c700-66
635 */
636 #define CTEST9_REG_00 0x23 /* Chip test 9 ro */
637 #define LCRC_REG_10 0x23
638
639 /*
640 * 0x24 through 0x27 are the DMA byte counter register. Instructions
641 * write their high 8 bits into the DCMD register, the low 24 bits into
642 * the DBC register.
643 *
644 * Function is dependent on the command type being executed.
645 */
646
647
648 #define DBC_REG 0x24
649 /*
650 * For Block Move Instructions, DBC is a 24 bit quantity representing
651 * the number of bytes to transfer.
652 * For Transfer Control Instructions, DBC is bit fielded as follows :
653 */
654 /* Bits 20 - 23 should be clear */
655 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
656 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
657 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
658 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
659 /* Bits 8 - 15 are reserved on some implementations ? */
660 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
661 #define DBC_TCI_MASK_SHIFT 8
662 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
663 #define DBC_TCI_DATA_SHIFT 0
664
665 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
666 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
667 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
668 #define DBC_RWRI_ADDRESS_SHIFT 16
669
670
671 /*
672 * DMA command r/w
673 */
674 #define DCMD_REG 0x27
675 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
676 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
677 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
678 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
679 #define DCMD_BMI_MSG 0x04 /* instruction */
680
681 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
682 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
683 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
684
685 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
686
687 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
688 instruction */
689 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
690 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
691 #define DCMD_TCI_MSG 0x04 /* instruction */
692 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
693 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
694 #define DCMD_TCI_OP_CALL 0x08 /* CALL */
695 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
696 #define DCMD_TCI_OP_INT 0x18 /* INT */
697
698 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
699 instruction */
700 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
701 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
702 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
703 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
704
705 #define DCMD_RWRI_OP_MASK 0x07
706 #define DCMD_RWRI_OP_MOVE 0x00
707 #define DCMD_RWRI_OP_SHL 0x01
708 #define DCMD_RWRI_OP_OR 0x02
709 #define DCMD_RWRI_OP_XOR 0x03
710 #define DCMD_RWRI_OP_AND 0x04
711 #define DCMD_RWRI_OP_SHR 0x05
712 #define DCMD_RWRI_OP_ADD 0x06
713 #define DCMD_RWRI_OP_ADDC 0x07
714
715 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
716 (three longs) */
717
718
719 #define DNAD_REG 0x28 /* through 0x2b DMA next address for
720 data */
721 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
722 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
723 save rw */
724 #define DMODE_REG_00 0x34 /* DMA mode rw */
725 #define DMODE_00_BL1 0x80 /* Burst length bits */
726 #define DMODE_00_BL0 0x40
727 #define DMODE_BL_MASK 0xc0
728 /* Burst lengths (800) */
729 #define DMODE_BL_2 0x00 /* 2 transfer */
730 #define DMODE_BL_4 0x40 /* 4 transfers */
731 #define DMODE_BL_8 0x80 /* 8 transfers */
732 #define DMODE_BL_16 0xc0 /* 16 transfers */
733
734 #define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
735 #define DMODE_700_286 0x10 /* 286 mode */
736 #define DMODE_700_IOM 0x08 /* Transfer to IO port */
737 #define DMODE_700_FAM 0x04 /* Fixed address mode */
738 #define DMODE_700_PIPE 0x02 /* Pipeline mode disables
739 * automatic fetch / exec
740 */
741 #define DMODE_MAN 0x01 /* Manual start mode,
742 * requires a 1 to be written
743 * to the start DMA bit in the DCNTL
744 * register to run scripts
745 */
746
747 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
748
749 /* NCR53c800 series only */
750 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
751 /* NCR53c710 only */
752 #define SCRATCB_REG_10 0x34 /* through 0x37 scratch B rw */
753
754 #define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
755 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
756 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
757 #define DMODE_800_ERL 0x08 /* Enable Read Line */
758
759 /* 35-38 are reserved on 700 and 700-66 series chips */
760 #define DIEN_REG 0x39 /* DMA interrupt enable rw */
761 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
762 #define DIEN_800_MDPE 0x40 /* Master data parity error */
763 #define DIEN_800_BF 0x20 /* BUS fault */
764 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
765 #define DIEN_SSI 0x08 /* Enable single step interrupt */
766 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
767 * interrupt
768 */
769 /* 0x02 is reserved on 800 series chips */
770 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
771 #define DIEN_700_OPC 0x01 /* Enable illegal instruction
772 * interrupt
773 */
774 #define DIEN_800_IID 0x01 /* Same meaning, different name */
775
776 /*
777 * DMA watchdog timer rw
778 * set in 16 CLK input periods.
779 */
780 #define DWT_REG 0x3a
781
782 /* DMA control rw */
783 #define DCNTL_REG 0x3b
784 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
785 #define DCNTL_700_CF0 0x40
786 #define DCNTL_700_CF_MASK 0xc0
787 /* Clock divisors Divisor SCLK range (MHZ) */
788 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
789 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
790 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
791 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
792
793 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
794 #define DCNTL_SSM 0x10 /* Single step mode */
795 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
796 * after selection */
797 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
798 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
799 /* 0x02 is reserved */
800 #define DCNTL_00_RST 0x01 /* Software reset, resets everything
801 * but 286 mode bit in DMODE. On the
802 * NCR53c710, this bit moved to CTEST8
803 */
804 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
805
806 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
807
808
809 /* NCR53c700-66 only */
810 #define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
811 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
812 /* NCR53c710 only */
813 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
814
815 #define SIEN1_REG_800 0x41
816 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
817 #define SIEN1_800_GEN 0x02 /* general purpose timer */
818 #define SIEN1_800_HTH 0x01 /* handshake to handshake */
819
820 #define SIST1_REG_800 0x43
821 #define SIST1_800_STO 0x04 /* selection/reselection timeout */
822 #define SIST1_800_GEN 0x02 /* general purpose timer */
823 #define SIST1_800_HTH 0x01 /* handshake to handshake */
824
825 #define SLPAR_REG_800 0x44 /* Parity */
826
827 #define MACNTL_REG_800 0x46 /* Memory access control */
828 #define MACNTL_800_TYP3 0x80
829 #define MACNTL_800_TYP2 0x40
830 #define MACNTL_800_TYP1 0x20
831 #define MACNTL_800_TYP0 0x10
832 #define MACNTL_800_DWR 0x08
833 #define MACNTL_800_DRD 0x04
834 #define MACNTL_800_PSCPT 0x02
835 #define MACNTL_800_SCPTS 0x01
836
837 #define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
838
839 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
840 #define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
841 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
842 #define STIME0_800_HTH_SHIFT 4
843 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
844 #define STIME0_800_SEL_SHIFT 0
845
846 #define STIME1_REG_800 0x49
847 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
848
849 #define RESPID_REG_800 0x4a /* Response ID, bit fielded */
850
851 #define STEST0_REG_800 0x4c
852 #define STEST0_800_SLT 0x08 /* Selection response logic test */
853 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
854 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
855 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
856
857 #define STEST1_REG_800 0x4d
858 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
859
860 #define STEST2_REG_800 0x4e
861 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
862 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
863 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
864 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
865 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
866 #define STEST2_800_LOW 0x01 /* SCSI low level mode */
867
868 #define STEST3_REG_800 0x4f
869 #define STEST3_800_TE 0x80 /* Enable active negation */
870 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
871 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
872 #define STEST3_800_DSI 0x10 /* Disable single initiator response */
873 #define STEST3_800_TTM 0x04 /* Time test mode */
874 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
875 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
876
877
878
879
880
881 #define OPTION_PARITY 0x1 /* Enable parity checking */
882 #define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
883 #define OPTION_700 0x8 /* Always run NCR53c700 scripts */
884 #define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
885 #define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
886 #define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
887 simple test code, return
888 DID_NO_CONNECT if any SCSI
889 commands are attempted. */
890 #define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
891 SCSI write is attempted */
892 #define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
893 each address and instruction
894 executed to debug buffer. */
895 #define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
896 instruction */
897 #define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
898 #define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
899 memory mapping */
900 #define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
901 I/O mapping */
902 #define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
903 #define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
904
905 #define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
906 #define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
907 #define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
908
909 #define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
910 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
911 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
912 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
913 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
914 #define OPTION_DEBUG_DSA 0x800000
915 #define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
916
917 #if !defined(PERM_OPTIONS)
918 #define PERM_OPTIONS 0
919 #endif
920
921 struct NCR53c7x0_synchronous {
922 unsigned long select_indirect; /* Value used for indirect selection */
923 unsigned long script[6]; /* Size ?? Script used when target is
924 reselected */
925 unsigned renegotiate:1; /* Force renegotiation on next
926 select */
927 };
928
929 #define CMD_FLAG_SDTR 1 /* Initiating synchronous
930 transfer negotiation */
931 #define CMD_FLAG_WDTR 2 /* Initiating wide transfer
932 negotiation */
933 #define CMD_FLAG_DID_SDTR 4 /* did SDTR */
934
935 struct NCR53c7x0_table_indirect {
936 unsigned long count;
937 void *address;
938 };
939
940 struct NCR53c7x0_cmd {
941 void *real; /* Real, unaligned address */
942 void (* free)(void *); /* Command to deallocate; NULL
943 for structures allocated with
944 scsi_register, etc. */
945 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
946 structure, Scsi_Cmnd points
947 at NCR53c7x0_cmd using
948 host_scribble structure */
949
950 int size; /* scsi_malloc'd size of this
951 structure */
952
953 int flags;
954
955 unsigned char select[11]; /* Select message, includes
956 IDENTIFY
957 (optional) QUEUE TAG
958 (optional) SDTR or WDTR
959 */
960
961
962 volatile struct NCR53c7x0_cmd *next, *prev;
963 /* Linux maintained lists. Note that
964 hostdata->free is a singly linked
965 list; the rest are doubly linked */
966
967
968
969 unsigned long *data_transfer_start; /* Start of data transfer routines */
970 unsigned long *data_transfer_end; /* Address after end of data transfer o
971 routines */
972
973 unsigned long residual[8]; /* Residual data transfer
974 shadow of data_transfer code.
975
976 Has instruction with modified
977 DBC field followed by jump to
978 CALL routine following command.
979 */
980
981 unsigned long dsa[0]; /* Variable length (depending
982 on host type, number of scatter /
983 gather buffers, etc). */
984 };
985
986 struct NCR53c7x0_break {
987 unsigned long *address, old_instruction[2];
988 struct NCR53c7x0_break *next;
989 unsigned char old_size; /* Size of old instruction */
990 };
991
992 /* Indicates that the NCR is not executing code */
993 #define STATE_HALTED 0
994 /*
995 * Indicates that the NCR is executing the wait for select / reselect
996 * script. Only used when running NCR53c700 compatible scripts, only
997 * state during which an ABORT is _not_ considered an error condition.
998 */
999 #define STATE_WAITING 1
1000 /* Indicates that the NCR is executing other code. */
1001 #define STATE_RUNNING 2
1002 /*
1003 * Indicates that the NCR was being aborted.
1004 */
1005 #define STATE_ABORTING 3
1006 /*
1007 * Indicates that the NCR was successfully aborted. */
1008 #define STATE_ABORTED 4
1009
1010
1011 /*
1012 * Where knowledge of SCSI SCRIPT(tm) specified values are needed
1013 * in an interrupt handler, an interrupt handler exists for each
1014 * different SCSI script so we don't have name space problems.
1015 *
1016 * Return values of these handlers are as follows :
1017 */
1018 #define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1019 #define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1020 #define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1021 #define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1022 #define SPECIFIC_INT_DONE 4 /* normal command completion */
1023 #define SPECIFIC_INT_BREAK 5 /* break point encountered */
1024
1025 struct NCR53c7x0_hostdata {
1026 int size; /* Size of entire Scsi_Host
1027 structure */
1028 struct Scsi_Host *next; /* next of this type */
1029 int board; /* set to board type, useful if
1030 we have host specific things,
1031 ie, a general purpose I/O
1032 bit is being used to enable
1033 termination, etc. */
1034
1035 int chip; /* set to chip type */
1036 /*
1037 * NCR53c700 = 700
1038 * NCR53c700-66 = 70066
1039 * NCR53c710 = 710
1040 * NCR53c720 = 720
1041 * NCR53c810 = 810
1042 */
1043
1044 /*
1045 * PCI bus, device, function, only for NCR53c8x0 chips.
1046 * pci_valid indicates that the PCI configuration information
1047 * is valid, and we can twiddle MAX_LAT, etc. as recommended
1048 * for maximum performance in the NCR documentation.
1049 */
1050 unsigned char pci_bus, pci_device_fn;
1051 unsigned pci_valid:1;
1052
1053 unsigned long *dsp; /* dsp to restart with after
1054 all stacked interrupts are
1055 handled. */
1056
1057 unsigned dsp_changed:1; /* Has dsp changed within this
1058 set of stacked interrupts ? */
1059
1060 unsigned char dstat; /* Most recent value of dstat */
1061 unsigned dstat_valid:1;
1062
1063 unsigned expecting_iid:1; /* Expect IID interrupt */
1064 unsigned expecting_sto:1; /* Expect STO interrupt */
1065
1066 /*
1067 * The code stays cleaner if we use variables with function
1068 * pointers and offsets that are unique for the different
1069 * scripts rather than having a slew of switch(hostdata->chip)
1070 * statements.
1071 *
1072 * It also means that the #defines from the SCSI SCRIPTS(tm)
1073 * don't have to be visible outside of the script-specific
1074 * instructions, preventing name space pollution.
1075 */
1076
1077 void (* init_fixup)(struct Scsi_Host *host);
1078 void (* init_save_regs)(struct Scsi_Host *host);
1079 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1080 void (* soft_reset)(struct Scsi_Host *host);
1081 int (* run_tests)(struct Scsi_Host *host);
1082
1083 /*
1084 * Called when DSTAT_SIR is set, indicating an interrupt generated
1085 * by the INT instruction, where values are unique for each SCSI
1086 * script. Should return one of the SPEC_* values.
1087 */
1088
1089 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1090
1091 long dsa_size; /* Size of DSA structure */
1092
1093 /*
1094 * Location of DSA fields for the SCSI SCRIPT corresponding to this
1095 * chip.
1096 */
1097
1098 long dsa_start;
1099 long dsa_end;
1100 long dsa_next;
1101 long dsa_prev;
1102 long dsa_cmnd;
1103 long dsa_select;
1104 long dsa_msgout;
1105 long dsa_cmdout;
1106 long dsa_dataout;
1107 long dsa_datain;
1108 long dsa_msgin;
1109 long dsa_msgout_other;
1110 long dsa_write_sync;
1111 long dsa_write_resume;
1112 long dsa_jump_resume;
1113 long dsa_check_reselect;
1114 long dsa_status;
1115
1116 /*
1117 * Important entry points that generic fixup code needs
1118 * to know about, fixed up.
1119 */
1120
1121 long E_accept_message;
1122 long E_dsa_code_template;
1123 long E_dsa_code_template_end;
1124 long E_command_complete;
1125 long E_msg_in;
1126 long E_initiator_abort;
1127 long E_other_transfer;
1128 long E_target_abort;
1129 long E_schedule;
1130 long E_debug_break;
1131 long E_reject_message;
1132 long E_respond_message;
1133 long E_select;
1134 long E_select_msgout;
1135 long E_test_0;
1136 long E_test_1;
1137 long E_test_2;
1138 long E_test_3;
1139 long E_dsa_zero;
1140 long E_dsa_jump_resume;
1141
1142 int options; /* Bitfielded set of options enabled */
1143 long test_completed; /* Test completed */
1144 int test_running; /* Test currently running */
1145 int test_source;
1146 volatile int test_dest;
1147
1148 volatile int state; /* state of driver, only used for
1149 OPTION_700 */
1150
1151 unsigned char dmode; /*
1152 * set to the address of the DMODE
1153 * register for this chip.
1154 */
1155 unsigned char istat; /*
1156 * set to the address of the ISTAT
1157 * register for this chip.
1158 */
1159
1160 int scsi_clock; /*
1161 * SCSI clock in HZ. 0 may be used
1162 * for unknown, although this will
1163 * disable synchronous negotiation.
1164 */
1165
1166 volatile int intrs; /* Number of interrupts */
1167 unsigned char saved_dmode;
1168 unsigned char saved_ctest4;
1169 unsigned char saved_ctest7;
1170 unsigned char saved_dcntl;
1171 unsigned char saved_scntl3;
1172
1173 unsigned char this_id_mask;
1174
1175 /* Debugger information */
1176 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1177 *breakpoint_current; /* Current breakpoint being stepped
1178 through, NULL if we are running
1179 normally. */
1180 #ifdef NCR_DEBUG
1181 int debug_size; /* Size of debug buffer */
1182 volatile int debug_count; /* Current data count */
1183 volatile char *debug_buf; /* Output ring buffer */
1184 volatile char *debug_write; /* Current write pointer */
1185 volatile char *debug_read; /* Current read pointer */
1186 #endif /* def NCR_DEBUG */
1187
1188 /* XXX - primitive debugging junk, remove when working ? */
1189 int debug_print_limit; /* Number of commands to print
1190 out exhaustive debugging
1191 information for if
1192 OPTION_DEBUG_DUMP is set */
1193
1194 unsigned char debug_lun_limit[8]; /* If OPTION_DEBUG_TARGET_LIMIT
1195 set, puke if commands are sent
1196 to other target/lun combinations */
1197
1198 int debug_count_limit; /* Number of commands to execute
1199 before puking to limit debugging
1200 output */
1201
1202
1203 volatile unsigned idle:1; /* set to 1 if idle */
1204
1205 /*
1206 * Table of synchronous transfer parameters set on a per-target
1207 * basis.
1208 *
1209 * XXX - do we need to increase this to 16 for the WIDE-SCSI
1210 * flavors of the board?
1211 */
1212
1213 volatile struct NCR53c7x0_synchronous sync[8];
1214
1215 volatile struct NCR53c7x0_cmd *issue_queue;
1216 /* waiting to be issued by
1217 Linux driver */
1218 volatile struct NCR53c7x0_cmd *running_list;
1219 /* commands running, maintained
1220 by Linux driver */
1221 volatile struct NCR53c7x0_cmd *current; /* currently connected
1222 nexus, ONLY valid for
1223 NCR53c700/NCR53c700-66
1224 */
1225
1226 volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
1227 allocated at probe time,
1228 which we can use for
1229 initialization */
1230 volatile struct NCR53c7x0_cmd *free;
1231 int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
1232 based on number of
1233 scatter/gather segments, etc.
1234 */
1235 volatile int num_cmds; /* Number of commands
1236 allocated */
1237 volatile unsigned char cmd_allocated[8]; /* Have we allocated commands
1238 for this target yet? If not,
1239 do so ASAP */
1240 volatile unsigned char busy[8][8]; /* number of commands
1241 executing on each target
1242 */
1243 /*
1244 * Eventually, I'll switch to a coroutine for calling
1245 * cmd->done(cmd), etc. so that we can overlap interrupt
1246 * processing with this code for maximum performance.
1247 */
1248
1249 volatile struct NCR53c7x0_cmd *finished_queue;
1250
1251
1252 /* Shared variables between SCRIPT and host driver */
1253 volatile unsigned char *issue_dsa_head;
1254 /* commands waiting to be
1255 issued, insertions are
1256 done by Linux driver,
1257 deletions are done by
1258 NCR */
1259 volatile unsigned char *issue_dsa_tail;
1260 volatile unsigned char msg_buf[16]; /* buffer for messages
1261 other than the command
1262 complete message */
1263 volatile unsigned char *reconnect_dsa_head;
1264 /* disconnected commands,
1265 maintained by NCR */
1266 /* Data identifying nexus we are trying to match during reselection */
1267 volatile unsigned char reselected_identify; /* IDENTIFY message */
1268 volatile unsigned char reselected_tag; /* second byte of queue tag
1269 message or 0 */
1270 /* These were static variables before we moved them */
1271
1272 long NCR53c7xx_zero;
1273 long NCR53c7xx_sink;
1274 char NCR53c7xx_msg_reject;
1275 char NCR53c7xx_msg_abort;
1276 char NCR53c7xx_msg_nop;
1277
1278 int script_count; /* Size of script in longs */
1279 unsigned long script[0]; /* Relocated SCSI script */
1280
1281 };
1282
1283 #define IRQ_NONE 255
1284 #define DMA_NONE 255
1285 #define IRQ_AUTO 254
1286 #define DMA_AUTO 254
1287
1288 #define BOARD_GENERIC 0
1289
1290 #define NCR53c7x0_insn_size(insn) \
1291 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1292
1293
1294 #define NCR53c7x0_local_declare() \
1295 volatile unsigned char *NCR53c7x0_address_memory; \
1296 unsigned short NCR53c7x0_address_io; \
1297 int NCR53c7x0_memory_mapped
1298
1299 #define NCR53c7x0_local_setup(host) \
1300 NCR53c7x0_address_memory = (void *) (host)->base; \
1301 NCR53c7x0_address_io = (unsigned short) (host)->io_port; \
1302 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1303 host->hostdata)-> options & OPTION_MEMORY_MAPPED
1304
1305 #define NCR53c7x0_read8(address) \
1306 (NCR53c7x0_memory_mapped ? \
1307 *( (NCR53c7x0_address_memory) + (address)) : \
1308 inb(NCR53c7x0_address_io + (address)))
1309
1310 #define NCR53c7x0_read16(address) \
1311 (NCR53c7x0_memory_mapped ? \
1312 *((unsigned short *) (NCR53c7x0_address_memory) + (address)) : \
1313 inw(NCR53c7x0_address_io + (address)))
1314
1315 #define NCR53c7x0_read32(address) \
1316 (NCR53c7x0_memory_mapped ? \
1317 *((unsigned long *) (NCR53c7x0_address_memory) + (address)) : \
1318 inl(NCR53c7x0_address_io + (address)))
1319
1320 #define NCR53c7x0_write8(address,value) \
1321 (NCR53c7x0_memory_mapped ? \
1322 *((unsigned char *) (NCR53c7x0_address_memory) + (address)) = \
1323 (value) : \
1324 outb((value), NCR53c7x0_address_io + (address)))
1325
1326 #define NCR53c7x0_write16(address,value) \
1327 (NCR53c7x0_memory_mapped ? \
1328 *((unsigned short *) (NCR53c7x0_address_memory) + (address)) = \
1329 (value) : \
1330 outw((value), NCR53c7x0_address_io + (address)))
1331
1332 #define NCR53c7x0_write32(address,value) \
1333 (NCR53c7x0_memory_mapped ? \
1334 *((unsigned long *) (NCR53c7x0_address_memory) + (address)) = \
1335 (value) : \
1336 outl((value), NCR53c7x0_address_io + (address)))
1337
1338 #define patch_abs_32(script, offset, symbol, value) \
1339 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1340 (unsigned long)); ++i) { \
1341 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1342 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1343 printk("scsi%d : %s reference %d at 0x%lx in %s is now 0x%lx\n",\
1344 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1345 (offset), #script, (script)[A_##symbol##_used[i] - \
1346 (offset)]); \
1347 }
1348
1349 #define patch_abs_rwri_data(script, offset, symbol, value) \
1350 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1351 (unsigned long)); ++i) \
1352 (script)[A_##symbol##_used[i] - (offset)] = \
1353 ((script)[A_##symbol##_used[i] - (offset)] & \
1354 ~DBC_RWRI_IMMEDIATE_MASK) | \
1355 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1356 DBC_RWRI_IMMEDIATE_MASK)
1357
1358 #define patch_dsa_32(dsa, symbol, word, value) \
1359 { \
1360 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(long) \
1361 + (word)] = (unsigned long) (value); \
1362 if (hostdata->options & OPTION_DEBUG_DSA) \
1363 printk("scsi : dsa %s symbol %s(%ld) word %d now 0x%lx\n", \
1364 #dsa, #symbol, (long) hostdata->##symbol, \
1365 (int) (word), (long) (value)); \
1366 }
1367
1368
1369
1370 #endif /* NCR53c7x0_C */
1371 #endif /* NCR53c7x0_H */
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*/