drivers/pci/pci.c

/* */
This source file includes following definitions.
pci_lookup_dev
pci_strbioserr
pci_strclass
pci_strvendor
pci_strdev
burst_bridge
sprint_dev_config
get_pci_list
pci_malloc
scan_bus
pci_init
   1 /*
   2  * drivers/pci/pci.c
   3  *
   4  * PCI services that are built on top of the BIOS32 service.
   5  *
   6  * Copyright 1993, 1994, 1995 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  */
   9 #include <linux/types.h>
  10 #include <linux/kernel.h>
  11 #include <linux/bios32.h>
  12 #include <linux/pci.h>
  13 #include <linux/string.h>
  14 
  15 #include <asm/page.h>
  16 
  17 struct pci_bus pci_root;
  18 struct pci_dev *pci_devices = 0;
  19 
  20 
  21 /* 
  22  * The bridge_id field is an offset of an item into the array
  23  * BRIDGE_MAPPING_TYPE. 0xff indicates that the device is not a PCI
  24  * bridge, or that we don't know for the moment how to configure it.
  25  * I'm trying to do my best so that the kernel stays small.  Different
  26  * chipset can have same optimization structure. i486 and pentium
  27  * chipsets from the same manufacturer usually have the same
  28  * structure.
  29  */
  30 #define DEVICE(vid,did,name) \
  31   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
  32 
  33 #define BRIDGE(vid,did,name,bridge) \
  34   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
  35 
  36 struct pci_dev_info dev_info[] = {
  37         DEVICE( NCR,            NCR_53C810,     "53c810"),
  38         DEVICE( NCR,            NCR_53C815,     "53c815"),
  39         DEVICE( NCR,            NCR_53C820,     "53c820"),
  40         DEVICE( NCR,            NCR_53C825,     "53c825"),
  41         DEVICE( ADAPTEC,        ADAPTEC_2940,   "2940"),
  42         DEVICE( ADAPTEC,        ADAPTEC_294x,   "294x"),
  43         DEVICE( DPT,            DPT,            "SmartCache/Raid"),
  44         DEVICE( S3,             S3_864_1,       "Vision 864-P"),
  45         DEVICE( S3,             S3_864_2,       "Vision 864-P"),
  46         DEVICE( S3,             S3_868, "Vision 868"),
  47         DEVICE( S3,             S3_928,         "Vision 928-P"),
  48         DEVICE( S3,             S3_964_1,       "Vision 964-P"),
  49         DEVICE( S3,             S3_964_2,       "Vision 964-P"),
  50         DEVICE( S3,             S3_811,         "Trio32/Trio64"),
  51         DEVICE( S3,             S3_968,         "Vision 968"),
  52         DEVICE( OPTI,           OPTI_82C822,    "82C822"),
  53         DEVICE( OPTI,           OPTI_82C621,    "82C621"),
  54         DEVICE( OPTI,           OPTI_82C557,    "82C557"),
  55         DEVICE( OPTI,           OPTI_82C558,    "82C558"),
  56         BRIDGE( UMC,            UMC_UM8881F,    "UM8881F",              0x02),
  57         BRIDGE( UMC,            UMC_UM8891A,    "UM8891A",              0x01),
  58         DEVICE( UMC,            UMC_UM8886F,    "UM8886F"),
  59         DEVICE( UMC,            UMC_UM8673F,    "UM8673F"),
  60         DEVICE( DEC,            DEC_TULIP,      "DC21040"),
  61         DEVICE( DEC,            DEC_TULIP_FAST, "DC21040"),
  62         DEVICE( DEC,            DEC_FDDI,       "DEFPA"),
  63         DEVICE( DEC,            DEC_BRD,        "DC21050"),
  64         DEVICE( MATROX,         MATROX_MGA_2,   "Atlas PX2085"),
  65         DEVICE( MATROX,         MATROX_MGA_IMP, "MGA Impression"),
  66         DEVICE( INTEL,          INTEL_82378,    "82378IB"),
  67         BRIDGE( INTEL,          INTEL_82424,    "82424ZX Saturn",       0x00),
  68         DEVICE( INTEL,          INTEL_82375,    "82375EB"),
  69         BRIDGE( INTEL,          INTEL_82434,    "82434LX Mercury/Neptune", 0x00),
  70         DEVICE( INTEL,          INTEL_82430,    "82430ZX Aries"),
  71         DEVICE( SMC,            SMC_37C665,     "FDC 37C665"),
  72         DEVICE( ATI,            ATI_M32,        "Mach 32"),
  73         DEVICE( ATI,            ATI_M64,        "Mach 64"),
  74         DEVICE( WEITEK,         WEITEK_P9000,   "P9000"),
  75         DEVICE( WEITEK,         WEITEK_P9100,   "P9100"),
  76         DEVICE( CIRRUS,         CIRRUS_5430,    "GD 5430"),
  77         DEVICE( CIRRUS,         CIRRUS_5434_4,  "GD 5434"),
  78         DEVICE( CIRRUS,         CIRRUS_5434_8,  "GD 5434"),
  79         DEVICE( CIRRUS,         CIRRUS_6729,    "CL 6729"),
  80         DEVICE( BUSLOGIC,       BUSLOGIC_946C,  "946C"),
  81         DEVICE( BUSLOGIC,       BUSLOGIC_946C_2,"946C"),
  82         DEVICE( N9,             N9_I128,        "Imagine 128"),
  83         DEVICE( AI,             AI_M1435,       "M1435"),
  84         DEVICE( AL,             AL_M1445,       "M1445"),
  85         DEVICE( AL,             AL_M1449,       "M1449"),
  86         DEVICE( AL,             AL_M1451,       "M1451"),
  87         DEVICE( TSENG,          TSENG_W32P_2,   "ET4000W32P"),
  88         DEVICE( TSENG,          TSENG_W32P_b,   "ET4000W32P rev B"),
  89         DEVICE( TSENG,          TSENG_W32P_c,   "ET4000W32P rev C"),
  90         DEVICE( TSENG,          TSENG_W32P_d,   "ET4000W32P rev D"),
  91         DEVICE( CMD,            CMD_640,        "640A"),
  92         DEVICE( VISION,         VISION_QD8500,  "QD-8500"),
  93         DEVICE( VISION,         VISION_QD8580,  "QD-8580"),
  94         DEVICE( AMD,            AMD_LANCE,      "79C970"),
  95         DEVICE( AMD,            AMD_SCSI,       "53C974"),
  96         DEVICE( VLSI,           VLSI_82C593,    "82C593-FC1"),
  97         DEVICE( VLSI,           VLSI_82C592,    "82C592-FC1"),
  98         DEVICE( ADL,            ADL_2301,       "2301"),
  99         DEVICE( SYMPHONY,       SYMPHONY_101,   "82C101"),
 100         DEVICE( TRIDENT,        TRIDENT_9420,   "TG 9420"),
 101         DEVICE( TRIDENT,        TRIDENT_9440,   "TG 9440"),
 102         DEVICE( CONTAQ,         CONTAQ_82C599,  "82C599"),
 103         DEVICE( NS,             NS_87410,       "87410"),
 104         DEVICE( VIA,            VIA_82C505,     "VT 82C505"),
 105         DEVICE( VIA,            VIA_82C576,     "VT 82C576 3V"),
 106         DEVICE( VIA,            VIA_82C561,     "VT 82C561"),
 107         DEVICE( SI,             SI_496,         "85C496"),
 108         DEVICE( SI,             SI_501,         "85C501"),
 109         DEVICE( SI,             SI_503,         "85C503"),
 110         DEVICE( SI,             SI_601,         "85C601"),
 111         DEVICE( LEADTEK,        LEADTEK_805,    "S3 805"),
 112         DEVICE( IMS,            IMS_8849,       "8849"),
 113         DEVICE( ZEINET,         ZEINET_1221,    "1221"),
 114         DEVICE( EF,             EF_ATM,         "155P-MF1"),
 115         DEVICE( HER,            HER_STING,      "Stingray"),
 116         DEVICE( HER,            HER_STING,      "Stingray"),
 117         DEVICE( ATRONICS,       ATRONICS_2015,  "IDE-2015PL"),
 118         DEVICE( CT,             CT_65545,       "65545"),
 119         DEVICE( FD,             FD_36C70,       "TMC-18C30"),
 120         DEVICE( WINBOND,        WINBOND_83769,  "W83769F"),
 121         DEVICE( 3COM,           3COM_3C590,     "3C590 10bT"),
 122         DEVICE( 3COM,           3COM_3C595TX,   "3C595 100bTX"),
 123         DEVICE( 3COM,           3COM_3C595T4,   "3C595 100bT4"),
 124         DEVICE( 3COM,           3COM_3C595MII,  "3C595 100b-MII"),
 125         DEVICE( PROMISE,        PROMISE_5300,   "DC5030"),
 126         DEVICE( QLOGIC,         QLOGIC_ISP1020, "ISP1020"),
 127         DEVICE( QLOGIC,         QLOGIC_ISP1022, "ISP1022"),
 128         DEVICE( X,              X_AGX016,       "ITT AGX016")
 129 };
 130 
 131 
 132 #ifdef CONFIG_PCI_OPTIMIZE
 133 
 134 /*
 135  * An item of this structure has the following meaning:
 136  * for each optimization, the register address, the mask
 137  * and value to write to turn it on.
 138  * There are 5 optimizations for the moment:
 139  * Cache L2 write back best than write through
 140  * Posted Write for CPU to PCI enable
 141  * Posted Write for CPU to MEMORY enable
 142  * Posted Write for PCI to MEMORY enable
 143  * PCI Burst enable
 144  *
 145  * Half of the bios I've meet don't allow you to turn that on, and you
 146  * can gain more than 15% on graphic accesses using those
 147  * optimizations...
 148  */
 149 struct optimization_type {
 150         char    *type;
 151         char    *off;
 152         char    *on;
 153 } bridge_optimization[] = {
 154         {"Cache L2",                    "write trough", "write back"},
 155         {"CPU-PCI posted write",        "off",          "on"},
 156         {"CPU-Memory posted write",     "off",          "on"},
 157         {"PCI-Memory posted write",     "off",          "on"},
 158         {"PCI burst",                   "off",          "on"}
 159 };
 160 
 161 #define NUM_OPTIMIZATIONS \
 162         (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
 163 
 164 struct bridge_mapping_type {
 165         unsigned char   addr;   /* config space address */
 166         unsigned char   mask;
 167         unsigned char   value;
 168 } bridge_mapping[] = {
 169         /*
 170          * Intel Neptune/Mercury/Saturn:
 171          *      If the internal cache is write back,
 172          *      the L2 cache must be write through!
 173          *      I've to check out how to control that
 174          *      for the moment, we won't touch the cache
 175          */
 176         {0x0    ,0x02   ,0x02   },
 177         {0x53   ,0x02   ,0x02   },
 178         {0x53   ,0x01   ,0x01   },
 179         {0x54   ,0x01   ,0x01   },
 180         {0x54   ,0x02   ,0x02   },
 181 
 182         /*
 183          * UMC 8891A Pentium chipset:
 184          *      Why did you think UMC was cheaper ??
 185          */
 186         {0x50   ,0x10   ,0x00   },
 187         {0x51   ,0x40   ,0x40   },
 188         {0x0    ,0x0    ,0x0    },
 189         {0x0    ,0x0    ,0x0    },
 190         {0x0    ,0x0    ,0x0    },
 191 
 192         /*
 193          * UMC UM8881F
 194          *      This is a dummy entry for my tests.
 195          *      I have this chipset and no docs....
 196          */
 197         {0x0    ,0x1    ,0x1    },
 198         {0x0    ,0x2    ,0x0    },
 199         {0x0    ,0x0    ,0x0    },
 200         {0x0    ,0x0    ,0x0    },
 201         {0x0    ,0x0    ,0x0    }
 202 };
 203 
 204 #endif /* CONFIG_PCI_OPTIMIZE */
 205 
 206 
 207 /*
 208  * If performance ever becomes important, device_info[] could be
 209  * sorted by key and this could be replaced by a binary search.
 210  */
 211 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
     /*  */
 212 {
 213         int i;
 214 
 215         for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
 216                 if (dev_info[i].vendor == vendor &&
 217                     dev_info[i].device == dev)
 218                 {
 219                         return &dev_info[i];
 220                 }
 221         }
 222         return 0;
 223 }
 224 
 225 
 226 char *pci_strbioserr (int error)
     /*  */
 227 {
 228         switch (error) {
 229               case PCIBIOS_SUCCESSFUL:          return "SUCCESSFUL";
 230               case PCIBIOS_FUNC_NOT_SUPPORTED:  return "FUNC_NOT_SUPPORTED";
 231               case PCIBIOS_BAD_VENDOR_ID:       return "SUCCESSFUL";
 232               case PCIBIOS_DEVICE_NOT_FOUND:    return "DEVICE_NOT_FOUND";
 233               case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
 234               case PCIBIOS_SET_FAILED:          return "SET_FAILED";
 235               case PCIBIOS_BUFFER_TOO_SMALL:    return "BUFFER_TOO_SMALL";
 236               default:                          return "Unknown error status";
 237         }
 238 }
 239 
 240 
 241 const char *pci_strclass (unsigned int class)
     /*  */
 242 {
 243         switch (class >> 8) {
 244               case PCI_CLASS_NOT_DEFINED:               return "Non-VGA device";
 245               case PCI_CLASS_NOT_DEFINED_VGA:           return "VGA compatible device";
 246 
 247               case PCI_CLASS_STORAGE_SCSI:              return "SCSI storage controller";
 248               case PCI_CLASS_STORAGE_IDE:               return "IDE controller";
 249               case PCI_CLASS_STORAGE_FLOPPY:            return "Floppy disk controller";
 250               case PCI_CLASS_STORAGE_IPI:               return "IPI bus controller";
 251               case PCI_CLASS_STORAGE_OTHER:             return "Unknown mass storage controller";
 252 
 253               case PCI_CLASS_NETWORK_ETHERNET:          return "Ethernet controller";
 254               case PCI_CLASS_NETWORK_TOKEN_RING:        return "Token ring network controller";
 255               case PCI_CLASS_NETWORK_FDDI:              return "FDDI network controller";
 256               case PCI_CLASS_NETWORK_OTHER:             return "Network controller";
 257 
 258               case PCI_CLASS_DISPLAY_VGA:               return "VGA compatible controller";
 259               case PCI_CLASS_DISPLAY_XGA:               return "XGA compatible controller";
 260               case PCI_CLASS_DISPLAY_OTHER:             return "Display controller";
 261 
 262               case PCI_CLASS_MULTIMEDIA_VIDEO:          return "Multimedia video controller";
 263               case PCI_CLASS_MULTIMEDIA_AUDIO:          return "Multimedia audio controller";
 264               case PCI_CLASS_MULTIMEDIA_OTHER:          return "Multimedia controller";
 265 
 266               case PCI_CLASS_MEMORY_RAM:                return "RAM memory";
 267               case PCI_CLASS_MEMORY_FLASH:              return "FLASH memory";
 268               case PCI_CLASS_MEMORY_OTHER:              return "Memory";
 269 
 270               case PCI_CLASS_BRIDGE_HOST:               return "Host bridge";
 271               case PCI_CLASS_BRIDGE_ISA:                return "ISA bridge";
 272               case PCI_CLASS_BRIDGE_EISA:               return "EISA bridge";
 273               case PCI_CLASS_BRIDGE_MC:                 return "MicroChannel bridge";
 274               case PCI_CLASS_BRIDGE_PCI:                return "PCI bridge";
 275               case PCI_CLASS_BRIDGE_PCMCIA:             return "PCMCIA bridge";
 276               case PCI_CLASS_BRIDGE_OTHER:              return "Bridge";
 277 
 278               default:                                  return "Unknown class";
 279         }
 280 }
 281 
 282 
 283 const char *pci_strvendor(unsigned int vendor)
     /*  */
 284 {
 285         switch (vendor) {
 286               case PCI_VENDOR_ID_NCR:           return "NCR";
 287               case PCI_VENDOR_ID_ADAPTEC:       return "Adaptec";
 288               case PCI_VENDOR_ID_DPT:           return "DPT";
 289               case PCI_VENDOR_ID_S3:            return "S3 Inc.";
 290               case PCI_VENDOR_ID_OPTI:          return "OPTI";
 291               case PCI_VENDOR_ID_UMC:           return "UMC";
 292               case PCI_VENDOR_ID_DEC:           return "DEC";
 293               case PCI_VENDOR_ID_MATROX:        return "Matrox";
 294               case PCI_VENDOR_ID_INTEL:         return "Intel";
 295               case PCI_VENDOR_ID_SMC:           return "SMC";
 296               case PCI_VENDOR_ID_ATI:           return "ATI";
 297               case PCI_VENDOR_ID_WEITEK:        return "Weitek";
 298               case PCI_VENDOR_ID_CIRRUS:        return "Cirrus Logic";
 299               case PCI_VENDOR_ID_BUSLOGIC:      return "Bus Logic";
 300               case PCI_VENDOR_ID_N9:            return "Number Nine";
 301               case PCI_VENDOR_ID_AI:            return "Acer Incorporated";
 302               case PCI_VENDOR_ID_AL:            return "Acer Labs";
 303               case PCI_VENDOR_ID_TSENG:         return "Tseng'Lab";
 304               case PCI_VENDOR_ID_CMD:           return "CMD";
 305               case PCI_VENDOR_ID_VISION:        return "Vision";
 306               case PCI_VENDOR_ID_AMD:           return "AMD";
 307               case PCI_VENDOR_ID_VLSI:          return "VLSI";
 308               case PCI_VENDOR_ID_ADL:           return "Advance Logic";
 309               case PCI_VENDOR_ID_SYMPHONY:      return "Symphony";
 310               case PCI_VENDOR_ID_TRIDENT:       return "Trident";
 311               case PCI_VENDOR_ID_CONTAQ:        return "Contaq";
 312               case PCI_VENDOR_ID_NS:            return "NS";
 313               case PCI_VENDOR_ID_VIA:           return "VIA Technologies";
 314               case PCI_VENDOR_ID_SI:            return "Silicon Integrated Systems";
 315               case PCI_VENDOR_ID_LEADTEK:       return "Leadtek Research";
 316               case PCI_VENDOR_ID_IMS:           return "IMS";
 317               case PCI_VENDOR_ID_ZEINET:        return "ZeiNet";
 318               case PCI_VENDOR_ID_EF:            return "Efficient Networks";
 319               case PCI_VENDOR_ID_HER:           return "Hercules";
 320               case PCI_VENDOR_ID_ATRONICS:      return "Atronics";
 321               case PCI_VENDOR_ID_CT:            return "Chips & Technologies";
 322               case PCI_VENDOR_ID_FD:            return "Future Domain";
 323               case PCI_VENDOR_ID_WINBOND:       return "Winbond";
 324               case PCI_VENDOR_ID_3COM:          return "3Com";
 325               case PCI_VENDOR_ID_PROMISE:       return "Promise Technology";
 326               case PCI_VENDOR_ID_QLOGIC:        return "Q Logic";
 327               default:                          return "Unknown vendor";
 328         }
 329 }
 330 
 331 
 332 const char *pci_strdev(unsigned int vendor, unsigned int device) 
     /*  */
 333 {
 334         struct pci_dev_info *info;
 335 
 336         info =  pci_lookup_dev(vendor, device);
 337         return info ? info->name : "Unknown device";
 338 }
 339 
 340 
 341 
 342 /*
 343  * Turn on/off PCI bridge optimization. This should allow benchmarking.
 344  */
 345 static void burst_bridge(unsigned char bus, unsigned char devfn,
     /*  */
 346                          unsigned char pos, int turn_on)
 347 {
 348 #ifdef CONFIG_PCI_OPTIMIZE
 349         struct bridge_mapping_type *bmap;
 350         unsigned char val;
 351         int i;
 352 
 353         pos *= NUM_OPTIMIZATIONS;
 354         printk("PCI bridge optimization.\n");
 355         for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
 356                 printk("    %s: ", bridge_optimization[i].type);
 357                 bmap = &bridge_mapping[pos + i];
 358                 if (!bmap->addr) {
 359                         printk("Not supported.");
 360                 } else {
 361                         pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
 362                         if ((val & bmap->mask) == bmap->value) {
 363                                 printk("%s.", bridge_optimization[i].on);
 364                                 if (!turn_on) {
 365                                         pcibios_write_config_byte(bus, devfn,
 366                                                                   bmap->addr,
 367                                                                   (val | bmap->mask)
 368                                                                   - bmap->value);
 369                                         printk("Changed!  Now %s.", bridge_optimization[i].off);
 370                                 }
 371                         } else {
 372                                 printk("%s.", bridge_optimization[i].off);
 373                                 if (turn_on) {
 374                                         pcibios_write_config_byte(bus, devfn,
 375                                                                   bmap->addr,
 376                                                                   (val & (0xff - bmap->mask))
 377                                                                   + bmap->value);
 378                                         printk("Changed!  Now %s.", bridge_optimization[i].on);
 379                                 }
 380                         }
 381                 }
 382                 printk("\n");
 383         }
 384 #endif /* CONFIG_PCI_OPTIMIZE */
 385 }
 386 
 387 
 388 /*
 389  * Convert some of the configuration space registers of the device at
 390  * address (bus,devfn) into a string (possibly several lines each).
 391  * The configuration string is stored starting at buf[len].  If the
 392  * string would exceed the size of the buffer (SIZE), 0 is returned.
 393  */
 394 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
     /*  */
 395 {
 396         unsigned long base;
 397         unsigned int l, class_rev, bus, devfn;
 398         unsigned short vendor, device, status;
 399         unsigned char bist, latency, min_gnt, max_lat;
 400         int reg, len = 0;
 401         const char *str;
 402 
 403         bus   = dev->bus->number;
 404         devfn = dev->devfn;
 405 
 406         pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
 407         pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
 408         pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
 409         pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
 410         pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
 411         pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
 412         pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
 413         pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
 414         if (len + 80 > size) {
 415                 return -1;
 416         }
 417         len += sprintf(buf + len, "  Bus %2d, device %3d, function %2d:\n",
 418                        bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
 419 
 420         if (len + 80 > size) {
 421                 return -1;
 422         }
 423         len += sprintf(buf + len, "    %s: %s %s (rev %d).\n      ",
 424                        pci_strclass(class_rev >> 8), pci_strvendor(vendor),
 425                        pci_strdev(vendor, device), class_rev & 0xff);
 426 
 427         if (!pci_lookup_dev(vendor, device)) {
 428                 len += sprintf(buf + len,
 429                                "Vendor id=%x. Device id=%x.\n      ",
 430                                vendor, device);
 431         }
 432 
 433         str = 0;        /* to keep gcc shut... */
 434         switch (status & PCI_STATUS_DEVSEL_MASK) {
 435               case PCI_STATUS_DEVSEL_FAST:   str = "Fast devsel.  "; break;
 436               case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel.  "; break;
 437               case PCI_STATUS_DEVSEL_SLOW:   str = "Slow devsel.  "; break;
 438         }
 439         if (len + strlen(str) > size) {
 440                 return -1;
 441         }
 442         len += sprintf(buf + len, str);
 443 
 444         if (status & PCI_STATUS_FAST_BACK) {
 445 #               define fast_b2b_capable "Fast back-to-back capable.  "
 446                 if (len + strlen(fast_b2b_capable) > size) {
 447                         return -1;
 448                 }
 449                 len += sprintf(buf + len, fast_b2b_capable);
 450 #               undef fast_b2b_capable
 451         }
 452 
 453         if (bist & PCI_BIST_CAPABLE) {
 454 #               define BIST_capable     "BIST capable.  "
 455                 if (len + strlen(BIST_capable) > size) {
 456                         return -1;
 457                 }
 458                 len += sprintf(buf + len, BIST_capable);
 459 #               undef BIST_capable
 460         }
 461 
 462         if (dev->irq) {
 463                 if (len + 40 > size) {
 464                         return -1;
 465                 }
 466                 len += sprintf(buf + len, "IRQ %d.  ", dev->irq);
 467         }
 468 
 469         if (dev->master) {
 470                 if (len + 80 > size) {
 471                         return -1;
 472                 }
 473                 len += sprintf(buf + len, "Master Capable.  ");
 474                 if (latency)
 475                   len += sprintf(buf + len, "Latency=%d.  ", latency); 
 476                 else
 477                   len += sprintf(buf + len, "No bursts.  ");
 478                 if (min_gnt)
 479                   len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
 480                 if (max_lat)
 481                   len += sprintf(buf + len, "Max Lat=%d.", max_lat);
 482         }
 483 
 484         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 485                 if (len + 40 > size) {
 486                         return -1;
 487                 }
 488                 pcibios_read_config_dword(bus, devfn, reg, &l);
 489                 base = l;
 490                 if (!base) {
 491                         continue;
 492                 }
 493 
 494                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 495                         len += sprintf(buf + len,
 496                                        "\n      I/O at 0x%lx.",
 497                                        base & PCI_BASE_ADDRESS_IO_MASK);
 498                 } else {
 499                         const char *pref, *type = "unknown";
 500 
 501                         if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 502                                 pref = "P";
 503                         } else {
 504                                 pref = "Non-p";
 505                         }
 506                         switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
 507                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 508                                 type = "32 bit"; break;
 509                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 510                                 type = "20 bit"; break;
 511                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 512                                 type = "64 bit";
 513                                 /* read top 32 bit address of base addr: */
 514                                 reg += 4;
 515                                 pcibios_read_config_dword(bus, devfn, reg, &l);
 516                                 base |= ((u64) l) << 32;
 517                                 break;
 518                         }
 519                         len += sprintf(buf + len,
 520                                        "\n      %srefetchable %s memory at "
 521                                        "0x%lx.", pref, type,
 522                                        base & PCI_BASE_ADDRESS_MEM_MASK);
 523                 }
 524         }
 525 
 526         len += sprintf(buf + len, "\n");
 527         return len;
 528 }
 529 
 530 
 531 /*
 532  * Return list of PCI devices as a character string for /proc/pci.
 533  * BUF is a buffer that is PAGE_SIZE bytes long.
 534  */
 535 int get_pci_list(char *buf)
     /*  */
 536 {
 537         int nprinted, len, size;
 538         struct pci_dev *dev;
 539 #       define MSG "\nwarning: page-size limit reached!\n"
 540 
 541         /* reserve same for truncation warning message: */
 542         size  = PAGE_SIZE - (strlen(MSG) + 1);
 543         len   = sprintf(buf, "PCI devices found:\n");
 544 
 545         for (dev = pci_devices; dev; dev = dev->next) {
 546                 nprinted = sprint_dev_config(dev, buf + len, size - len);
 547                 if (nprinted < 0) {
 548                         return len + sprintf(buf + len, MSG);
 549                 }
 550                 len += nprinted;
 551         }
 552         return len;
 553 }
 554 
 555 
 556 /*
 557  * pci_malloc() returns initialized memory of size SIZE.  Can be
 558  * used only while pci_init() is active.
 559  */
 560 static void *pci_malloc(long size, unsigned long *mem_startp)
     /*  */
 561 {
 562         void *mem;
 563 
 564 #ifdef DEBUG
 565         printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
 566 #endif
 567         mem = (void*) *mem_startp;
 568         *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
 569         memset(mem, 0, size);
 570         return mem;
 571 }
 572 
 573 
 574 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
     /*  */
 575 {
 576         unsigned int devfn, l, max;
 577         unsigned char cmd, tmp, hdr_type = 0;
 578         struct pci_dev_info *info;
 579         struct pci_dev *dev;
 580         struct pci_bus *child;
 581 
 582 #ifdef DEBUG
 583         printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
 584 #endif
 585 
 586         max = bus->secondary;
 587         for (devfn = 0; devfn < 0xff; ++devfn) {
 588                 if (PCI_FUNC(devfn) == 0) {
 589                         pcibios_read_config_byte(bus->number, devfn,
 590                                                  PCI_HEADER_TYPE, &hdr_type);
 591                 } else if (!(hdr_type & 0x80)) {
 592                         /* not a multi-function device */
 593                         continue;
 594                 }
 595 
 596                 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
 597                                           &l);
 598                 /* some broken boards return 0 if a slot is empty: */
 599                 if (l == 0xffffffff || l == 0x00000000) {
 600                         hdr_type = 0;
 601                         continue;
 602                 }
 603 
 604                 dev = pci_malloc(sizeof(*dev), mem_startp);
 605                 dev->bus = bus;
 606                 /*
 607                  * Put it into the simple chain of devices on this
 608                  * bus.  It is used to find devices once everything is
 609                  * set up.
 610                  */
 611                 dev->next = pci_devices;
 612                 pci_devices = dev;
 613 
 614                 dev->devfn  = devfn;
 615                 dev->vendor = l & 0xffff;
 616                 dev->device = (l >> 16) & 0xffff;
 617 
 618                 /*
 619                  * Check to see if we now about this device and report
 620                  * a message at boot time.  This is the only way to
 621                  * learn about new hardware...
 622                  */
 623                 info = pci_lookup_dev(dev->vendor, dev->device);
 624                 if (!info) {
 625                         printk("Warning : Unknown PCI device.  Please read include/linux/pci.h \n");
 626                 } else {
 627                         /* Some BIOS' are lazy. Let's do their job: */
 628                         if (info->bridge_type != 0xff) {
 629                                 burst_bridge(bus->number, devfn,
 630                                              info->bridge_type, 1);
 631                         }
 632                 }
 633 
 634                 /* non-destructively determine if device can be a master: */
 635                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 636                                          &cmd);
 637                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 638                                           cmd | PCI_COMMAND_MASTER);
 639                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 640                                          &tmp);
 641                 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
 642                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 643                                           cmd);
 644 
 645                 /* read irq level (may be changed during pcibios_fixup()): */
 646                 pcibios_read_config_byte(bus->number, devfn,
 647                                          PCI_INTERRUPT_LINE, &dev->irq);
 648 
 649                 /* check to see if this device is a PCI-PCI bridge: */
 650                 pcibios_read_config_dword(bus->number, devfn,
 651                                           PCI_CLASS_REVISION, &l);
 652                 l = l >> 8;                     /* upper 3 bytes */
 653                 dev->class = l;
 654                 /*
 655                  * Now insert it into the list of devices held
 656                  * by the parent bus.
 657                  */
 658                 dev->sibling = bus->devices;
 659                 bus->devices = dev;
 660 
 661                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
 662                         unsigned int buses;
 663 
 664                         /*
 665                          * Insert it into the tree of buses.
 666                          */
 667                         child = pci_malloc(sizeof(*child), mem_startp);
 668                         child->next   = bus->children;
 669                         bus->children = child;
 670                         child->self = dev;
 671                         child->parent = bus;
 672 
 673                         /*
 674                          * Set up the primary, secondary and subordinate
 675                          * bus numbers.
 676                          */
 677                         child->number = child->secondary = ++max;
 678                         child->primary = bus->secondary;
 679                         child->subordinate = 0xff;
 680                         /*
 681                          * Clear all status bits and turn off memory,
 682                          * I/O and master enables.
 683                          */
 684                         pcibios_write_config_word(bus->number, devfn,
 685                                                   PCI_COMMAND, 0x0000);
 686                         pcibios_write_config_word(bus->number, devfn,
 687                                                   PCI_STATUS, 0xffff);
 688                         /*
 689                          * Configure the bus numbers for this bridge:
 690                          */
 691                         pcibios_read_config_dword(bus->number, devfn, 0x18,
 692                                                   &buses);
 693                         buses &= 0xff000000;
 694                         buses |= (((unsigned int)(child->primary)     <<  0) |
 695                                   ((unsigned int)(child->secondary)   <<  8) |
 696                                   ((unsigned int)(child->subordinate) << 16));
 697                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 698                                                    buses);
 699                         /*
 700                          * Now we can scan all subordinate buses:
 701                          */
 702                         max = scan_bus(child, mem_startp);
 703                         /*
 704                          * Set the subordinate bus number to its real
 705                          * value:
 706                          */
 707                         child->subordinate = max;
 708                         buses = (buses & 0xff00ffff)
 709                           | ((unsigned int)(child->subordinate) << 16);
 710                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 711                                                    buses);
 712                 }
 713         }
 714         /*
 715          * We've scanned the bus and so we know all about what's on
 716          * the other side of any bridges that may be on this bus plus
 717          * any devices.
 718          *
 719          * Return how far we've got finding sub-buses.
 720          */
 721         return max;
 722 }
 723 
 724 
 725 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
     /*  */
 726 {
 727         mem_start = pcibios_init(mem_start, mem_end);
 728 
 729         if (!pcibios_present()) {
 730                 printk("pci_init: no BIOS32 detected\n");
 731                 return mem_start;
 732         }
 733 
 734         printk("Probing PCI hardware.\n");
 735 
 736         memset(&pci_root, 0, sizeof(pci_root));
 737         pci_root.subordinate = scan_bus(&pci_root, &mem_start);
 738 
 739         /* give BIOS a chance to apply platform specific fixes: */
 740         mem_start = pcibios_fixup(mem_start, mem_end);
 741 
 742 #ifdef DEBUG
 743         {
 744                 int len = get_pci_list(mem_start);
 745                 if (len) {
 746                         ((char*)mem_start)[len] = '\0';
 747                         printk("%s\n", mem_start);
 748                 }
 749         }
 750 #endif
 751         return mem_start;
 752 }
/* */
root/drivers/pci/pci.c

DEFINITIONS
