1 /* ultra.h: Definitions and defines for the TI V9 UltraSparc. 2 * 3 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 4 */ 5 6 #ifndef _SPARC_ULTRA_H 7 #define _SPARC_ULTRA_H 8 9 /* Spitfire MMU control register: 10 * 11 * ---------------------------------------------------------- 12 * | | IMPL | VERS | | MID | | 13 * ---------------------------------------------------------- 14 * 64 31-28 27-24 23-22 21-17 16 0 15 * 16 * IMPL: Implementation of this Spitfire. 17 * VERS: Version of this Spitfire. 18 * MID: Module ID of this processor. 19 */ 20 21 #define SPITFIRE_MIDMASK 0x00000000003e0000 22 23 /* Spitfire Load Store Unit control register: 24 * 25 * --------------------------------------------------------------------- 26 * | RSV | PWR | PWW | VWR | VWW | RSV | PMASK | DME | IME | DCE | ICE | 27 * --------------------------------------------------------------------- 28 * 63-25 24 23 22 21 20 19-4 3 2 1 0 29 * 30 * PWR: Physical Watchpoint Read enable: 0=off 1=on 31 * PWW: Physical Watchpoint Write enable: 0=off 1=on 32 * VWR: Virtual Watchpoint Read enable: 0=off 1=on 33 * VWW: Virtual Watchpoint Write enable: 0=off 1=on 34 * PMASK: Parity MASK ??? 35 * DME: Data MMU Enable: 0=off 1=on 36 * IME: Instruction MMU Enable: 0=off 1=on 37 * DCE: Data Cache Enable: 0=off 1=on 38 * ICE: Instruction Cache Enable: 0=off 1=on 39 */ 40 41 #define SPITFIRE_LSU_PWR 0x01000000 42 #define SPITFIRE_LSU_PWW 0x00800000 43 #define SPITFIRE_LSU_VWR 0x00400000 44 #define SPITFIRE_LSU_VWW 0x00200000 45 #define SPITFIRE_LSU_PMASK 0x000ffff0 46 #define SPITFIRE_LSU_DME 0x00000008 47 #define SPITFIRE_LSU_IME 0x00000004 48 #define SPITFIRE_LSU_DCE 0x00000002 49 #define SPITFIRE_LSU_ICE 0x00000001 50 51 #endif /* !(_SPARC_ULTRA_H) */