include/asm-sparc/mxcc.h

/* */
   1 /* mxcc.h:  Definitions of the Viking MXCC registers
   2  *
   3  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5 
   6 #ifndef _SPARC_MXCC_H
   7 #define _SPARC_MXCC_H
   8 
   9 /* These registers are accessed through ASI 0x2. */
  10 #define MXCC_DATSTREAM       0x1C00000  /* Data stream register */
  11 #define MXCC_SRCSTREAM       0x1C00100  /* Source stream register */
  12 #define MXCC_DESSTREAM       0x1C00200  /* Destination stream register */
  13 #define MXCC_RMCOUNT         0x1C00300  /* Count of references and misses */
  14 #define MXCC_STEST           0x1C00804  /* Internal self-test */
  15 #define MXCC_CREG            0x1C00A04  /* Control register */
  16 #define MXCC_SREG            0x1C00B00  /* Status register */
  17 #define MXCC_RREG            0x1C00C04  /* Reset register */
  18 #define MXCC_EREG            0x1C00E00  /* Error code register */
  19 #define MXCC_PREG            0x1C00F04  /* Address port register */
  20 
  21 /* The MXCC Control Register:
  22  *
  23  * ----------------------------------------------------------------------
  24  * |                                   | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
  25  * ----------------------------------------------------------------------
  26  *  31                              10    9    8-6   5   4    3   2  1-0
  27  *
  28  * RRC: Controls what you read from MXCC_RMCOUNT reg.
  29  *      0=Misses 1=References
  30  * PRE: Prefetch enable
  31  * MCE: Multiple Command Enable
  32  * PARE: Parity enable
  33  * ECE: External cache enable
  34  */
  35 
  36 #define MXCC_CTL_RRC   0x00000200
  37 #define MXCC_CTL_PRE   0x00000020
  38 #define MXCC_CTL_MCE   0x00000010
  39 #define MXCC_CTL_PARE  0x00000008
  40 #define MXCC_CTL_ECE   0x00000004
  41 
  42 /* The MXCC Error Register:
  43  *
  44  * --------------------------------------------------------
  45  * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
  46  * --------------------------------------------------------
  47  *  31   30 29  28  27  26  25 24-15  14-7   6  5-3   2-0
  48  *
  49  * ME: Multiple Errors have occurred
  50  * CE: Cache consistancy Error
  51  * PEW: Parity Error during a Write operation
  52  * PEE: Parity Error involving the External cache
  53  * ASE: ASynchronous Error
  54  * EIV: This register is toast
  55  * MOPC: MXCC Operation Code for instance causing error
  56  * ECODE: The Error CODE
  57  * PRIV: A privileged mode error? 0=no 1=yes
  58  * HPADDR: High PhysicalADDRess bits (35-32)
  59  */
  60 
  61 #define MXCC_ERR_ME     0x80000000
  62 #define MXCC_ERR_CE     0x20000000
  63 #define MXCC_ERR_PEW    0x10000000
  64 #define MXCC_ERR_PEE    0x08000000
  65 #define MXCC_ERR_ASE    0x04000000
  66 #define MXCC_ERR_EIV    0x02000000
  67 #define MXCC_ERR_MOPC   0x01FF8000
  68 #define MXCC_ERR_ECODE  0x00007F80
  69 #define MXCC_ERR_PRIV   0x00000040
  70 #define MXCC_ERR_HPADDR 0x0000000f
  71 
  72 /* The MXCC Port register:
  73  *
  74  * -----------------------------------------------------
  75  * |                | MID |                            |
  76  * -----------------------------------------------------
  77  *  31            21 20-18 17                         0
  78  *
  79  * MID: The moduleID of the cpu your read this from.
  80  */
  81 
  82 #endif /* !(_SPARC_MXCC_H) */
/* */
root/include/asm-sparc/mxcc.h
