drivers/scsi/aic7xxx.c

/* */
This source file includes following definitions.
debug
debug_config
aic7xxx_setup
aic7xxx_loadseq
aic7xxx_delay
rcs_version
aic7xxx_info
aic7xxx_putscb
aic7xxx_putdmascb
aic7xxx_getscb
aic7xxx_length
aic7xxx_scsirate
aic7xxx_isr
aic7xxx_probe
read_seeprom
detect_maxscb
aic7xxx_register
aic7xxx_detect
aic7xxx_buildscb
aic7xxx_queue
aic7xxx_kill
aic7xxx_abort
aic7xxx_reset
aic7xxx_biosparam
   1 /*+M*************************************************************************
   2  * Adaptec 274x/284x/294x device driver for Linux.
   3  *
   4  * Copyright (c) 1994 John Aycock
   5  *   The University of Calgary Department of Computer Science.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  * An alternate version of this driver with a BSD-style copyright can
  22  * be found on XXX.
  23  *
  24  * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F
  25  * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA
  26  * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide,
  27  * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux,
  28  * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file
  29  * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual,
  30  * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the
  31  * ANSI SCSI-2 specification (draft 10c), ...
  32  *
  33  * ----------------------------------------------------------------
  34  *  Modified to include support for wide and twin bus adapters,
  35  *  DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes,
  36  *  and other rework of the code.
  37  *
  38  *  Parts of this driver are based on the FreeBSD driver by Justin
  39  *  T. Gibbs.
  40  *
  41  *  A Boot time option was also added for not resetting the scsi bus.
  42  *
  43  *    Form:  aic7xxx=extended,no_reset
  44  *
  45  *    -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95
  46  *
  47  *  $Id: aic7xxx.c,v 1.49 1995/06/28 05:41:09 deang Exp $
  48  *-M*************************************************************************/
  49 
  50 #ifdef MODULE
  51 #include <linux/module.h>
  52 #endif
  53 
  54 #include <stdarg.h>
  55 #include <asm/io.h>
  56 #include <linux/string.h>
  57 #include <linux/kernel.h>
  58 #include <linux/ioport.h>
  59 #include <linux/bios32.h>
  60 #include <linux/delay.h>
  61 #include <linux/sched.h>
  62 #include <linux/pci.h>
  63 #include <linux/proc_fs.h>
  64 #include "../block/blk.h"
  65 #include "sd.h"
  66 #include "scsi.h"
  67 #include "hosts.h"
  68 #include "aic7xxx.h"
  69 
  70 #define AIC7XXX_C_VERSION  "$Revision: 1.49 $"
  71 
  72 #define NUMBER(arr)     (sizeof(arr) / sizeof(arr[0]))
  73 #define MIN(a,b) ((a < b) ? a : b)
  74 
  75 /*
  76  * Defines for PCI bus support, testing twin bus support, DMAing of
  77  * SCBs, and tagged queueing.
  78  *
  79  *   o PCI bus support - this has been implemented and working since
  80  *     the December 1, 1994 release of this driver. If you don't have
  81  *     a PCI bus and do not wish to configure your kernel with PCI
  82  *     support, then make sure this define is set to the cprrect
  83  *     define for PCI support (CONFIG_PCI) and configure your kernel
  84  *     without PCI support (make config).
  85  *
  86  *   o Twin bus support - this has been tested and does work.
  87  *
  88  *   o DMAing of SCBs - thanks to Kai Makisara, this now works
  89  *
  90  *   o Tagged queueing - this driver is capable of tagged queueing
  91  *     but I am unsure as to how well the higher level driver implements
  92  *     tagged queueing. Therefore, the maximum commands per lun is
  93  *     set to 2. If you want to implement tagged queueing, ensure
  94  *     this define is not commented out.
  95  *
  96  *   o Sharing IRQs - allowed for sharing of IRQs. This will allow
  97  *     for multiple aic7xxx host adapters sharing the same IRQ, but
  98  *     not for sharing IRQs with other devices. The higher level
  99  *     PCI code and interrupt handling needs to be modified to
 100  *     support this.
 101  *
 102  *  Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95
 103  */
 104 
 105 /* Uncomment this for testing twin bus support. */
 106 #define AIC7XXX_TWIN_SUPPORT
 107 
 108 /* Uncomment this for DMAing of SCBs. */
 109 #define AIC7XXX_USE_DMA
 110 
 111 /* Uncomment this for tagged queueing. */
 112 /* #define AIC7XXX_TAGGED_QUEUEING */
 113 
 114 /* Uncomment this for allowing sharing of IRQs. */
 115 #define AIC7XXX_SHARE_IRQS
 116 
 117 /* Set this to the delay in seconds after SCSI bus reset. */
 118 #define AIC7XXX_RESET_DELAY 15
 119 
 120 /*
 121  * Uncomment this to always use scatter/gather lists.
 122  * *NOTE: The sequencer must be changed also!
 123  */
 124 #define AIC7XXX_USE_SG
 125 
 126 /*
 127  * Controller type and options
 128  */
 129 typedef enum {
 130   AIC_NONE,
 131   AIC_274x,    /* EISA aic7770 */
 132   AIC_284x,    /* VLB  aic7770 */
 133   AIC_7870,    /* PCI  aic7870 */
 134   AIC_7850,    /* PCI  aic7850 */
 135   AIC_7872     /* PCI  aic7870 on 394x */
 136 } aha_type;
 137 
 138 typedef enum {
 139   AIC_SINGLE,  /* Single Channel */
 140   AIC_TWIN,    /* Twin Channel */
 141   AIC_WIDE     /* Wide Channel */
 142 } aha_bus_type;
 143 
 144 typedef enum {
 145   AIC_UNKNOWN,
 146   AIC_ENABLED,
 147   AIC_DISABLED
 148 } aha_status_type;
 149 
 150 /*
 151  * There should be a specific return value for this in scsi.h, but
 152  * it seems that most drivers ignore it.
 153  */
 154 #define DID_UNDERFLOW   DID_ERROR
 155 
 156 /*
 157  *  What we want to do is have the higher level scsi driver requeue
 158  *  the command to us. There is no specific driver status for this
 159  *  condition, but the higher level scsi driver will requeue the
 160  *  command on a DID_BUS_BUSY error.
 161  */
 162 #define DID_RETRY_COMMAND DID_BUS_BUSY
 163 
 164 /*
 165  * EISA/VL-bus stuff
 166  */
 167 #define MINSLOT         1
 168 #define MAXSLOT         15
 169 #define SLOTBASE(x)     ((x) << 12)
 170 #define MAXIRQ          15
 171 
 172 /*
 173  * Standard EISA Host ID regs  (Offset from slot base)
 174  */
 175 #define HID0(x)         ((x) + 0xC80)   /* 0,1: msb of ID2, 2-7: ID1      */
 176 #define HID1(x)         ((x) + 0xC81)   /* 0-4: ID3, 5-7: LSB ID2         */
 177 #define HID2(x)         ((x) + 0xC82)   /* product                        */
 178 #define HID3(x)         ((x) + 0xC83)   /* firmware revision              */
 179 
 180 /*
 181  * AIC-7770 I/O range to reserve for a card
 182  */
 183 #define MINREG(x)       ((x) + 0xC00ul)
 184 #define MAXREG(x)       ((x) + 0xCBFul)
 185 
 186 /* -------------------- AIC-7770 offset definitions ----------------------- */
 187 
 188 /*
 189  * SCSI Sequence Control (p. 3-11).
 190  * Each bit, when set starts a specific SCSI sequence on the bus
 191  */
 192 #define SCSISEQ(x)              ((x) + 0xC00ul)
 193 #define         TEMODEO         0x80
 194 #define         ENSELO          0x40
 195 #define         ENSELI          0x20
 196 #define         ENRSELI         0x10
 197 #define         ENAUTOATNO      0x08
 198 #define         ENAUTOATNI      0x04
 199 #define         ENAUTOATNP      0x02
 200 #define         SCSIRSTO        0x01
 201 
 202 /*
 203  * SCSI Transfer Control 1 Register (pp. 3-14,15).
 204  * Controls the SCSI module data path.
 205  */
 206 #define SXFRCTL1(x)             ((x) + 0xC02ul)
 207 #define         BITBUCKET       0x80
 208 #define         SWRAPEN         0x40
 209 #define         ENSPCHK         0x20
 210 #define         STIMESEL        0x18
 211 #define         ENSTIMER        0x04
 212 #define         ACTNEGEN        0x02
 213 #define         STPWEN          0x01            /* Powered Termination */
 214 
 215 /*
 216  * SCSI Control Signal Read Register (p. 3-15).
 217  * Reads the actual state of the SCSI bus pins
 218  */
 219 #define SCSISIGI(x)             ((x) + 0xC03ul)
 220 #define         CDI             0x80
 221 #define         IOI             0x40
 222 #define         MSGI            0x20
 223 #define         ATNI            0x10
 224 #define         SELI            0x08
 225 #define         BSYI            0x04
 226 #define         REQI            0x02
 227 #define         ACKI            0x01
 228 
 229 /*
 230  * SCSI Contol Signal Write Register (p. 3-16).
 231  * Writing to this register modifies the control signals on the bus. Only
 232  * those signals that are allowed in the current mode (Initiator/Target) are
 233  * asserted.
 234  */
 235 #define SCSISIGO(x)             ((x) + 0xC03ul)
 236 #define         CDO             0x80
 237 #define         IOO             0x40
 238 #define         MSGO            0x20
 239 #define         ATNO            0x10
 240 #define         SELO            0x08
 241 #define         BSYO            0x04
 242 #define         REQO            0x02
 243 #define         ACKO            0x01
 244 
 245 /*
 246  * SCSI Rate
 247  */
 248 #define SCSIRATE(x)             ((x) + 0xC04ul)
 249 
 250 /*
 251  * SCSI ID (p. 3-18).
 252  * Contains the ID of the board and the current target on the
 253  * selected channel
 254  */
 255 #define SCSIID(x)               ((x) + 0xC05ul)
 256 #define         TID             0xF0            /* Target ID mask */
 257 #define         OID             0x0F            /* Our ID mask */
 258 
 259 /*
 260  * SCSI Status 0 (p. 3-21)
 261  * Contains one set of SCSI Interrupt codes
 262  * These are most likely of interest to the sequencer
 263  */
 264 #define SSTAT0(x)               ((x) + 0xC0Bul)
 265 #define         TARGET          0x80            /* Board is a target */
 266 #define         SELDO           0x40            /* Selection Done */
 267 #define         SELDI           0x20            /* Board has been selected */
 268 #define         SELINGO         0x10            /* Selection In Progress */
 269 #define         SWRAP           0x08            /* 24bit counter wrap */
 270 #define         SDONE           0x04            /* STCNT = 0x000000 */
 271 #define         SPIORDY         0x02            /* SCSI PIO Ready */
 272 #define         DMADONE         0x01            /* DMA transfer completed */
 273 
 274 /*
 275  * Clear SCSI Interrupt 1 (p. 3-23)
 276  * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 277  */
 278 #define CLRSINT1(x)             ((x) + 0xC0Cul)
 279 #define         CLRSELTIMEO     0x80
 280 #define         CLRATNO         0x40
 281 #define         CLRSCSIRSTI     0x20
 282 /*  UNUSED                      0x10 */
 283 #define         CLRBUSFREE      0x08
 284 #define         CLRSCSIPERR     0x04
 285 #define         CLRPHASECHG     0x02
 286 #define         CLRREQINIT      0x01
 287 
 288 /*
 289  * SCSI Status 1 (p. 3-24)
 290  * These interrupt bits are of interest to the kernel driver
 291  */
 292 #define SSTAT1(x)               ((x) + 0xC0Cul)
 293 #define         SELTO           0x80
 294 #define         ATNTARG         0x40
 295 #define         SCSIRSTI        0x20
 296 #define         PHASEMIS        0x10
 297 #define         BUSFREE         0x08
 298 #define         SCSIPERR        0x04
 299 #define         PHASECHG        0x02
 300 #define         REQINIT         0x01
 301 
 302 /*
 303  * SCSI Interrrupt Mode 1 (pp. 3-28,29).
 304  * Set bits in this register enable the corresponding
 305  * interrupt source.
 306  */
 307 #define SIMODE1(x)              ((x) + 0xC11ul)
 308 #define         ENSELTIMO       0x80
 309 #define         ENATNTARG       0x40
 310 #define         ENSCSIRST       0x20
 311 #define         ENPHASEMIS      0x10
 312 #define         ENBUSFREE       0x08
 313 #define         ENSCSIPERR      0x04
 314 #define         ENPHASECHG      0x02
 315 #define         ENREQINIT       0x01
 316 
 317 /*
 318  * Selection/Reselection ID (p. 3-31)
 319  * Upper four bits are the device id. The ONEBIT is set when the re/selecting
 320  * device did not set its own ID.
 321  */
 322 #define SELID(x)                ((x) + 0xC19ul)
 323 #define         SELID_MASK      0xF0
 324 #define         ONEBIT          0x08
 325 /*  UNUSED                      0x07 */
 326 
 327 /*
 328  * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 329  * Controls the reading and writing of an external serial 1-bit
 330  * EEPROM Device.  In order to access the serial EEPROM, you must
 331  * first set the SEEMS bit that generates a request to the memory
 332  * port for access to the serial EEPROM device.  When the memory
 333  * port is not busy servicing another request, it reconfigures
 334  * to allow access to the serial EEPROM.  When this happens, SEERDY
 335  * gets set high to verify that the memory port access has been
 336  * granted.  See aic7xxx_read_eprom for detailed information on
 337  * the protocol necessary to read the serial EEPROM.
 338  */
 339 #define SEECTL(x)               ((x) + 0xC1Eul)
 340 #define         EXTARBACK       0x80
 341 #define         EXTARBREQ       0x40
 342 #define         SEEMS           0x20
 343 #define         SEERDY          0x10
 344 #define         SEECS           0x08
 345 #define         SEECK           0x04
 346 #define         SEEDO           0x02
 347 #define         SEEDI           0x01
 348 
 349 /*
 350  * SCSI Block Control (p. 3-32)
 351  * Controls Bus type and channel selection. In a twin channel configuration
 352  * addresses 0x00-0x1E are gated to the appropriate channel based on this
 353  * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
 354  * on a wide bus.
 355  */
 356 #define SBLKCTL(x)              ((x) + 0xC1Ful)
 357 /*  UNUSED                      0xC0 */
 358 #define         AUTOFLUSHDIS    0x20            /* used for Rev C check */
 359 /*  UNUSED                      0x10 */
 360 #define         SELBUSB         0x08
 361 /*  UNUSED                      0x04 */
 362 #define         SELWIDE         0x02
 363 /*  UNUSED                      0x01 */
 364 #define         SELSINGLE       0x00
 365 
 366 /*
 367  * Sequencer Control (p. 3-33)
 368  * Error detection mode and speed configuration
 369  */
 370 #define SEQCTL(x)               ((x) + 0xC60ul)
 371 #define         PERRORDIS       0x80
 372 #define         PAUSEDIS        0x40
 373 #define         FAILDIS         0x20
 374 #define         FASTMODE        0x10
 375 #define         BRKADRINTEN     0x08
 376 #define         STEP            0x04
 377 #define         SEQRESET        0x02
 378 #define         LOADRAM         0x01
 379 
 380 /*
 381  * Sequencer RAM Data (p. 3-34)
 382  * Single byte window into the Scratch Ram area starting at the address
 383  * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
 384  * four bytes in sucessesion. The SEQADDRs will increment after the most
 385  * significant byte is written
 386  */
 387 #define SEQRAM(x)               ((x) + 0xC61ul)
 388 
 389 /*
 390  * Sequencer Address Registers (p. 3-35)
 391  * Only the first bit of SEQADDR1 holds addressing information
 392  */
 393 #define SEQADDR0(x)             ((x) + 0xC62ul)
 394 #define SEQADDR1(x)             ((x) + 0xC63ul)
 395 
 396 #define ACCUM(x)                ((x) + 0xC64ul)         /* accumulator */
 397 
 398 /*
 399  * Board Control (p. 3-43)
 400  */
 401 #define BCTL(x)         ((x) + 0xC84ul)
 402 /*   RSVD                       0xF0 */
 403 #define         ACE             0x08    /* Support for external processors */
 404 /*   RSVD                       0x06 */
 405 #define         ENABLE          0x01
 406 
 407 #define BUSSPD(x)               ((x) + 0xC86ul) /* FIFO threshold bits ? */
 408 
 409 /*
 410  * Host Control (p. 3-47) R/W
 411  * Overal host control of the device.
 412  */
 413 #define HCNTRL(x)               ((x) + 0xC87ul)
 414 /*    UNUSED                    0x80 */
 415 #define         POWRDN          0x40
 416 /*    UNUSED                    0x20 */
 417 #define         SWINT           0x10
 418 #define         IRQMS           0x08
 419 #define         PAUSE           0x04
 420 #define         INTEN           0x02
 421 #define         CHIPRST         0x01
 422 #define         REQ_PAUSE       IRQMS | PAUSE | INTEN
 423 #define         UNPAUSE_274X    IRQMS | INTEN
 424 #define         UNPAUSE_284X    INTEN
 425 #define         UNPAUSE_294X    IRQMS | INTEN
 426 
 427 /*
 428  * SCB Pointer (p. 3-49)
 429  * Gate one of the four SCBs into the SCBARRAY window.
 430  */
 431 #define SCBPTR(x)               ((x) + 0xC90ul)
 432 
 433 /*
 434  * Interrupt Status (p. 3-50)
 435  * Status for system interrupts
 436  */
 437 #define INTSTAT(x)              ((x) + 0xC91ul)
 438 #define         SEQINT_MASK     0xF0            /* SEQINT Status Codes */
 439 #define                 BAD_PHASE       0x00
 440 #define                 SEND_REJECT     0x10
 441 #define                 NO_IDENT        0x20
 442 #define                 NO_MATCH        0x30
 443 #define                 MSG_SDTR        0x40
 444 #define                 MSG_WDTR        0x50
 445 #define                 MSG_REJECT      0x60
 446 #define                 BAD_STATUS      0x70
 447 #define                 RESIDUAL        0x80
 448 #define                 ABORT_TAG       0x90
 449 #define                 AWAITING_MSG    0xa0
 450 #define         BRKADRINT 0x08
 451 #define         SCSIINT   0x04
 452 #define         CMDCMPLT  0x02
 453 #define         SEQINT    0x01
 454 #define         INT_PEND  (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
 455 
 456 /*
 457  * Hard Error (p. 3-53)
 458  * Reporting of catastrophic errors. You usually cannot recover from
 459  * these without a full board reset.
 460  */
 461 #define ERROR(x)                ((x) + 0xC92ul)
 462 /*    UNUSED                    0xF0 */
 463 #define         PARERR          0x08
 464 #define         ILLOPCODE       0x04
 465 #define         ILLSADDR        0x02
 466 #define         ILLHADDR        0x01
 467 
 468 /*
 469  * Clear Interrupt Status (p. 3-52)
 470  */
 471 #define CLRINT(x)               ((x) + 0xC92ul)
 472 #define         CLRBRKADRINT    0x08
 473 #define         CLRSCSIINT      0x04
 474 #define         CLRCMDINT       0x02
 475 #define         CLRSEQINT       0x01
 476 
 477 /*
 478  * SCB Auto Increment (p. 3-59)
 479  * Byte offset into the SCB Array and an optional bit to allow auto
 480  * incrementing of the address during download and upload operations
 481  */
 482 #define SCBCNT(x)               ((x) + 0xC9Aul)
 483 #define         SCBAUTO         0x80
 484 #define         SCBCNT_MASK     0x1F
 485 
 486 /*
 487  * Queue In FIFO (p. 3-60)
 488  * Input queue for queued SCBs (commands that the seqencer has yet to start)
 489  */
 490 #define QINFIFO(x)              ((x) + 0xC9Bul)
 491 
 492 /*
 493  * Queue In Count (p. 3-60)
 494  * Number of queued SCBs
 495  */
 496 #define QINCNT(x)               ((x) + 0xC9Cul)
 497 
 498 /*
 499  * Queue Out FIFO (p. 3-61)
 500  * Queue of SCBs that have completed and await the host
 501  */
 502 #define QOUTFIFO(x)             ((x) + 0xC9Dul)
 503 
 504 /*
 505  * Queue Out Count (p. 3-61)
 506  * Number of queued SCBs in the Out FIFO
 507  */
 508 #define QOUTCNT(x)              ((x) + 0xC9Eul)
 509 
 510 #define SCBARRAY(x)             ((x) + 0xCA0ul)
 511 
 512 /* ---------------- END AIC-7770 Register Definitions ----------------- */
 513 
 514 /* --------------------- AIC-7870-only definitions -------------------- */
 515 
 516 #define DSPCISTATUS(x)          ((x) + 0xC86ul)
 517 #define         DFTHRESH        0xC0
 518 
 519 /* Scratch RAM offset definitions */
 520 
 521 /* ---------------------- Scratch RAM Offsets ------------------------- */
 522 /* These offsets are either to values that are initialized by the board's
 523  * BIOS or are specified by the Linux sequencer code. If I can figure out
 524  * how to read the EISA configuration info at probe time, the cards could
 525  * be run without BIOS support installed
 526  */
 527 
 528 /*
 529  * 1 byte per target starting at this address for configuration values
 530  */
 531 #define HA_TARG_SCRATCH(x)      ((x) + 0xC20ul)
 532 
 533 /*
 534  * The sequencer will stick the first byte of any rejected message here so
 535  * we can see what is getting thrown away.
 536  */
 537 #define HA_REJBYTE(x)           ((x) + 0xC31ul)
 538 
 539 /*
 540  * Bit vector of targets that have disconnection disabled.
 541  */
 542 #define HA_DISC_DSB             ((x) + 0xc32ul)
 543 
 544 /*
 545  * Length of pending message
 546  */
 547 #define HA_MSG_LEN(x)           ((x) + 0xC34ul)
 548 
 549 /*
 550  * Outgoing Message Body
 551  */
 552 #define HA_MSG_START(x)         ((x) + 0xC35ul)
 553 
 554 /*
 555  * These are offsets into the card's scratch ram. Some of the values are
 556  * specified in the AHA2742 technical reference manual and are initialized
 557  * by the BIOS at boot time.
 558  */
 559 #define HA_ARG_1(x)             ((x) + 0xC4Aul) /* sdtr <-> rate parameters */
 560 #define HA_RETURN_1(x)          ((x) + 0xC4Aul)
 561 #define         SEND_SENSE      0x80
 562 #define         SEND_SDTR       0x80
 563 #define         SEND_WDTR       0x80
 564 #define         SEND_REJ        0x40
 565 
 566 #define HA_SIGSTATE(x)          ((x) + 0xC4Bul) /* value in SCSISIGO */
 567 #define HA_SCBCOUNT(x)          ((x) + 0xC52ul) /* number of hardware SCBs */
 568 
 569 #define HA_FLAGS(x)             ((x) + 0xC53ul) /* TWIN and WIDE bus flags */
 570 #define         SINGLE_BUS      0x00
 571 #define         TWIN_BUS        0x01
 572 #define         WIDE_BUS        0x02
 573 #define         ACTIVE_MSG      0x20
 574 #define         IDENTIFY_SEEN   0x40
 575 #define         RESELECTING     0x80
 576 
 577 #define HA_ACTIVE0(x)           ((x) + 0xC54ul) /* Active bits; targets 0-7 */
 578 #define HA_ACTIVE1(x)           ((x) + 0xC55ul) /* Active bits; targets 8-15 */
 579 #define SAVED_TCL(x)            ((x) + 0xC56ul) /* Saved target, channel, LUN */
 580 #define WAITING_SCBH(x)         ((x) + 0xC57ul) /* Head of disconnected targets list. */
 581 #define WAITING_SCBT(x)         ((x) + 0xC58ul) /* Tail of disconnected targets list. */
 582 
 583 #define HA_SCSICONF(x)          ((x) + 0xC5Aul) /* SCSI config register */
 584 #define HA_INTDEF(x)            ((x) + 0xC5Cul) /* interrupt def'n register */
 585 #define HA_HOSTCONF(x)          ((x) + 0xC5Dul) /* host config def'n register */
 586 
 587 #define MSG_ABORT               0x06
 588 #define MSG_BUS_DEVICE_RESET    0x0c
 589 #define BUS_8_BIT               0x00
 590 #define BUS_16_BIT              0x01
 591 #define BUS_32_BIT              0x02
 592 
 593 
 594 /*
 595  *
 596  * Define the format of the SEEPROM registers (16 bits).
 597  *
 598  */
 599 struct seeprom_config {
 600 
 601 /*
 602  * SCSI ID Configuration Flags
 603  */
 604 #define CFXFER          0x0007          /* synchronous transfer rate */
 605 #define CFSYNCH         0x0008          /* enable synchronous transfer */
 606 #define CFDISC          0x0010          /* enable disconnection */
 607 #define CFWIDEB         0x0020          /* wide bus device */
 608 /* UNUSED               0x00C0 */
 609 #define CFSTART         0x0100          /* send start unit SCSI command */
 610 #define CFINCBIOS       0x0200          /* include in BIOS scan */
 611 #define CFRNFOUND       0x0400          /* report even if not found */
 612 /* UNUSED               0xF800 */
 613   unsigned short device_flags[16];      /* words 0-15 */
 614 
 615 /*
 616  * BIOS Control Bits
 617  */
 618 #define CFSUPREM        0x0001          /* support all removeable drives */
 619 #define CFSUPREMB       0x0002          /* support removeable drives for boot only */
 620 #define CFBIOSEN        0x0004          /* BIOS enabled */
 621 /* UNUSED               0x0008 */
 622 #define CFSM2DRV        0x0010          /* support more than two drives */
 623 /* UNUSED               0x0060 */
 624 #define CFEXTEND        0x0080          /* extended translation enabled */
 625 /* UNUSED               0xFF00 */
 626   unsigned short bios_control;          /* word 16 */
 627 
 628 /*
 629  * Host Adapter Control Bits
 630  */
 631 /* UNUSED               0x0003 */
 632 #define CFWSTERM        0x0008          /* SCSI high byte termination (wide card) */
 633 #define CFSTERM         0x0004          /* SCSI low byte termination (non-wide cards) */
 634 #define CFSPARITY       0x0010          /* SCSI parity */
 635 /* UNUSED               0x0020 */
 636 #define CFRESETB        0x0040          /* reset SCSI bus at IC initialization */
 637 /* UNUSED               0xFF80 */
 638   unsigned short adapter_control;       /* word 17 */
 639 
 640 /*
 641  * Bus Release, Host Adapter ID
 642  */
 643 #define CFSCSIID        0x000F          /* host adapter SCSI ID */
 644 /* UNUSED               0x00F0 */
 645 #define CFBRTIME        0xFF00          /* bus release time */
 646   unsigned short brtime_id;             /* word 18 */
 647 
 648 /*
 649  * Maximum targets
 650  */
 651 #define CFMAXTARG       0x00FF  /* maximum targets */
 652 /* UNUSED               0xFF00 */
 653   unsigned short max_targets;           /* word 19 */
 654 
 655   unsigned short res_1[11];             /* words 20-30 */
 656   unsigned short checksum;              /* word 31 */
 657 
 658 };
 659 
 660 
 661 #define AIC7XXX_DEBUG
 662 
 663 /*
 664  * Pause the sequencer and wait for it to actually stop - this
 665  * is important since the sequencer can disable pausing for critical
 666  * sections.
 667  */
 668 #define PAUSE_SEQUENCER(p) \
 669   outb(p->pause, HCNTRL(p->base));                      \
 670   while ((inb(HCNTRL(p->base)) & PAUSE) == 0)           \
 671     ;                                                   \
 672 
 673 /*
 674  * Unpause the sequencer. Unremarkable, yet done often enough to
 675  * warrant an easy way to do it.
 676  */
 677 #define UNPAUSE_SEQUENCER(p) \
 678   outb(p->unpause, HCNTRL(p->base))
 679 
 680 /*
 681  * Restart the sequencer program from address zero
 682  */
 683 #define RESTART_SEQUENCER(p) \
 684   do {                                                  \
 685     outb(SEQRESET | FASTMODE, SEQCTL(p->base)); \
 686   } while (inb(SEQADDR0(p->base)) != 0 &&               \
 687            inb(SEQADDR1(p->base)) != 0);                \
 688   UNPAUSE_SEQUENCER(p);
 689 
 690 /*
 691  * If an error occurs during a data transfer phase, run the comand
 692  * to completion - it's easier that way - making a note of the error
 693  * condition in this location. This then will modify a DID_OK status
 694  * into an appropriate error for the higher-level SCSI code.
 695  */
 696 #define aic7xxx_error(cmd)      ((cmd)->SCp.Status)
 697 
 698 /*
 699  * Keep track of the targets returned status.
 700  */
 701 #define aic7xxx_status(cmd)     ((cmd)->SCp.sent_command)
 702 
 703 /*
 704  * The position of the SCSI commands scb within the scb array.
 705  */
 706 #define aic7xxx_position(cmd)   ((cmd)->SCp.have_data_in)
 707 
 708 /*
 709  * Since the sequencer code DMAs the scatter-gather structures
 710  * directly from memory, we use this macro to assert that the
 711  * kernel structure hasn't changed.
 712  */
 713 #define SG_STRUCT_CHECK(sg) \
 714   ((char *)&(sg).address - (char *)&(sg) != 0 ||  \
 715    (char *)&(sg).length  - (char *)&(sg) != 8 ||  \
 716    sizeof((sg).address) != 4 ||                   \
 717    sizeof((sg).length)  != 4 ||                   \
 718    sizeof(sg)           != 12)
 719 
 720 /*
 721  * "Static" structures. Note that these are NOT initialized
 722  * to zero inside the kernel - we have to initialize them all
 723  * explicitly.
 724  *
 725  * We support a maximum of one adapter card per IRQ level (see the
 726  * rationale for this above). On an interrupt, use the IRQ as an
 727  * index into aic7xxx_boards[] to locate the card information.
 728  */
 729 static struct Scsi_Host *aic7xxx_boards[MAXIRQ + 1];
 730 
 731 /*
 732  * The driver keeps up to four scb structures per card in memory. Only the
 733  * first 26 bytes of the structure are valid for the hardware, the rest used
 734  * for driver level bookeeping. The driver is further optimized
 735  * so that we only have to download the first 19 bytes since as long
 736  * as we always use S/G, the last fields should be zero anyway.
 737  */
 738 #ifdef AIC7XXX_USE_SG
 739 #define SCB_DOWNLOAD_SIZE       19      /* amount to actually download */
 740 #else
 741 #define SCB_DOWNLOAD_SIZE       26
 742 #endif
 743 
 744 #define SCB_UPLOAD_SIZE         19      /* amount to actually upload */
 745 
 746 struct aic7xxx_scb {
 747 /* ------------    Begin hardware supported fields    ---------------- */
 748 /*1 */  unsigned char control;
 749 #define SCB_NEEDWDTR 0x80                       /* Initiate Wide Negotiation */
 750 #define SCB_NEEDSDTR 0x40                       /* Initiate Sync Negotiation */
 751 #define SCB_NEEDDMA  0x08                       /* SCB needs to be DMA'd from
 752                                                  * from host memory
 753                                                  */
 754 #define SCB_REJ_MDP      0x80                   /* Reject MDP message */
 755 #define SCB_DISEN        0x40                   /* SCB Disconnect enable */
 756 #define SCB_TE           0x20                   /* Tag enable */
 757 /*      RESERVED         0x10 */
 758 #define SCB_WAITING      0x08                   /* Waiting */
 759 #define SCB_DIS          0x04                   /* Disconnected */
 760 #define SCB_TAG_TYPE     0x03
 761 #define         SIMPLE_QUEUE 0x00               /* Simple Queue */
 762 #define         HEAD_QUEUE   0x01               /* Head of Queue */
 763 #define         ORD_QUEUE    0x02               /* Ordered Queue */
 764 /*              ILLEGAL      0x03 */
 765 /*2 */  unsigned char target_channel_lun;       /* 4/1/3 bits */
 766 /*3 */  unsigned char SG_segment_count;
 767 /*7 */  unsigned char SG_list_pointer[4] __attribute__ ((packed));
 768 /*11*/  unsigned char SCSI_cmd_pointer[4] __attribute__ ((packed));
 769 /*12*/  unsigned char SCSI_cmd_length;
 770 /*14*/  unsigned char RESERVED[2];              /* must be zero */
 771 /*15*/  unsigned char target_status;
 772 /*18*/  unsigned char residual_data_count[3];
 773 /*19*/  unsigned char residual_SG_segment_count;
 774 /*23*/  unsigned char data_pointer[4] __attribute__ ((packed));
 775 /*26*/  unsigned char data_count[3];
 776 /*30*/  unsigned char host_scb[4] __attribute__ ((packed));
 777 /*31*/  u_char next_waiting;            /* Used to thread SCBs awaiting selection. */
 778 #define SCB_LIST_NULL 0x10              /* SCB list equivelent to NULL */
 779 #if 0
 780         /*
 781          *  No real point in transferring this to the
 782          *  SCB registers.
 783          */
 784         unsigned char RESERVED[1];
 785 #endif
 786 
 787         /*-----------------end of hardware supported fields----------------*/
 788         struct aic7xxx_scb *next;       /* next ptr when in free list */
 789         Scsi_Cmnd          *cmd;        /* Scsi_Cmnd for this scb */
 790         int                 state;      /* current state of scb */
 791 #define SCB_FREE               0x00
 792 #define SCB_ACTIVE             0x01
 793 #define SCB_ABORTED            0x02
 794 #define SCB_DEVICE_RESET       0x04
 795 #define SCB_IMMED              0x08
 796 #define SCB_SENSE              0x10
 797         unsigned int        position;       /* Position in scb array */
 798 #ifdef AIC7XXX_USE_SG
 799         struct scatterlist  sg;
 800         struct scatterlist  sense_sg;
 801 #endif
 802         unsigned char       sense_cmd[6];   /* Allocate 6 characters for sense command */
 803 };
 804 
 805 static struct {
 806   unsigned char errno;
 807   char *errmesg;
 808 } hard_error[] = {
 809   { ILLHADDR,  "Illegal Host Access" },
 810   { ILLSADDR,  "Illegal Sequencer Address referrenced" },
 811   { ILLOPCODE, "Illegal Opcode in sequencer program" },
 812   { PARERR,    "Sequencer Ram Parity Error" }
 813 };
 814 
 815 static unsigned char
 816 generic_sense[] = { REQUEST_SENSE, 0, 0, 0, 255, 0 };
 817 
 818 /*
 819  * The maximum number of SCBs we could have for ANY type
 820  * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE
 821  * SEQUENCER CODE IF THIS IS MODIFIED!
 822  */
 823 #define AIC7XXX_MAXSCB  16
 824 
 825 /*
 826  * Define a structure used for each host adapter, only one per IRQ.
 827  */
 828 struct aic7xxx_host {
 829   int                      base;             /* card base address */
 830   int                      maxscb;           /* hardware SCBs */
 831   int                      numscb;           /* current number of scbs */
 832   int                      extended;         /* extended xlate? */
 833   aha_type                 type;             /* card type */
 834   aha_bus_type             bus_type;         /* normal/twin/wide bus */
 835   unsigned char            a_scanned;        /* 0 not scanned, 1 scanned */
 836   unsigned char            b_scanned;        /* 0 not scanned, 1 scanned */
 837   unsigned int             isr_count;        /* Interrupt count */
 838   volatile unsigned char   unpause;          /* unpause value for HCNTRL */
 839   volatile unsigned char   pause;            /* pause value for HCNTRL */
 840   volatile unsigned short  needsdtr_copy;    /* default config */
 841   volatile unsigned short  needsdtr;
 842   volatile unsigned short  sdtr_pending;
 843   volatile unsigned short  needwdtr_copy;    /* default config */
 844   volatile unsigned short  needwdtr;
 845   volatile unsigned short  wdtr_pending;
 846   struct seeprom_config    seeprom;
 847   int                      have_seeprom;
 848   struct Scsi_Host        *next;             /* allow for multiple IRQs */
 849   struct aic7xxx_scb       scb_array[AIC7XXX_MAXSCB];  /* active commands */
 850   struct aic7xxx_scb      *free_scb;         /* list of free SCBs */
 851 };
 852 
 853 struct aic7xxx_host_config {
 854   int              irq;        /* IRQ number */
 855   int              base;       /* I/O base */
 856   int              maxscb;     /* hardware SCBs */
 857   int              unpause;    /* unpause value for HCNTRL */
 858   int              pause;      /* pause value for HCNTRL */
 859   int              scsi_id;    /* host SCSI ID */
 860   int              scsi_id_b;  /* host SCSI ID B channel for twin cards */
 861   int              extended;   /* extended xlate? */
 862   int              busrtime;   /* bus release time */
 863   aha_type         type;       /* card type */
 864   aha_bus_type     bus_type;   /* normal/twin/wide bus */
 865   aha_status_type  parity;     /* bus parity enabled/disabled */
 866   aha_status_type  low_term;   /* bus termination low byte */
 867   aha_status_type  high_term;  /* bus termination high byte (wide cards only) */
 868 };
 869 
 870 /*
 871  * Valid SCSIRATE values. (p. 3-17)
 872  * Provides a mapping of tranfer periods in ns to the proper value to
 873  * stick in the scsiscfr reg to use that transfer rate.
 874  */
 875 static struct {
 876   short period;
 877   short rate;
 878   char *english;
 879 } aic7xxx_syncrates[] = {
 880   { 100,   0,  "10.0" },
 881   { 125,   1,  "8.0"  },
 882   { 150,   2,  "6.67" },
 883   { 175,   3,  "5.7"  },
 884   { 200,   4,  "5.0"  },
 885   { 225,   5,  "4.4"  },
 886   { 250,   6,  "4.0"  },
 887   { 275,   7,  "3.6"  }
 888 };
 889 
 890 static int num_aic7xxx_syncrates =
 891     sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
 892 
 893 #ifdef AIC7XXX_DEBUG
 894 extern int vsprintf(char *, const char *, va_list);
 895 
 896 static void
 897 debug(const char *fmt, ...)
     /*  */
 898 {
 899   va_list ap;
 900   char buf[256];
 901 
 902   va_start(ap, fmt);
 903   vsprintf(buf, fmt, ap);
 904   printk(buf);
 905   va_end(ap);
 906 }
 907 
 908 static void
 909 debug_config(struct aic7xxx_host_config *p)
     /*  */
 910 {
 911   int host_conf, scsi_conf;
 912   unsigned char brelease;
 913   unsigned char dfthresh;
 914 
 915   static int DFT[] = { 0, 50, 75, 100 };
 916   static int SST[] = { 256, 128, 64, 32 };
 917   static char *BUSW[] = { "", "-TWIN", "-WIDE" };
 918 
 919   host_conf = inb(HA_HOSTCONF(p->base));
 920   scsi_conf = inb(HA_SCSICONF(p->base));
 921 
 922   /*
 923    * The 7870 gets the bus release time and data FIFO threshold
 924    * from the serial EEPROM (stored in the config structure) and
 925    * scsi_conf register respectively.  The 7770 gets the bus
 926    * release time and data FIFO threshold from the scsi_conf and
 927    * host_conf registers respectively.
 928    */
 929   if ((p->type == AIC_274x) || (p->type == AIC_284x))
 930   {
 931     brelease = scsi_conf & 0x3F;
 932     dfthresh = host_conf >> 6;
 933   }
 934   else
 935   {
 936     brelease = p->busrtime;
 937     dfthresh = scsi_conf >> 6;
 938   }
 939   if (brelease == 0)
 940   {
 941     brelease = 2;
 942   }
 943 
 944   switch (p->type)
 945   {
 946     case AIC_274x:
 947       printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
 948       break;
 949 
 950     case AIC_284x:
 951       printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
 952       break;
 953 
 954     case AIC_7870:
 955       printk("AIC7870%s (PCI-bus):\n", BUSW[p->bus_type]);
 956       break;
 957 
 958     case AIC_7850:
 959       printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
 960       break;
 961 
 962     case AIC_7872:
 963       printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
 964       break;
 965 
 966     default:
 967       panic("aic7xxx debug_config: internal error\n");
 968   }
 969 
 970   printk("    irq %d\n"
 971          "    bus release time %d bclks\n"
 972          "    data fifo threshold %d%%\n",
 973          p->irq,
 974          brelease,
 975          DFT[dfthresh]);
 976 
 977   printk("    SCSI CHANNEL A:\n"
 978          "        scsi id %d\n"
 979          "        scsi selection timeout %d ms\n"
 980          "        scsi bus reset at power-on %sabled\n",
 981          scsi_conf & 0x07,
 982          SST[(scsi_conf >> 3) & 0x03],
 983          (scsi_conf & 0x40) ? "en" : "dis");
 984 
 985   if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
 986   { /* Set the parity for 7770 based cards. */
 987     p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
 988   }
 989   if (p->parity != AIC_UNKNOWN)
 990   {
 991     printk("        scsi bus parity %sabled\n",
 992            (p->parity == AIC_ENABLED) ? "en" : "dis");
 993   }
 994 
 995   if (p->type == AIC_274x)
 996   {
 997     p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
 998   }
 999   if (p->low_term != AIC_UNKNOWN)
1000   {
1001     printk("        scsi bus termination (low byte) %sabled\n",
1002           (p->low_term == AIC_ENABLED) ? "en" : "dis");
1003   }
1004   if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1005   {
1006     printk("        scsi bus termination (high byte) %sabled\n",
1007           (p->high_term == AIC_ENABLED) ? "en" : "dis");
1008   }
1009 }
1010 #else
1011 #  define debug(fmt, args...)
1012 #  define debug_config(x)
1013 #endif AIC7XXX_DEBUG
1014 
1015 /*
1016  * XXX - these options apply unilaterally to _all_ 274x/284x/294x
1017  *       cards in the system. This should be fixed, but then,
1018  *       does anyone really have more than one in a machine?
1019  */
1020 static int aic7xxx_extended = 0;        /* extended translation on? */
1021 static int aic7xxx_no_reset = 0;        /* no resetting of SCSI bus */
1022 
1023 /*+F*************************************************************************
1024  * Function:
1025  *   aic7xxx_setup
1026  *
1027  * Description:
1028  *   Handle Linux boot parameters.
1029  *-F*************************************************************************/
1030 void
1031 aic7xxx_setup(char *s, int *dummy)
     /*  */
1032 {
1033   int   i;
1034   char *p;
1035 
1036   static struct {
1037     char *name;
1038     int *flag;
1039   } options[] = {
1040     { "extended",    &aic7xxx_extended },
1041     { "no_reset",    &aic7xxx_no_reset },
1042     { NULL,          NULL}
1043   };
1044 
1045   for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1046   {
1047     for (i = 0; options[i].name; i++)
1048     {
1049       if (!strcmp(options[i].name, p))
1050       {
1051         *(options[i].flag) = !0;
1052       }
1053     }
1054   }
1055 }
1056 
1057 /*+F*************************************************************************
1058  * Function:
1059  *   aic7xxx_loadseq
1060  *
1061  * Description:
1062  *   Load the sequencer code into the controller memory.
1063  *-F*************************************************************************/
1064 static void
1065 aic7xxx_loadseq(int base)
     /*  */
1066 {
1067   static unsigned char seqprog[] = {
1068     /*
1069      * Each sequencer instruction is 29 bits
1070      * long (fill in the excess with zeroes)
1071      * and has to be loaded from least -> most
1072      * significant byte, so this table has the
1073      * byte ordering reversed.
1074      */
1075 #   include "aic7xxx_seq.h"
1076   };
1077 
1078   /*
1079    * When the AIC-7770 is paused (as on chip reset), the
1080    * sequencer address can be altered and a sequencer
1081    * program can be loaded by writing it, byte by byte, to
1082    * the sequencer RAM port - the Adaptec documentation
1083    * recommends using REP OUTSB to do this, hence the inline
1084    * assembly. Since the address autoincrements as we load
1085    * the program, reset it back to zero afterward. Disable
1086    * sequencer RAM parity error detection while loading, and
1087    * make sure the LOADRAM bit is enabled for loading.
1088    */
1089   outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1090 
1091   asm volatile("cld\n\t"
1092                "rep\n\t"
1093                "outsb"
1094                : /* no output */
1095                :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1096                :"si", "cx", "dx");
1097 
1098   /*
1099    * WARNING!  This is a magic sequence!  After extensive
1100    * experimentation, it seems that you MUST turn off the
1101    * LOADRAM bit before you play with SEQADDR again, else
1102    * you will end up with parity errors being flagged on
1103    * your sequencer program. (You would also think that
1104    * turning off LOADRAM and setting SEQRESET to reset the
1105    * address to zero would work, but you need to do it twice
1106    * for it to take effect on the address. Timing problem?)
1107    */
1108   do {
1109     /*
1110      * Actually, reset it until
1111      * the address shows up as
1112      * zero just to be safe..
1113      */
1114     outb(SEQRESET | FASTMODE, SEQCTL(base));
1115   } while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1116 }
1117 
1118 /*+F*************************************************************************
1119  * Function:
1120  *   aic7xxx_delay
1121  *
1122  * Description:
1123  *   Delay for specified amount of time.
1124  *-F*************************************************************************/
1125 static void
1126 aic7xxx_delay(int seconds)
     /*  */
1127 {
1128   unsigned long i;
1129 
1130   i = jiffies + (seconds * 100);  /* compute time to stop */
1131 
1132   while (jiffies < i)
1133   {
1134     ;  /* Do nothing! */
1135   }
1136 }
1137 
1138 /*+F*************************************************************************
1139  * Function:
1140  *   rcs_version
1141  *
1142  * Description:
1143  *   Return a string containing just the RCS version number from either
1144  *   an Id or Revison RCS clause.
1145  *-F*************************************************************************/
1146 const char *
1147 rcs_version(const char *version_info)
     /*  */
1148 {
1149   static char buf[10];
1150   char *bp, *ep;
1151 
1152   bp = NULL;
1153   strcpy(buf, "????");
1154   if (!strncmp(version_info, "$Id: ", 5))
1155   {
1156     if ((bp = strchr(version_info, ' ')) != NULL)
1157     {
1158       bp++;
1159       if ((bp = strchr(bp, ' ')) != NULL)
1160       {
1161         bp++;
1162       }
1163     }
1164   }
1165   else
1166   {
1167     if (!strncmp(version_info, "$Revision: ", 11))
1168     {
1169       if ((bp = strchr(version_info, ' ')) != NULL)
1170       {
1171         bp++;
1172       }
1173     }
1174   }
1175 
1176   if (bp != NULL)
1177   {
1178     if ((ep = strchr(bp, ' ')) != NULL)
1179     {
1180       register int len = ep - bp;
1181 
1182       strncpy(buf, bp, len);
1183       buf[len] = '\0';
1184     }
1185   }
1186 
1187   return buf;
1188 }
1189 
1190 /*+F*************************************************************************
1191  * Function:
1192  *   aic7xxx_info
1193  *
1194  * Description:
1195  *   Return a string describing the driver.
1196  *-F*************************************************************************/
1197 const char *
1198 aic7xxx_info(struct Scsi_Host *notused)
     /*  */
1199 {
1200   static char buffer[128];
1201 
1202   strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1203   strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1204   strcat(buffer, "/");
1205   strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1206   strcat(buffer, "/");
1207   strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1208 
1209   return buffer;
1210 }
1211 
1212 /*+F*************************************************************************
1213  * Function:
1214  *   aic7xxx_putscb
1215  *
1216  * Description:
1217  *   Transfer a SCB to the controller.
1218  *-F*************************************************************************/
1219 static void
1220 aic7xxx_putscb(int base, struct aic7xxx_scb *scb)
     /*  */
1221 {
1222 #ifdef AIC7XXX_USE_DMA
1223   /*
1224    * All we need to do, is to output the position
1225    * of the SCB in the SCBARRAY to the QINFIFO
1226    * of the host adapter.
1227    */
1228   outb(scb->position, QINFIFO(base));
1229 #else
1230   /*
1231    * By turning on the SCB auto increment, any reference
1232    * to the SCB I/O space postincrements the SCB address
1233    * we're looking at. So turn this on and dump the relevant
1234    * portion of the SCB to the card.
1235    */
1236   outb(SCBAUTO, SCBCNT(base));
1237 
1238   asm volatile("cld\n\t"
1239                "rep\n\t"
1240                "outsb"
1241                : /* no output */
1242                :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1243                :"si", "cx", "dx");
1244 
1245   outb(0, SCBCNT(base));
1246 #endif
1247 }
1248 
1249 /*+F*************************************************************************
1250  * Function:
1251  *   aic7xxx_putdmascb
1252  *
1253  * Description:
1254  *   DMA a SCB to the controller.
1255  *-F*************************************************************************/
1256 static void
1257 aic7xxx_putdmascb(int base, struct aic7xxx_scb *scb)
     /*  */
1258 {
1259   /*
1260    * By turning on the SCB auto increment, any reference
1261    * to the SCB I/O space postincrements the SCB address
1262    * we're looking at. So turn this on and dump the relevant
1263    * portion of the SCB to the card.
1264    */
1265   outb(SCBAUTO, SCBCNT(base));
1266 
1267   asm volatile("cld\n\t"
1268                "rep\n\t"
1269                "outsb"
1270                : /* no output */
1271                :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1272                :"si", "cx", "dx");
1273 
1274   outb(0, SCBCNT(base));
1275 }
1276 
1277 /*+F*************************************************************************
1278  * Function:
1279  *   aic7xxx_getscb
1280  *
1281  * Description:
1282  *   Get a SCB from the controller.
1283  *-F*************************************************************************/
1284 static void
1285 aic7xxx_getscb(int base, struct aic7xxx_scb *scb)
     /*  */
1286 {
1287   /*
1288    * This is almost identical to aic7xxx_putscb().
1289    */
1290   outb(SCBAUTO, SCBCNT(base));
1291 
1292   asm volatile("cld\n\t"
1293                "rep\n\t"
1294                "insb"
1295                : /* no output */
1296                :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1297                :"di", "cx", "dx");
1298 
1299   outb(0, SCBCNT(base));
1300 }
1301 
1302 /*+F*************************************************************************
1303  * Function:
1304  *   aic7xxx_length
1305  *
1306  * Description:
1307  *   How much data should be transferred for this SCSI command? Stop
1308  *   at segment sg_last if it's a scatter-gather command so we can
1309  *   compute underflow easily.
1310  *-F*************************************************************************/
1311 static unsigned
1312 aic7xxx_length(Scsi_Cmnd *cmd, int sg_last)
     /*  */
1313 {
1314   int i, segments;
1315   unsigned length;
1316   struct scatterlist *sg;
1317 
1318   segments = cmd->use_sg - sg_last;
1319   sg = (struct scatterlist *) cmd->buffer;
1320 
1321   if (cmd->use_sg)
1322   {
1323     for (i = length = 0; i < cmd->use_sg && i < segments; i++)
1324     {
1325       length += sg[i].length;
1326     }
1327   }
1328   else
1329   {
1330     length = cmd->request_bufflen;
1331   }
1332 
1333   return(length);
1334 }
1335 
1336 /*+F*************************************************************************
1337  * Function:
1338  *   aic7xxx_scsirate
1339  *
1340  * Description:
1341  *   Look up the valid period to SCSIRATE conversion in our table
1342  *-F*************************************************************************/
1343 static void
1344 aic7xxx_scsirate(unsigned char *scsirate, unsigned char period,
     /*  */
1345                  unsigned char offset, int target)
1346 {
1347   int i;
1348 
1349   for (i = 0; i < num_aic7xxx_syncrates; i++)
1350   {
1351     if ((aic7xxx_syncrates[i].period - period) >= 0)
1352     {
1353       *scsirate = (aic7xxx_syncrates[i].rate << 4) | (offset & 0x0F);
1354       printk("aic7xxx: target %d now synchronous at %sMb/s, offset = 0x%x\n",
1355              target, aic7xxx_syncrates[i].english, offset);
1356       return;
1357     }
1358   }
1359 
1360   /*
1361    * Default to asyncronous transfer
1362    */
1363   *scsirate = 0;
1364   printk("aic7xxx: target %d using asynchronous transfers\n", target);
1365 }
1366 
1367 /*+F*************************************************************************
1368  * Function:
1369  *   aic7xxx_isr
1370  *
1371  * Description:
1372  *   SCSI controller interrupt handler.
1373  *
1374  *   NOTE: Since we declared this using SA_INTERRUPT, interrupts should
1375  *         be disabled all through this function unless we say otherwise.
1376  *-F*************************************************************************/
1377 static void
1378 aic7xxx_isr(int irq, struct pt_regs * regs)
     /*  */
1379 {
1380   int base, intstat;
1381   struct aic7xxx_host *p;
1382   struct aic7xxx_scb *scb;
1383   unsigned char active, ha_flags, transfer;
1384   unsigned char scsi_id, bus_width;
1385   unsigned char offset, rate, scratch;
1386   unsigned char max_offset;
1387   unsigned char head, tail;
1388   unsigned short target_mask;
1389   long flags;
1390   void *addr;
1391   int actual;
1392   int target, tcl;
1393   int scbptr;
1394   Scsi_Cmnd *cmd;
1395 #if 0
1396 static int_count = 0;
1397 #endif
1398 
1399   p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1400 #ifdef AIC7XXX_SHARE_IRQS
1401   /*
1402    * Search for the host with a pending interrupt.
1403    */
1404   while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
1405   {
1406     p = (struct aic7xxx_host *) p->next->hostdata;
1407   }
1408   if (p == NULL)
1409   {
1410     printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1411     return;
1412   }
1413 #endif
1414   base = p->base;
1415   if (p->isr_count == 0xffffffff)
1416   {
1417     p->isr_count = 0;
1418   }
1419   else
1420   {
1421     p->isr_count = p->isr_count + 1;
1422   }
1423   if ((p->a_scanned == 0) && (p->isr_count == 1))
1424   {
1425     /* Allow for one interrupt when the card is enabled. */
1426     return;
1427   }
1428 
1429   /*
1430    * Handle all the interrupt sources - especially for SCSI
1431    * interrupts, we won't get a second chance at them.
1432    */
1433   intstat = inb(INTSTAT(base));
1434 
1435   if (intstat & BRKADRINT)
1436   {
1437     int i;
1438     unsigned char errno = inb(ERROR(base));
1439 
1440     printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
1441     for (i = 0; i < NUMBER(hard_error); i++)
1442     {
1443       if (errno & hard_error[i].errno)
1444       {
1445         printk("  %s\n", hard_error[i].errmesg);
1446       }
1447     }
1448 
1449     panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
1450           inb(ERROR(base)),
1451           inb(SEQADDR1(base)) << 8 | inb(SEQADDR0(base)));
1452   }
1453 
1454   if (intstat & SEQINT)
1455   {
1456     /*
1457      * Although the sequencer is paused immediately on
1458      * a SEQINT, an interrupt for a SCSIINT or a CMDCMPLT
1459      * condition will have unpaused the sequencer before
1460      * this point.
1461      */
1462     PAUSE_SEQUENCER(p);
1463 
1464     switch (intstat & SEQINT_MASK)
1465     {
1466       case BAD_PHASE:
1467         panic("aic7xxx_isr: unknown scsi bus phase\n");
1468 
1469       case SEND_REJECT:
1470         debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
1471               inb(HA_REJBYTE(base)));
1472         break;
1473 
1474       case NO_IDENT:
1475         panic("aic7xxx_isr: reconnecting target %d at seqaddr 0x%x "
1476               "didn't issue IDENTIFY message\n",
1477               (inb(SELID(base)) >> 4) & 0x0F,
1478               (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
1479         break;
1480 
1481       case NO_MATCH:
1482         tcl = inb(SCBARRAY(base) + 1);
1483         target = (tcl >> 4) & 0x0F;
1484         /* Purposefully mask off the top bit of targets 8-15. */
1485         target_mask = 0x01 << (target & 0x07);
1486 
1487         debug("aic7xxx_isr: sequencer couldn't find match "
1488               "for reconnecting target %d, channel %d, lun %d - "
1489               "issuing ABORT\n", target, (tcl & 0x08) >> 3, tcl & 0x07);
1490         if (tcl & 0x88)
1491         {
1492           /* Second channel stores its info in byte
1493            * two of HA_ACTIVE
1494            */
1495           active = inb(HA_ACTIVE1(base));
1496           active = active & ~(target_mask);
1497           outb(active, HA_ACTIVE1(base));
1498         }
1499         else
1500         {
1501           active = inb(HA_ACTIVE0(base));
1502           active = active & ~(target_mask);
1503           outb(active, HA_ACTIVE0(base));
1504         }
1505 #ifdef AIC7XXX_USE_DMA
1506         outb(SCB_NEEDDMA, SCBARRAY(base));
1507 #endif
1508 
1509         /*
1510          * Check out why this use to be outb(0x80, CLRINT(base))
1511          * clear the timeout
1512          */
1513         outb(CLRSELTIMEO, CLRSINT1(base));
1514         RESTART_SEQUENCER(p);
1515         break;
1516 
1517       case MSG_SDTR:
1518         /*
1519          * Help the sequencer to translate the negotiated
1520          * transfer rate. Transfer is 1/4 the period
1521          * in ns as is returned by the sync negotiation
1522          * message. So, we must multiply by four.
1523          */
1524         transfer = (inb(HA_ARG_1(base)) << 2);
1525         offset = inb(ACCUM(base));
1526         scsi_id = inb(SCSIID(base)) >> 0x04;
1527         if (inb(SBLKCTL(base)) & 0x08)
1528         {
1529           scsi_id = scsi_id + 8;  /* B channel */
1530         }
1531         target_mask = (0x01 << scsi_id);
1532         scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1533         /*
1534          * The maximum offset for a wide device is 0x08; for a
1535          * 8-bit bus device the maximum offset is 0x0f.
1536          */
1537         if (scratch & 0x80)
1538         {
1539           max_offset = 0x08;
1540         }
1541         else
1542         {
1543           max_offset = 0x0f;
1544         }
1545         aic7xxx_scsirate(&rate, transfer, MIN(offset, max_offset), scsi_id);
1546         /*
1547          * Preserve the wide transfer flag.
1548          */
1549         rate = rate | (scratch & 0x80);
1550         outb(rate, HA_TARG_SCRATCH(base) + scsi_id);
1551         outb(rate, SCSIRATE(base));
1552         if ((rate & 0xf) == 0)
1553         { /*
1554            * The requested rate was so low that asynchronous transfers
1555            * are faster (not to mention the controller won't support
1556            * them), so we issue a reject to ensure we go to asynchronous
1557            * transfers.
1558            */
1559            outb(SEND_REJ, HA_RETURN_1(base));
1560         }
1561         else
1562         {
1563           /*
1564            * See if we initiated Sync Negotiation
1565            */
1566           if (p->sdtr_pending & target_mask)
1567           {
1568             /*
1569              * Don't send an SDTR back to the target.
1570              */
1571             outb(0, HA_RETURN_1(base));
1572           }
1573           else
1574           {
1575             /*
1576              * Send our own SDTR in reply.
1577              */
1578             printk("Sending SDTR!!\n");
1579             outb(SEND_SDTR, HA_RETURN_1(base));
1580           }
1581         }
1582         /*
1583          * Clear the flags.
1584          */
1585         p->needsdtr = p->needsdtr & ~target_mask;
1586         p->sdtr_pending = p->sdtr_pending & ~target_mask;
1587         break;
1588 
1589       case MSG_WDTR:
1590       {
1591         bus_width = inb(ACCUM(base));
1592         scsi_id = inb(SCSIID(base)) >> 0x04;
1593         if (inb(SBLKCTL(base)) & 0x08)
1594         {
1595           scsi_id = scsi_id + 8;  /* B channel */
1596         }
1597         printk("Received MSG_WDTR, scsi_id = %d, "
1598                "needwdtr = 0x%x\n", scsi_id, p->needwdtr);
1599         scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1600 
1601         target_mask = (0x01 << scsi_id);
1602         if (p->wdtr_pending & target_mask)
1603         {
1604           /*
1605            * Don't send an WDTR back to the target, since we asked first.
1606            */
1607           outb(0, HA_RETURN_1(base));
1608           switch (bus_width)
1609           {
1610             case BUS_8_BIT:
1611               scratch = scratch & 0x7F;
1612               break;
1613 
1614             case BUS_16_BIT:
1615               printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1616                      scsi_id);
1617               scratch = scratch | 0x80;
1618               break;
1619           }
1620         }
1621         else
1622         {
1623           /*
1624            * Send our own WDTR in reply.
1625            */
1626           printk("Will send WDTR!!\n");
1627           switch (bus_width)
1628           {
1629             case BUS_8_BIT:
1630               scratch = scratch & 0x7F;
1631               break;
1632 
1633             case BUS_32_BIT:
1634               /* Negotiate 16 bits. */
1635               bus_width = BUS_16_BIT;
1636               /* Yes, we mean to fall thru here */
1637 
1638             case BUS_16_BIT:
1639               printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1640                      scsi_id);
1641               scratch = scratch | 0x80;
1642               break;
1643           }
1644           outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
1645         }
1646         p->needwdtr = p->needwdtr & ~target_mask;
1647         p->wdtr_pending = p->wdtr_pending & ~target_mask;
1648         outb(scratch, HA_TARG_SCRATCH(base) + scsi_id);
1649         outb(scratch, SCSIRATE(base));
1650         break;
1651       }
1652 
1653       case MSG_REJECT:
1654       {
1655         /*
1656          * What we care about here is if we had an
1657          * outstanding SDTR or WDTR message for this
1658          * target. If we did, this is a signal that
1659          * the target is refusing negotiation.
1660          */
1661 
1662         unsigned char targ_scratch, scsi_id;
1663         unsigned short mask;
1664 
1665         scsi_id = inb(SCSIID(base)) >> 0x04;
1666         if (inb(SBLKCTL(base)) & 0x08)
1667         {
1668           scsi_id = scsi_id + 8;
1669         }
1670 
1671         mask = (0x01 << scsi_id);
1672 
1673         targ_scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1674 
1675         if (p->wdtr_pending & mask)
1676         {
1677           /*
1678            * note 8bit xfers and clear flag
1679            */
1680           targ_scratch = targ_scratch & 0x7F;
1681           p->needwdtr = p->needwdtr & ~mask;
1682           p->wdtr_pending = p->wdtr_pending & ~mask;
1683           outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1684           printk("aic7xxx: target %d refusing WIDE negotiation. Using "
1685                  "8 bit transfers\n", scsi_id);
1686         }
1687         else
1688         {
1689           if (p->sdtr_pending & mask)
1690           {
1691             /*
1692              * note asynch xfers and clear flag
1693              */
1694             targ_scratch = targ_scratch & 0xF0;
1695             p->needsdtr = p->needsdtr & ~mask;
1696             p->sdtr_pending = p->sdtr_pending & ~mask;
1697             outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1698             printk("aic7xxx: target %d refusing syncronous negotiation. Using "
1699                    "asyncronous transfers\n", scsi_id);
1700           }
1701           /*
1702            * Otherwise, we ignore it.
1703            */
1704         }
1705         outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1706         outb(targ_scratch, SCSIRATE(base));
1707         break;
1708       }
1709 
1710       case BAD_STATUS:
1711         scsi_id = inb(SCSIID(base)) >> 0x04;
1712         scbptr = inb(SCBPTR(base));
1713         scb = &(p->scb_array[scbptr]);
1714         outb(0, HA_RETURN_1(base));   /* CHECK_CONDITION may change this */
1715         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1716         {
1717           printk("aic7xxx_isr: referenced scb not valid "
1718                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1719                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1720         }
1721         else
1722         {
1723           cmd = scb->cmd;
1724           aic7xxx_getscb(base, scb);
1725           aic7xxx_status(cmd) = scb->target_status;
1726 
1727           cmd->result = cmd->result | scb->target_status;
1728 
1729           /*
1730            * This test is just here for debugging purposes.
1731            * It will go away when the timeout problem is resolved.
1732            */
1733           switch (status_byte(scb->target_status))
1734           {
1735             case GOOD:
1736               break;
1737 
1738             case CHECK_CONDITION:
1739               if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
1740               {
1741                 void         *req_buf;
1742 #ifndef AIC7XXX_USE_SG
1743                 unsigned int  req_buflen;
1744 #endif
1745 
1746                 /* Update the timeout for the SCSI command. */
1747 /*                update_timeout(cmd, SENSE_TIMEOUT); */
1748 
1749                 /* Send a sense command to the requesting target. */
1750                 cmd->flags = cmd->flags | WAS_SENSE;
1751                 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
1752                        sizeof(generic_sense));
1753 
1754                 scb->sense_cmd[1] = cmd->lun << 5;
1755                 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
1756 
1757 #ifdef AIC7XXX_USE_SG
1758                 scb->sense_sg.address = (char *) &cmd->sense_buffer;
1759                 scb->sense_sg.length = sizeof(cmd->sense_buffer);
1760                 req_buf = &scb->sense_sg;
1761 #else
1762                 req_buf = &cmd->sense_buffer;
1763                 req_buflen = sizeof(cmd->sense_buffer);
1764 #endif
1765                 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
1766                 memset(scb, 0, SCB_DOWNLOAD_SIZE);
1767                 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
1768                     ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
1769                 addr = scb->sense_cmd;
1770                 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
1771                 memcpy(scb->SCSI_cmd_pointer, &addr,
1772                        sizeof(scb->SCSI_cmd_pointer));
1773 #ifdef AIC7XXX_USE_SG
1774                 scb->SG_segment_count = 1;
1775                 memcpy (scb->SG_list_pointer, &req_buf,
1776                         sizeof(scb->SG_list_pointer));
1777 #else
1778                 scb->SG_segment_count = 0;
1779                 memcpy (scb->data_pointer, &req_buf,
1780                         sizeof(scb->data_pointer));
1781                 memcpy (scb->data_count, &req_buflen, 3);
1782 #endif
1783 
1784                 outb(SCBAUTO, SCBCNT(base));
1785                 asm volatile("cld\n\t"
1786                              "rep\n\t"
1787                              "outsb"
1788                              : /* no output */
1789                              :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1790                              :"si", "cx", "dx");
1791                 outb(0, SCBCNT(base));
1792                 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
1793 
1794                 /*
1795                  * Add this SCB to the "waiting for selection" list.
1796                  */
1797                 head = inb(WAITING_SCBH(base));
1798                 tail = inb(WAITING_SCBT(base));
1799                 if (head & SCB_LIST_NULL)
1800                 { /* list is empty */
1801                   head = scb->position;
1802                   tail = SCB_LIST_NULL;
1803                 }
1804                 else
1805                 {
1806                   if (tail & SCB_LIST_NULL)
1807                   { /* list has one element */
1808                     tail = scb->position;
1809                     outb(head, SCBPTR(base));
1810                     outb(tail, (SCBARRAY(base) + 30));
1811                   }
1812                   else
1813                   { /* list has more than one element */
1814                     outb(tail, SCBPTR(base));
1815                     tail = scb->position;
1816                     outb(tail, (SCBARRAY(base) + 30));
1817                   }
1818                 }
1819                 outb(head, WAITING_SCBH(base));
1820                 outb(tail, WAITING_SCBT(base));
1821                 outb(SEND_SENSE, HA_RETURN_1(base));
1822               }  /* first time sense, no errors */
1823               else
1824               {
1825                 /*
1826                  * Indicate that we asked for sense, have the sequencer do
1827                  * a normal command complete, and have the scsi driver handle
1828                  * this condition.
1829                  */
1830                 cmd->flags = cmd->flags | ASKED_FOR_SENSE;
1831               }
1832               break;
1833 
1834             case BUSY:
1835               printk("aic7xxx_isr: Target busy\n");
1836               if (!aic7xxx_error(cmd))
1837               {
1838                 aic7xxx_error(cmd) = DID_BUS_BUSY;
1839               }
1840               break;
1841 
1842             case QUEUE_FULL:
1843               printk("aic7xxx_isr: Queue full\n");
1844               if (!aic7xxx_error(cmd))
1845               {
1846                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1847               }
1848               break;
1849 
1850             default:
1851               printk("aic7xxx_isr: Unexpected target status 0x%x\n",
1852                      scb->target_status);
1853               if (!aic7xxx_error(cmd))
1854               {
1855                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1856               }
1857               break;
1858           }  /* end switch */
1859         }  /* end else of */
1860         break;
1861 
1862       case RESIDUAL:
1863         scbptr = inb(SCBPTR(base));
1864         scb = &(p->scb_array[scbptr]);
1865         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1866         {
1867           printk("aic7xxx_isr: referenced scb not valid "
1868                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1869                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1870         }
1871         else
1872         {
1873           cmd = scb->cmd;
1874           /*
1875            *  Don't destroy valid residual information with
1876            *  residual coming from a check sense operation.
1877            */
1878           if (!(cmd->flags & WAS_SENSE))
1879           {
1880             /*
1881              *  We had an underflow. At this time, there's only
1882              *  one other driver that bothers to check for this,
1883              *  and cmd->underflow seems to be set rather half-
1884              *  heartedly in the higher-level SCSI code.
1885              */
1886             actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
1887 
1888             actual -= ((inb(SCBARRAY(base + 17)) << 16) |
1889                        (inb(SCBARRAY(base + 16)) <<  8) |
1890                        inb(SCBARRAY(base + 15)));
1891 
1892             if (actual < cmd->underflow)
1893             {
1894               printk("aic7xxx: target %d underflow - "
1895                      "wanted (at least) %u, got %u\n",
1896                      cmd->target, cmd->underflow, actual);
1897 
1898               aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1899               aic7xxx_status(cmd) = scb->target_status;
1900             }
1901           }
1902         }
1903         break;
1904 
1905       case ABORT_TAG:
1906         scbptr = inb(SCBPTR(base));
1907         scb = &(p->scb_array[scbptr]);
1908         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1909         {
1910           printk("aic7xxx_isr: referenced scb not valid "
1911                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1912                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1913         }
1914         else
1915         {
1916           cmd = scb->cmd;
1917           /*
1918            * We didn't recieve a valid tag back from the target
1919            * on a reconnect.
1920            */
1921           printk("aic7xxx_isr: invalid tag recieved on channel %c "
1922                  "target %d, lun %d -- sending ABORT_TAG\n",
1923                   (cmd->channel & 0x01) ? 'B':'A',
1924                   cmd->target, cmd->lun & 0x07);
1925           /*
1926            *  This is a critical section, since we don't want the
1927            *  queue routine mucking with the host data.
1928            */
1929           save_flags(flags);
1930           cli();
1931 
1932           /*
1933            *  Process the command after marking the scb as free
1934            *  and adding it to the free list.
1935            */
1936           scb->state = SCB_FREE;
1937           scb->cmd = NULL;
1938           scb->next = p->free_scb;      /* preserve next pointer */
1939           p->free_scb = scb;            /* add at head of list */
1940 
1941           restore_flags (flags);
1942           cmd->result = (DID_RETRY_COMMAND << 16);
1943           cmd->scsi_done(cmd);
1944         }
1945         break;
1946 
1947       case AWAITING_MSG:
1948         scbptr = inb(SCBPTR(base));
1949         scb = &(p->scb_array[scbptr]);
1950         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1951         {
1952           printk("aic7xxx_isr: referenced scb not valid "
1953                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1954                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1955         }
1956         else
1957         {
1958           /*
1959            * This SCB had a zero length command, informing the sequencer
1960            * that we wanted to send a special message to this target.
1961            * We only do this for BUS_DEVICE_RESET messages currently.
1962            */
1963            if (scb->state & SCB_DEVICE_RESET)
1964            {
1965              outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
1966              outb(1, HA_MSG_LEN(base));
1967            }
1968            else
1969            {
1970              panic ("aic7xxx_isr: AWAITING_SCB for an SCB that does "
1971                     "not have a waiting message");
1972            }
1973         }
1974         break;
1975 
1976       default:               /* unknown */
1977         debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
1978               intstat, inb(SCSISIGI(base)));
1979         break;
1980     }
1981     outb(CLRSEQINT, CLRINT(base));
1982     UNPAUSE_SEQUENCER(p);
1983   }
1984 
1985   if (intstat & SCSIINT)
1986   {
1987     int status = inb(SSTAT1(base));
1988 
1989     scbptr = inb(SCBPTR(base));
1990     scb = &p->scb_array[scbptr];
1991     if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1992     {
1993       printk("aic7xxx_isr: no command for scb (scsiint)\n");
1994       /*
1995        * Turn off the interrupt and set status
1996        * to zero, so that it falls through the
1997        * reset of the SCSIINT code.
1998        */
1999       outb(status, CLRSINT1(base));
2000       UNPAUSE_SEQUENCER(p);
2001       outb(CLRSCSIINT, CLRINT(base));
2002       status = 0;
2003       scb = NULL;
2004     }
2005     else
2006     {
2007       cmd = scb->cmd;
2008 
2009       /*
2010        * Only the SCSI Status 1 register has information
2011        * about exceptional conditions that we'd have a
2012        * SCSIINT about; anything in SSTAT0 will be handled
2013        * by the sequencer. Note that there can be multiple
2014        * bits set.
2015        */
2016       if (status & SELTO)
2017       {
2018         unsigned char target_mask = (1 << (cmd->target & 0x07));
2019         unsigned char waiting;
2020 
2021         /*
2022          * Hardware selection timer has expired. Turn
2023          * off SCSI selection sequence.
2024          */
2025         outb(ENRSELI, SCSISEQ(base));
2026         cmd->result = (DID_TIME_OUT << 16);
2027         /*
2028          * Clear an pending messages for the timed out
2029          * target and mark the target as free.
2030          */
2031         ha_flags = inb(HA_FLAGS(base));
2032         outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2033 
2034         if (scb->target_channel_lun & 0x88)
2035         {
2036           active = inb(HA_ACTIVE1(base));
2037           active = active & ~(target_mask);
2038           outb(active, HA_ACTIVE1(base));
2039         }
2040         else
2041         {
2042           active = inb(HA_ACTIVE0(base));
2043           active = active & ~(target_mask);
2044           outb(active, HA_ACTIVE0(base));
2045         }
2046 
2047 #ifdef AIC7XXX_USE_DMA
2048         outb(SCB_NEEDDMA, SCBARRAY(base));
2049 #endif
2050 
2051         /*
2052          * Shut off the offending interrupt sources, reset
2053          * the sequencer address to zero and unpause it,
2054          * then call the high-level SCSI completion routine.
2055          *
2056          * WARNING!  This is a magic sequence!  After many
2057          * hours of guesswork, turning off the SCSI interrupts
2058          * in CLRSINT? does NOT clear the SCSIINT bit in
2059          * INTSTAT. By writing to the (undocumented, unused
2060          * according to the AIC-7770 manual) third bit of
2061          * CLRINT, you can clear INTSTAT. But, if you do it
2062          * while the sequencer is paused, you get a BRKADRINT
2063          * with an Illegal Host Address status, so the
2064          * sequencer has to be restarted first.
2065          */
2066         outb(CLRSELTIMEO, CLRSINT1(base));
2067 
2068         outb(CLRSCSIINT, CLRINT(base));
2069 
2070         /* Shift the waiting for selection queue forward */
2071         waiting = inb(WAITING_SCBH(base));
2072         outb(waiting, SCBPTR(base));
2073         waiting = inb(SCBARRAY(base) + 30);
2074         outb(waiting, WAITING_SCBH(base));
2075 
2076         RESTART_SEQUENCER(p);
2077         /*
2078          * This is a critical section, since we don't want the
2079          * queue routine mucking with the host data.
2080          */
2081         save_flags(flags);
2082         cli();
2083 
2084         /*
2085          * Process the command after marking the scb as free
2086          * and adding it to the free list.
2087          */
2088         scb->state = SCB_FREE;
2089         scb->cmd = NULL;
2090         scb->next = p->free_scb;        /* preserve next pointer */
2091         p->free_scb = scb;              /* add at head of list */
2092 
2093         restore_flags(flags);
2094 
2095         cmd->scsi_done(cmd);
2096 #if 0
2097   printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2098          scb->position, scb->state, (unsigned int) scb->cmd);
2099 #endif
2100       }
2101       else
2102       {
2103         if (status & SCSIPERR)
2104         {
2105           /*
2106            * A parity error has occurred during a data
2107            * transfer phase. Flag it and continue.
2108            */
2109           printk("aic7xxx: parity error on target %d, "
2110                  "channel %d, lun %d\n",
2111                  cmd->target,
2112                  cmd->channel & 0x01,
2113                  cmd->lun & 0x07);
2114           aic7xxx_error(cmd) = DID_PARITY;
2115 
2116           /*
2117            * Clear interrupt and resume as above.
2118            */
2119           outb(CLRSCSIPERR, CLRSINT1(base));
2120           UNPAUSE_SEQUENCER(p);
2121 
2122           outb(CLRSCSIINT, CLRINT(base));
2123           scb = NULL;
2124         }
2125         else
2126         {
2127           if (! (status & BUSFREE))
2128           {
2129              /*
2130               * We don't know what's going on. Turn off the
2131               * interrupt source and try to continue.
2132               */
2133              printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2134              outb(status, CLRSINT1(base));
2135              UNPAUSE_SEQUENCER(p);
2136              outb(CLRSCSIINT, CLRINT(base));
2137              scb = NULL;
2138           }
2139         }
2140       }
2141     }  /* else */
2142   }
2143 
2144   if (intstat & CMDCMPLT)
2145   {
2146     int complete;
2147 
2148     /*
2149      * The sequencer will continue running when it
2150      * issues this interrupt. There may be >1 commands
2151      * finished, so loop until we've processed them all.
2152      */
2153     do {
2154       complete = inb(QOUTFIFO(base));
2155 
2156       scb = &(p->scb_array[complete]);
2157       if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2158       {
2159         printk("aic7xxx warning: "
2160                "no command for scb %d (cmdcmplt)\n"
2161                "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x\n",
2162                complete, inb(QOUTFIFO(base)),
2163                scb->state, (unsigned int) scb->cmd);
2164         outb(CLRCMDINT, CLRINT(base));
2165         continue;
2166       }
2167       cmd = scb->cmd;
2168 
2169       cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2170       if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2171       { /* Got sense information. */
2172         cmd->flags = cmd->flags & ASKED_FOR_SENSE;
2173       }
2174 #if 0
2175       printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2176              scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2177 #endif
2178       /*
2179        * This is a critical section, since we don't want the
2180        * queue routine mucking with the host data.
2181        */
2182       save_flags(flags);
2183       cli();
2184 
2185       scb->state = SCB_FREE;
2186       scb->next = p->free_scb;
2187       scb->cmd = NULL;
2188       p->free_scb = &(p->scb_array[scb->position]);
2189 
2190       restore_flags(flags);
2191 #if 0
2192   if (scb != &p->scb_array[scb->position])
2193   {
2194     printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
2195   }
2196   printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2197          scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2198 #endif
2199 
2200       cmd->scsi_done(cmd);
2201 
2202       /*
2203        * Clear interrupt status before checking
2204        * the output queue again. This eliminates
2205        * a race condition whereby a command could
2206        * complete between the queue poll and the
2207        * interrupt clearing, so notification of the
2208        * command being complete never made it back
2209        * up to the kernel.
2210        */
2211       outb(CLRCMDINT, CLRINT(base));
2212     } while (inb(QOUTCNT(base)));
2213   }
2214 }
2215 
2216 /*+F*************************************************************************
2217  * Function:
2218  *   aic7xxx_probe
2219  *
2220  * Description:
2221  *   Probing for EISA boards: it looks like the first two bytes
2222  *   are a manufacturer code - three characters, five bits each:
2223  *
2224  *               BYTE 0   BYTE 1   BYTE 2   BYTE 3
2225  *              ?1111122 22233333 PPPPPPPP RRRRRRRR
2226  *
2227  *   The characters are baselined off ASCII '@', so add that value
2228  *   to each to get the real ASCII code for it. The next two bytes
2229  *   appear to be a product and revision number, probably vendor-
2230  *   specific. This is what is being searched for at each port,
2231  *   and what should probably correspond to the ID= field in the
2232  *   ECU's .cfg file for the card - if your card is not detected,
2233  *   make sure your signature is listed in the array.
2234  *
2235  *   The fourth byte's lowest bit seems to be an enabled/disabled
2236  *   flag (rest of the bits are reserved?).
2237  *-F*************************************************************************/
2238 static aha_type
2239 aic7xxx_probe(int slot, int base)
     /*  */
2240 {
2241   int i;
2242   unsigned char buf[4];
2243 
2244   static struct {
2245     int n;
2246     unsigned char signature[sizeof(buf)];
2247     aha_type type;
2248   } AIC7xxx[] = {
2249     { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x },  /* host adapter 274x */
2250     { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x },  /* motherboard 274x  */
2251     { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x },  /* 284x, BIOS enabled */
2252     { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x }   /* 284x, BIOS disabled */
2253   };
2254 
2255   /*
2256    * The VL-bus cards need to be primed by
2257    * writing before a signature check.
2258    */
2259   for (i = 0; i < sizeof(buf); i++)
2260   {
2261     outb(0x80 + i, base);
2262     buf[i] = inb(base + i);
2263   }
2264 
2265   for (i = 0; i < NUMBER(AIC7xxx); i++)
2266   {
2267     /*
2268      * Signature match on enabled card?
2269      */
2270     if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
2271     {
2272       if (inb(base + 4) & 1)
2273       {
2274         return(AIC7xxx[i].type);
2275       }
2276 
2277       printk("aic7xxx disabled at slot %d, ignored\n", slot);
2278     }
2279   }
2280 
2281   return(AIC_NONE);
2282 }
2283 
2284 /*+F*************************************************************************
2285  * Function:
2286  *   read_seeprom
2287  *
2288  * Description:
2289  *   Reads the serial EEPROM and returns 1 if successful and 0 if
2290  *   not successful.
2291  *
2292  *   The instruction set of the 93C46 chip is as follows:
2293  *
2294  *               Start  OP
2295  *     Function   Bit  Code  Address    Data     Description
2296  *     -------------------------------------------------------------------
2297  *     READ        1    10   A5 - A0             Reads data stored in memory,
2298  *                                               starting at specified address
2299  *     EWEN        1    00   11XXXX              Write enable must preceed
2300  *                                               all programming modes
2301  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
2302  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
2303  *     ERAL        1    00   10XXXX              Erase all registers
2304  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
2305  *     EWDS        1    00   00XXXX              Disables all programming
2306  *                                               instructions
2307  *     *Note: A value of X for address is a don't care condition.
2308  *
2309  *   The 93C46 has a four wire interface: clock, chip select, data in, and
2310  *   data out.  In order to perform one of the above functions, you need
2311  *   to enable the chip select for a clock period (typically a minimum of
2312  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
2313  *   respectively.  While the chip select remains high, you can clock in
2314  *   the instructions (above) starting with the start bit, followed by the
2315  *   OP code, Address, and Data (if needed).  For the READ instruction, the
2316  *   requested 16-bit register contents is read from the data out line but
2317  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
2318  *   first).  The clock cycling from low to high initiates the next data
2319  *   bit to be sent from the chip.
2320  *
2321  *   The 7870 interface to the 93C46 serial EEPROM is through the SEECTL
2322  *   register.  After successful arbitration for the memory port, the
2323  *   SEECS bit of the SEECTL register is connected to the chip select.
2324  *   The SEECK, SEEDO, and SEEDI are connected to the clock, data out,
2325  *   and data in lines respectively.  The SEERDY bit of SEECTL is useful
2326  *   in that it gives us an 800 nsec timer.  After a write to the SEECTL
2327  *   register, the SEERDY goes high 800 nsec later.  The one exception
2328  *   to this is when we first request access to the memory port.  The
2329  *   SEERDY goes high to signify that access has been granted and, for
2330  *   this case, has no implied timing.
2331  *
2332  *-F*************************************************************************/
2333 static int
2334 read_seeprom(int base, struct seeprom_config *sc)
     /*  */
2335 {
2336   int i = 0, k = 0;
2337   unsigned long timeout;
2338   unsigned char temp;
2339   unsigned short checksum = 0;
2340   unsigned short *seeprom = (unsigned short *) sc;
2341   struct seeprom_cmd {
2342     unsigned char len;
2343     unsigned char bits[3];
2344   };
2345   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
2346 
2347 #define CLOCK_PULSE(p) \
2348   while ((inb(SEECTL(base)) & SEERDY) == 0)     \
2349   {                                             \
2350     ;  /* Do nothing */                         \
2351   }
2352 
2353   /*
2354    * Request access of the memory port.  When access is
2355    * granted, SEERDY will go high.  We use a 1 second
2356    * timeout which should be near 1 second more than
2357    * is needed.  Reason: after the 7870 chip reset, there
2358    * should be no contention.
2359    */
2360   outb(SEEMS, SEECTL(base));
2361   timeout = jiffies + 100;  /* 1 second timeout */
2362   while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
2363   {
2364     ;  /* Do nothing!  Wait for access to be granted. */
2365   }
2366   if ((inb(SEECTL(base)) & SEERDY) == 0)
2367   {
2368     outb (0, SEECTL(base));
2369     return (0);
2370   }
2371 
2372   /*
2373    * Read the first 32 registers of the seeprom.  For the 7870,
2374    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
2375    * but only the first 32 are used by Adaptec BIOS.  The loop
2376    * will range from 0 to 31.
2377    */
2378   for (k = 0; k < (sizeof(*sc) / 2); k = k + 1)
2379   {
2380     /* Send chip select for one clock cycle. */
2381     outb(SEEMS | SEECK | SEECS, SEECTL(base));
2382     CLOCK_PULSE(base);
2383 
2384     /*
2385      * Now we're ready to send the read command followed by the
2386      * address of the 16-bit register we want to read.
2387      */
2388     for (i = 0; i < seeprom_read.len; i = i + 1)
2389     {
2390       temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
2391       outb(temp, SEECTL(base));
2392       CLOCK_PULSE(base);
2393       temp = temp ^ SEECK;
2394       outb(temp, SEECTL(base));
2395       CLOCK_PULSE(base);
2396     }
2397     /* Send the 6 bit address (MSB first, LSB last). */
2398     for (i = 5; i >= 0; i = i - 1)
2399     {
2400       temp = k;
2401       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
2402       temp = SEEMS | SEECS | (temp << 1);
2403       outb(temp, SEECTL(base));
2404       CLOCK_PULSE(base);
2405       temp = temp ^ SEECK;
2406       outb(temp, SEECTL(base));
2407       CLOCK_PULSE(base);
2408     }
2409 
2410     /*
2411      * Now read the 16 bit register.  An initial 0 precedes the
2412      * register contents which begins with bit 15 (MSB) and ends
2413      * with bit 0 (LSB).  The initial 0 will be shifted off the
2414      * top of our word as we let the loop run from 0 to 16.
2415      */
2416     for (i = 0; i <= 16; i = i + 1)
2417     {
2418       temp = SEEMS | SEECS;
2419       outb(temp, SEECTL(base));
2420       CLOCK_PULSE(base);
2421       temp = temp ^ SEECK;
2422       seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
2423       outb(temp, SEECTL(base));
2424       CLOCK_PULSE(base);
2425     }
2426 
2427     /*
2428      * The serial EEPROM has a checksum in the last word.  Keep a
2429      * running checksum for all words read except for the last
2430      * word.  We'll verify the checksum after all words have been
2431      * read.
2432      */
2433     if (k < (sizeof(*sc) / 2) - 1)
2434     {
2435       checksum = checksum + seeprom[k];
2436     }
2437 
2438     /* Reset the chip select for the next command cycle. */
2439     outb(SEEMS, SEECTL(base));
2440     CLOCK_PULSE(base);
2441     outb(SEEMS | SEECK, SEECTL(base));
2442     CLOCK_PULSE(base);
2443     outb(SEEMS, SEECTL(base));
2444     CLOCK_PULSE(base);
2445   }
2446 
2447   if (checksum != sc->checksum)
2448   {
2449     printk ("aic7xxx : SEEPROM checksum error, ignoring SEEPROM settings.\n");
2450     return (0);
2451   }
2452 
2453 #if 0
2454   printk ("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
2455   printk ("Serial EEPROM:");
2456   for (k = 0; k < (sizeof(*sc) / 2); k = k + 1)
2457   {
2458     if (((k % 8) == 0) && (k != 0))
2459     {
2460       printk ("\n              ");
2461     }
2462     printk (" 0x%x", seeprom[k]);
2463   }
2464   printk ("\n");
2465 #endif
2466 
2467   /* Release access to the memory port and the serial EEPROM. */
2468   outb(0, SEECTL(base));
2469   return (1);
2470 }
2471 
2472 /*+F*************************************************************************
2473  * Function:
2474  *   detect_maxscb
2475  *
2476  * Description:
2477  *   Return the maximum number of SCB's allowed for a given controller.
2478  *-F*************************************************************************/
2479 static int
2480 detect_maxscb(aha_type type, int base)
     /*  */
2481 {
2482   unsigned char sblkctl_reg;
2483   int maxscb = 0;
2484 
2485   switch (type)
2486   {
2487     case AIC_274x:
2488     case AIC_284x:
2489       /*
2490        * Check for Rev C or E boards. Rev E boards can supposedly have
2491        * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.
2492        * Until we know how to access more than 4 SCBs for the Rev E chips,
2493        * we limit them, along with the Rev C chips, to 4 SCBs.
2494        *
2495        * The Rev E boards have a read/write autoflush bit in the
2496        * SBLKCTL registor, while in the Rev C boards it is read only.
2497        */
2498       sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
2499       outb(sblkctl_reg, SBLKCTL(base));
2500       if (inb(SBLKCTL(base)) == sblkctl_reg)
2501       {  /* We detected a Rev E board. */
2502         printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
2503         outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
2504         maxscb = 4;
2505       }
2506       else
2507       {
2508         printk("aic7770: Rev C and previous; using 4 SCB's\n");
2509         maxscb = 4;
2510       }
2511       break;
2512 
2513     case AIC_7850:
2514       maxscb = 3;
2515       break;
2516 
2517     case AIC_7870:
2518       maxscb = 16;
2519       break;
2520 
2521     case AIC_7872:
2522       /*
2523        * Really has 255, but we'll wait to verify that we access
2524        * them the same way and do not have to set the card to
2525        * use the memory port to access external SCB RAM.
2526        */
2527       maxscb = 16;
2528       break;
2529 
2530     case AIC_NONE:
2531       /*
2532        * This should never happen... But just in case.
2533        */
2534       break;
2535   }
2536 
2537   return(maxscb);
2538 }
2539 
2540 /*+F*************************************************************************
2541  * Function:
2542  *   aic7xxx_register
2543  *
2544  * Description:
2545  *   Register a Adaptec aic7xxx chip SCSI controller with the kernel.
2546  *-F*************************************************************************/
2547 static int
2548 aic7xxx_register(Scsi_Host_Template *template, aha_type type,
     /*  */
2549                  int base, unsigned char irq)
2550 {
2551   static char * board_name[] = {"", "274x", "284x", "7870", "7850", "7872"};
2552   int i;
2553   unsigned char sblkctl;
2554   int max_targets;
2555   int found = 1;
2556   unsigned char target_settings;
2557   unsigned char scsi_conf;
2558   int have_seeprom = 0;
2559   struct Scsi_Host *host;
2560   struct aic7xxx_host *p;
2561   struct aic7xxx_host_config config;
2562   struct seeprom_config sc;
2563 
2564   config.type = type;
2565   config.base = base;
2566   config.irq = irq;
2567   config.parity = AIC_UNKNOWN;
2568   config.low_term = AIC_UNKNOWN;
2569   config.high_term = AIC_UNKNOWN;
2570   config.busrtime = 0;
2571 
2572   /*
2573    * Lock out other contenders for our i/o space.
2574    */
2575   request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
2576 
2577   switch (type)
2578   {
2579     case AIC_274x:
2580 #if 1
2581       printk("aha274x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2582 #endif
2583       /*
2584        * For some 274x boards, we must clear the CHIPRST bit
2585        * and pause the sequencer. For some reason, this makes
2586        * the driver work. For 284x boards, we give it a
2587        * CHIPRST just like the 294x boards.
2588        *
2589        * Use the BIOS settings to determine the interrupt
2590        * trigger type (level or edge) and use this value
2591        * for pausing and unpausing the sequencer.
2592        */
2593       config.unpause = (inb(HCNTRL(config.base)) & IRQMS) | INTEN;
2594       config.pause = config.unpause | PAUSE;
2595       config.extended = aic7xxx_extended;
2596 
2597       /*
2598        * I don't think we need to kick the reset again, the initial probe
2599        * does a reset, it seems that this is kicking a dead horse here.
2600        * So... I will try to just verify that the chip has come out of the
2601        * reset state and continue the same as the 284x.
2602        * In the Calgary version of the driver:
2603        *   1) Chip Reset
2604        *   2) Set unpause to IRQMS | INTEN
2605        *   3) If an interrupt occured without any commands queued, the
2606        *      unpause was set to just INTEN
2607        * I changed the initial reset code to just mask in the CHIPRST bit
2608        * and try to leave the other settings alone.
2609        *
2610        * I don't think we need the warning about chip reset not being clear.
2611        * On both my test machines (2842 & 2940), they work just fine with a
2612        * HCNTRL() of 0x5 (PAUSE | CHIPRST). Notice though, the 274x also
2613        * adds the INTEN flag, where neither the 284x or 294x do.
2614        */
2615       outb(config.pause | CHIPRST, HCNTRL(config.base));
2616       aic7xxx_delay(1);
2617       if (inb(HCNTRL(config.base)) & CHIPRST)
2618       {
2619         printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
2620       }
2621       outb(config.pause, HCNTRL(config.base));
2622 
2623       /*
2624        * Just to be on the safe side with the 274x, we will re-read the irq
2625        * since there was some issue about reseting the board.
2626        */
2627       config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2628       config.busrtime = inb(HA_SCSICONF(config.base)) & 0x3C;
2629 
2630       /*
2631        * A reminder until this can be detected automatically.
2632        */
2633       printk("aha274x: extended translation %sabled\n",
2634              config.extended ? "en" : "dis");
2635       break;
2636 
2637     case AIC_284x:
2638 #if 1
2639       printk("aha284x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2640 #endif
2641       outb(CHIPRST, HCNTRL(config.base));
2642       config.unpause = UNPAUSE_284X;
2643       config.pause = REQ_PAUSE; /* DWG would like to be like the rest */
2644       config.extended = aic7xxx_extended;
2645       config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2646 
2647       /*
2648        * A reminder until this can be detected automatically.
2649        */
2650       printk("aha284x: extended translation %sabled\n",
2651              config.extended ? "en" : "dis");
2652       break;
2653 
2654     case AIC_7850:
2655     case AIC_7870:
2656     case AIC_7872:
2657 #if 1
2658       printk("aic%s hcntrl=0x%x\n", board_name[type], inb(HCNTRL(config.base)));
2659 #endif
2660 
2661       outb(CHIPRST, HCNTRL(config.base));
2662       config.unpause = UNPAUSE_294X;
2663       config.pause = config.unpause | PAUSE;
2664       config.extended = aic7xxx_extended;
2665       config.scsi_id = 7;
2666 
2667       printk ("aic78xx: Reading SEEPROM... ");
2668       have_seeprom = read_seeprom(base, &sc);
2669       if (! have_seeprom)
2670       {
2671         printk ("Unable to read SEEPROM\n");
2672       }
2673       else
2674       {
2675         printk ("done\n");
2676         config.extended = (sc.bios_control & CFEXTEND) >> 7;
2677         config.scsi_id = (sc.brtime_id & CFSCSIID);
2678         config.parity = (sc.adapter_control & CFSPARITY) ?
2679                          AIC_ENABLED : AIC_DISABLED;
2680         config.low_term = (sc.adapter_control & CFSTERM) ?
2681                               AIC_ENABLED : AIC_DISABLED;
2682         config.high_term = (sc.adapter_control & CFWSTERM) ?
2683                               AIC_ENABLED : AIC_DISABLED;
2684         config.busrtime = (sc.brtime_id & CFBRTIME) >> 8;
2685       }
2686 
2687       /*
2688        * XXX - force data fifo threshold to 100%. Why does this
2689        *       need to be done?
2690        */
2691       outb(inb(DSPCISTATUS(config.base)) | DFTHRESH, DSPCISTATUS(config.base));
2692       outb(config.scsi_id | DFTHRESH, HA_SCSICONF(config.base));
2693 
2694       /*
2695        * In case we are a wide card, place scsi ID in second conf byte.
2696        */
2697       outb(config.scsi_id, (HA_SCSICONF(config.base) + 1));
2698 
2699       /*
2700        * A reminder until this can be detected automatically.
2701        */
2702       printk("aic%s: extended translation %sabled\n", board_name[type],
2703              config.extended ? "en" : "dis");
2704       break;
2705 
2706     default:
2707       panic("aic7xxx_register: internal error\n");
2708   }
2709 
2710   config.maxscb = detect_maxscb(type, base);
2711 
2712   if ((config.type == AIC_274x) || (config.type == AIC_284x))
2713   {
2714     if (config.pause & IRQMS)
2715     {
2716       printk("aic7xxx: Using Level Sensitive Interrupts\n");
2717     }
2718     else
2719     {
2720       printk("aic7xxx: Using Edge Triggered Interrupts\n");
2721     }
2722   }
2723 
2724   /*
2725    * Read the bus type from the SBLKCTL register. Set the FLAGS
2726    * register in the sequencer for twin and wide bus cards.
2727    */
2728   sblkctl = inb(SBLKCTL(base)) & 0x0F;  /* mask out upper two bits */
2729   switch (sblkctl)
2730   {
2731     case 0:     /* narrow/normal bus */
2732       config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2733       config.bus_type = AIC_SINGLE;
2734       outb(0, HA_FLAGS(base));
2735       break;
2736 
2737     case 2:     /* Wide bus */
2738       config.scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
2739       config.bus_type = AIC_WIDE;
2740       printk("aic7xxx : Enabling wide channel of %s-Wide\n",
2741              board_name[config.type]);
2742       outb(WIDE_BUS, HA_FLAGS(base));
2743       break;
2744 
2745     case 8:     /* Twin bus */
2746       config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2747 #ifdef AIC7XXX_TWIN_SUPPORT
2748       config.scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
2749       config.bus_type = AIC_TWIN;
2750       printk("aic7xxx : Enabled channel B of %s-Twin\n",
2751              board_name[config.type]);
2752       outb(TWIN_BUS, HA_FLAGS(base));
2753 #else
2754       config.bus_type = AIC_SINGLE;
2755       printk("aic7xxx : Channel B of %s-Twin will be ignored\n",
2756              board_name[config.type]);
2757       outb(0, HA_FLAGS(base));
2758 #endif
2759       break;
2760 
2761     default:
2762       printk("aic7xxx is an unsupported type 0x%x, please "
2763              "mail deang@ims.com\n", inb(SBLKCTL(base)));
2764       outb(0, HA_FLAGS(base));
2765       return(0);
2766   }
2767 
2768   /*
2769    * Clear the upper two bits. For the 294x cards, clearing the
2770    * upper two bits, will take the card out of diagnostic mode
2771    * and make the host adatper LED follow bus activity (will not
2772    * always be on).
2773    */
2774   outb(sblkctl, SBLKCTL(base));
2775 
2776   /*
2777    * The IRQ level in i/o port 4 maps directly onto the real
2778    * IRQ number. If it's ok, register it with the kernel.
2779    *
2780    * NB. the Adaptec documentation says the IRQ number is only
2781    *     in the lower four bits; the ECU information shows the
2782    *     high bit being used as well. Which is correct?
2783    *
2784    * The 294x cards (PCI) get their interrupt from PCI BIOS.
2785    */
2786   if (((config.type == AIC_274x) || (config.type == AIC_284x))
2787       && (config.irq < 9 || config.irq > 15))
2788   {
2789     printk("aic7xxx uses unsupported IRQ level, ignoring\n");
2790     return(0);
2791   }
2792 
2793   /*
2794    * Check the IRQ to see if it is shared by another aic7xxx
2795    * controller. If it is and sharing of IRQs is not defined,
2796    * then return 0 hosts found. If sharing of IRQs is allowed
2797    * or the IRQ is not shared by another host adapter, then
2798    * proceed.
2799    */
2800 #ifndef AIC7XXX_SHARE_IRQS
2801    if (aic7xxx_boards[config.irq] != NULL)
2802    {
2803      printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
2804      return(0);
2805    }
2806 #endif
2807 
2808   /*
2809    * Print out debugging information before re-enabling
2810    * the card - a lot of registers on it can't be read
2811    * when the sequencer is active.
2812    */
2813   debug_config(&config);
2814 
2815   /*
2816    * Before registry, make sure that the offsets of the
2817    * struct scatterlist are what the sequencer will expect,
2818    * otherwise disable scatter-gather altogether until someone
2819    * can fix it. This is important since the sequencer will
2820    * DMA elements of the SG array in while executing commands.
2821    */
2822   if (template->sg_tablesize != SG_NONE)
2823   {
2824     struct scatterlist sg;
2825 
2826     if (SG_STRUCT_CHECK(sg))
2827     {
2828       printk("aic7xxx warning: kernel scatter-gather "
2829              "structures changed, disabling it\n");
2830       template->sg_tablesize = SG_NONE;
2831     }
2832   }
2833 
2834   /*
2835    * Register each "host" and fill in the returned Scsi_Host
2836    * structure as best we can. Some of the parameters aren't
2837    * really relevant for bus types beyond ISA, and none of the
2838    * high-level SCSI code looks at it anyway. Why are the fields
2839    * there? Also save the pointer so that we can find the
2840    * information when an IRQ is triggered.
2841    */
2842   host = scsi_register(template, sizeof(struct aic7xxx_host));
2843   host->can_queue = config.maxscb;
2844 #ifdef AIC7XXX_TAGGED_QUEUEING
2845   host->cmd_per_lun = 2;
2846 #else
2847   host->cmd_per_lun = 1;
2848 #endif
2849   host->this_id = config.scsi_id;
2850   host->irq = config.irq;
2851   if (config.bus_type == AIC_WIDE)
2852   {
2853     host->max_id = 16;
2854   }
2855   if (config.bus_type == AIC_TWIN)
2856   {
2857     host->max_channel = 1;
2858   }
2859 
2860   p = (struct aic7xxx_host *) host->hostdata;
2861 
2862   /* Initialize the scb array by setting the state to free. */
2863   for (i = 0; i < AIC7XXX_MAXSCB; i = i + 1)
2864   {
2865     p->scb_array[i].state = SCB_FREE;
2866     p->scb_array[i].next = NULL;
2867     p->scb_array[i].cmd = NULL;
2868   }
2869 
2870   p->isr_count = 0;
2871   p->a_scanned = 0;
2872   p->b_scanned = 0;
2873   p->base = config.base;
2874   p->maxscb = config.maxscb;
2875   p->numscb = 0;
2876   p->extended = config.extended;
2877   p->type = config.type;
2878   p->bus_type = config.bus_type;
2879   p->have_seeprom = have_seeprom;
2880   p->seeprom = sc;
2881   p->free_scb = NULL;
2882   p->next = NULL;
2883 
2884   p->unpause = config.unpause;
2885   p->pause = config.pause;
2886 
2887   if (aic7xxx_boards[config.irq] == NULL)
2888   {
2889     /*
2890      * Register IRQ with the kernel.
2891      */
2892     if (request_irq(config.irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
2893     {
2894       printk("aic7xxx couldn't register irq %d, ignoring\n", config.irq);
2895       return(0);
2896     }
2897     aic7xxx_boards[config.irq] = host;
2898   }
2899   else
2900   {
2901     /*
2902      * We have found a host adapter sharing an IRQ of a previously
2903      * registered host adapter. Add this host adapter's Scsi_Host
2904      * to the beginning of the linked list of hosts at the same IRQ.
2905      */
2906     p->next = aic7xxx_boards[config.irq];
2907     aic7xxx_boards[config.irq] = host;
2908   }
2909 
2910   /*
2911    * Load the sequencer program, then re-enable the board -
2912    * resetting the AIC-7770 disables it, leaving the lights
2913    * on with nobody home. On the PCI bus you *may* be home,
2914    * but then your mailing address is dynamically assigned
2915    * so no one can find you anyway :-)
2916    */
2917   printk("aic7xxx: Downloading sequencer code..");
2918   aic7xxx_loadseq(base);
2919 
2920   /* Set Fast Mode and Enable the board */
2921   outb(FASTMODE, SEQCTL(base));
2922 
2923   if ((p->type == AIC_274x || p->type == AIC_284x))
2924   {
2925     outb(ENABLE, BCTL(base));
2926   }
2927 
2928   printk("done.\n");
2929 
2930   /*
2931    * Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels
2932    */
2933   if (p->bus_type == AIC_TWIN)
2934   {
2935     /*
2936      * The device is gated to channel B after a chip reset,
2937      * so set those values first.
2938      */
2939     outb(config.scsi_id_b, SCSIID(base));
2940     scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
2941     scsi_conf = scsi_conf | ENSTIMER | ACTNEGEN | STPWEN;
2942     outb(scsi_conf, SXFRCTL1(base));
2943     outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
2944     /* Select Channel A */
2945     outb(0, SBLKCTL(base));
2946   }
2947   outb(config.scsi_id, SCSIID(base));
2948   scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
2949   outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
2950   outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
2951 
2952   /* Look at the information that board initialization or the board
2953    * BIOS has left us. In the lower four bits of each target's
2954    * scratch space any value other than 0 indicates that we should
2955    * initiate synchronous transfers. If it's zero, the user or the
2956    * BIOS has decided to disable synchronous negotiation to that
2957    * target so we don't activate the needsdtr flag.
2958    */
2959   p->needsdtr_copy = 0;
2960   p->sdtr_pending = 0;
2961   p->needwdtr_copy = 0;
2962   p->wdtr_pending = 0;
2963   if (p->bus_type == AIC_SINGLE)
2964   {
2965     max_targets = 8;
2966   }
2967   else
2968   {
2969     max_targets = 16;
2970   }
2971 
2972   for (i = 0; i < max_targets; i = i + 1)
2973   {
2974     if (have_seeprom)
2975     {
2976       target_settings = (sc.device_flags[i] & CFXFER) << 4;
2977       if (sc.device_flags[i] & CFSYNCH)
2978       {
2979         p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
2980       }
2981       if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
2982       {
2983         p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
2984       }
2985     }
2986     else
2987     {
2988       target_settings = inb(HA_TARG_SCRATCH(base) + i);
2989       if (target_settings & 0x0F)
2990       {
2991         p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
2992         /*
2993          * Default to asynchronous transfers (0 offset)
2994          */
2995         target_settings = target_settings & 0xF0;
2996       }
2997       /*
2998        * If we are not wide, forget WDTR. This makes the driver
2999        * work on some cards that don't leave these fields cleared
3000        * when BIOS is not installed.
3001        */
3002       if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
3003       {
3004         p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3005         target_settings = target_settings & 0x7F;
3006       }
3007     }
3008     outb(target_settings, (HA_TARG_SCRATCH(base) + i));
3009   }
3010 
3011   p->needsdtr = p->needsdtr_copy;
3012   p->needwdtr = p->needwdtr_copy;
3013   printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
3014   printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
3015 
3016   /* 
3017    * Clear the control byte for every SCB so that the sequencer
3018    * doesn't get confused and think that one of them is valid
3019    */
3020   for (i = 0; i < config.maxscb; i = i + 1)
3021   {
3022     outb(i, SCBPTR(base));
3023     outb(0, SCBARRAY(base));
3024   }
3025 
3026   /*
3027    * For reconnecting targets, the sequencer code needs to
3028    * know how many SCBs it has to search through.
3029    */
3030   outb(config.maxscb, HA_SCBCOUNT(base));
3031 
3032   /*
3033    * Clear the active flags - no targets are busy.
3034    */
3035   outb(0, HA_ACTIVE0(base));
3036   outb(0, HA_ACTIVE1(base));
3037 
3038   /* We don't have any waiting selections */
3039   outb (SCB_LIST_NULL, WAITING_SCBH(base));
3040   outb (SCB_LIST_NULL, WAITING_SCBT(base));
3041 
3042   /*
3043    * Reset the SCSI bus. Is this necessary?
3044    *   There may be problems for a warm boot without resetting
3045    *   the SCSI bus. Either BIOS settings in scratch RAM
3046    *   will not get reinitialized, or devices may stay at
3047    *   previous negotiated settings (SDTR and WDTR) while
3048    *   the driver will think that no negotiations have been
3049    *   performed.
3050    *
3051    * Some devices need a long time to "settle" after a SCSI
3052    * bus reset.
3053    */
3054 
3055   if (!aic7xxx_no_reset)
3056   {
3057     printk("Resetting the SCSI bus...\n");
3058     outb(SCSIRSTO, SCSISEQ(base));
3059     udelay(1000);
3060     outb(0, SCSISEQ(base));
3061     aic7xxx_delay(AIC7XXX_RESET_DELAY);
3062   }
3063 
3064   /*
3065    * Unpause the sequencer before returning and enable
3066    * interrupts - we shouldn't get any until the first
3067    * command is sent to us by the high-level SCSI code.
3068    */
3069   UNPAUSE_SEQUENCER(p);
3070   return(found);
3071 }
3072 
3073 /*+F*************************************************************************
3074  * Function:
3075  *   aic7xxx_detect
3076  *
3077  * Description:
3078  *   Try to detect and register an Adaptec 7770 or 7870 SCSI controller.
3079  *-F*************************************************************************/
3080 int
3081 aic7xxx_detect(Scsi_Host_Template *template)
     /*  */
3082 {
3083   aha_type type = AIC_NONE;
3084   int found = 0, slot, base;
3085   unsigned char irq = 0;
3086   int i;
3087 
3088   /*
3089    * Since we may allow sharing of IRQs, it is imperative
3090    * that we "null-out" the aic7xxx_boards array. It is
3091    * not guaranteed to be initialized to 0 (NULL). We use
3092    * a NULL entry to indicate that no prior hosts have
3093    * been found/registered for that IRQ.
3094    */
3095   for (i = 0; i <= MAXIRQ; i++)
3096   {
3097     aic7xxx_boards[i] = NULL;
3098   }
3099 
3100   /*
3101    * EISA/VL-bus card signature probe.
3102    */
3103   for (slot = MINSLOT; slot <= MAXSLOT; slot++)
3104   {
3105     base = SLOTBASE(slot);
3106 
3107     if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
3108     {
3109       /*
3110        * Some other driver has staked a
3111        * claim to this i/o region already.
3112        */
3113       continue;
3114     }
3115 
3116     type = aic7xxx_probe(slot, HID0(base));
3117     if (type != AIC_NONE)
3118     {
3119       printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3120 #if 0
3121       outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3122       irq = inb(HA_INTDEF(base)) & 0x0F;
3123 #endif
3124 
3125       /*
3126        * We "find" a AIC-7770 if we locate the card
3127        * signature and we can set it up and register
3128        * it with the kernel without incident.
3129        */
3130       found += aic7xxx_register(template, type, base, irq);
3131     }
3132   }
3133 
3134 #ifdef CONFIG_PCI
3135 
3136 #define DEVREVID  0x08
3137 #define DEVCONFIG 0x40
3138 #define DEVSTATUS 0x41
3139 #define RAMPSM    0x02
3140 
3141 /* This should be defined in pci.h */
3142 #define PCI_DEVICE_ID_ADAPTEC_7850      0x5078
3143 #define PCI_DEVICE_ID_ADAPTEC_7872      0x7278
3144 
3145   /*
3146    * PCI-bus probe.
3147    */
3148   if (pcibios_present())
3149   {
3150     int error;
3151     int done = 0;
3152     unsigned int io_port;
3153     unsigned short index = 0;
3154     unsigned char pci_bus, pci_device_fn;
3155     unsigned char devrevid, devconfig, devstatus;
3156     char rev_id[] = {'B', 'C', 'D'};
3157 
3158     while (!done)
3159     {
3160       if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3161                                 PCI_DEVICE_ID_ADAPTEC_294x,
3162                                 index, &pci_bus, &pci_device_fn)) ||
3163            (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3164                                 PCI_DEVICE_ID_ADAPTEC_2940,
3165                                 index, &pci_bus, &pci_device_fn)))
3166       {
3167         type = AIC_7870;
3168       }
3169       else
3170       {
3171         if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3172                                 PCI_DEVICE_ID_ADAPTEC_7850,
3173                                 index, &pci_bus, &pci_device_fn))
3174         {
3175           type = AIC_7850;
3176         }
3177         else
3178         {
3179           if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3180                                   PCI_DEVICE_ID_ADAPTEC_7872,
3181                                   index, &pci_bus, &pci_device_fn))
3182           {
3183             type = AIC_7872;
3184           }
3185           else
3186           {
3187             type = AIC_NONE;
3188             done = 1;
3189           }
3190         }
3191       }
3192 
3193       if (!done)
3194       {
3195         /*
3196          * Read esundry information from PCI BIOS.
3197          */
3198         error = pcibios_read_config_dword(pci_bus, pci_device_fn,
3199                                           PCI_BASE_ADDRESS_0, &io_port);
3200 
3201         if (error)
3202         {
3203           panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
3204         }
3205 
3206         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3207                                          PCI_INTERRUPT_LINE, &irq);
3208         if (error)
3209         {
3210           panic("aic7xxx_detect: error %d reading irq.\n", error);
3211         }
3212 
3213         /*
3214          * Make the base I/O register look like EISA and VL-bus.
3215          */
3216         base = io_port - 0xC01;
3217 
3218         printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3219         outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3220 
3221         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3222                                          DEVREVID, &devrevid);
3223         if (devrevid < 3)
3224         {
3225           printk ("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
3226         }
3227         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3228                                          DEVCONFIG, &devconfig);
3229         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3230                                          DEVSTATUS, &devstatus);
3231         printk ("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
3232                 devconfig, devstatus);
3233         if (devstatus & RAMPSM)
3234         {
3235           printk ("aic7xxx_detect: detected external SCB RAM, "
3236                   "mail deang@ims.com for test patch");
3237         }
3238 
3239         found += aic7xxx_register(template, type, base, irq);
3240         index += 1;
3241       }
3242     }
3243   }
3244 #endif CONFIG_PCI
3245 
3246   template->name = (char *) aic7xxx_info(NULL);
3247   return(found);
3248 }
3249 
3250 
3251 /*+F*************************************************************************
3252  * Function:
3253  *   aic7xxx_buildscb
3254  *
3255  * Description:
3256  *   Build a SCB.
3257  *-F*************************************************************************/
3258 static void
3259 aic7xxx_buildscb(struct aic7xxx_host *p,
     /*  */
3260                  Scsi_Cmnd *cmd,
3261                  struct aic7xxx_scb *scb)
3262 {
3263   void *addr;
3264   unsigned length;
3265   unsigned short mask;
3266 
3267   /*
3268    * Setup the control byte if we need negotiation and have not
3269    * already requested it.
3270    */
3271 #ifdef AIC7XXX_TAGGED_QUEUEING
3272   if (cmd->device->tagged_supported)
3273   {
3274     if (cmd->device->tagged_queue == 0)
3275     {
3276       printk ("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
3277               "channel %d\n", cmd->target, cmd->channel);
3278       cmd->device->tagged_queue = 1;
3279       cmd->device->current_tag = 1;  /* enable tagging */
3280     }
3281     cmd->tag = cmd->device->current_tag;
3282     cmd->device->current_tag = cmd->device->current_tag + 1;
3283     scb->control = scb->control | SCB_TE;
3284   }
3285 #endif
3286   mask = (0x01 << cmd->target);
3287   if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
3288   {
3289     p->wdtr_pending = p->wdtr_pending | mask;
3290     scb->control = scb->control | SCB_NEEDWDTR;
3291 #if 0
3292     printk("Sending WDTR request to target %d.\n", cmd->target);
3293 #endif
3294   }
3295   else
3296   {
3297     if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
3298     {
3299       p->sdtr_pending = p->sdtr_pending | mask;
3300       scb->control = scb->control | SCB_NEEDSDTR;
3301 #if 0
3302       printk("Sending SDTR request to target %d.\n", cmd->target);
3303 #endif
3304     }
3305   }
3306 
3307 #if 0
3308   printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
3309          cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
3310 #endif
3311   scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
3312         ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
3313 
3314   /*
3315    * The interpretation of request_buffer and request_bufflen
3316    * changes depending on whether or not use_sg is zero; a
3317    * non-zero use_sg indicates the number of elements in the
3318    * scatter-gather array.
3319    *
3320    * The AIC-7770 can't support transfers of any sort larger
3321    * than 2^24 (three-byte count) without backflips. For what
3322    * the kernel is doing, this shouldn't occur. I hope.
3323    */
3324   length = aic7xxx_length(cmd, 0);
3325 
3326   if (length > 0xFFFFFF)
3327   {
3328     panic("aic7xxx_buildscb: can't transfer > 2^24 - 1 bytes\n");
3329   }
3330 
3331   /*
3332    * XXX - this relies on the host data being stored in a
3333    *       little-endian format.
3334    */
3335   addr = cmd->cmnd;
3336   scb->SCSI_cmd_length = cmd->cmd_len;
3337   memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
3338 
3339   if (cmd->use_sg)
3340   {
3341 #if 0
3342     debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
3343           cmd->use_sg, length);
3344 #endif
3345     scb->SG_segment_count = cmd->use_sg;
3346     memcpy(scb->SG_list_pointer, &cmd->request_buffer,
3347            sizeof(scb->SG_list_pointer));
3348   }
3349   else
3350   {
3351 #if 0
3352     debug ("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
3353            (unsigned long) cmd->request_buffer, cmd->request_bufflen);
3354 #endif
3355 #ifdef AIC7XXX_USE_SG
3356     scb->SG_segment_count = 1;
3357     scb->sg.address = (char *) cmd->request_buffer;
3358     scb->sg.length = cmd->request_bufflen;
3359     addr = &scb->sg;
3360     memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
3361 #else
3362     scb->SG_segment_count = 0;
3363     memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
3364     memcpy(scb->data_count, &cmd->request_bufflen, 3);
3365 #endif
3366   }
3367 }
3368 
3369 /*+F*************************************************************************
3370  * Function:
3371  *   aic7xxx_queue
3372  *
3373  * Description:
3374  *   Queue a SCB to the controller.
3375  *-F*************************************************************************/
3376 int
3377 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
     /*  */
3378 {
3379   long flags;
3380 #ifndef AIC7XXX_USE_DMA
3381   int old_scbptr;
3382 #endif
3383   struct aic7xxx_host *p;
3384   struct aic7xxx_scb *scb;
3385   unsigned char curscb;
3386 
3387   p = (struct aic7xxx_host *) cmd->host->hostdata;
3388 
3389   /* Check to see if channel was scanned. */
3390  if (!p->a_scanned && (cmd->channel == 0))
3391   {
3392     printk("aic7xxx: Scanning channel A for devices.\n");
3393     p->a_scanned = 1;
3394   }
3395   else
3396   {
3397     if (!p->b_scanned && (cmd->channel == 1))
3398     {
3399       printk("aic7xxx: Scanning channel B for devices.\n");
3400       p->b_scanned = 1;
3401     }
3402   }
3403 
3404 #if 0
3405   debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
3406         cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
3407         cmd->lun & 0x07);
3408 #endif
3409 
3410   /*
3411    * This is a critical section, since we don't want the
3412    * interrupt routine mucking with the host data or the
3413    * card. Since the kernel documentation is vague on
3414    * whether or not we are in a cli/sti pair already, save
3415    * the flags to be on the safe side.
3416    */
3417   save_flags(flags);
3418   cli();
3419 
3420   /*
3421    * Find a free slot in the SCB array to load this command
3422    * into. Since can_queue is set to the maximum number of
3423    * SCBs for the card, we should always find one.
3424    *
3425    * First try to find an scb in the free list. If there are
3426    * none in the free list, then check the current number of
3427    * of scbs and take an unused one from the scb array.
3428    */
3429   scb = p->free_scb;
3430   if (scb != NULL)
3431   { /* found one in the free list */
3432     p->free_scb = scb->next;   /* remove and update head of list */
3433     /*
3434      * Warning! For some unknown reason, the scb at the head
3435      * of the free list is not the same address that it should
3436      * be. That's why we set the scb pointer taken by the
3437      * position in the array. The scb at the head of the list
3438      * should match this address, but it doesn't.
3439      */
3440     scb = &(p->scb_array[scb->position]);
3441     scb->control = 0;
3442     scb->state = SCB_ACTIVE;
3443   }
3444   else
3445   {
3446     if (p->numscb >= p->maxscb)
3447     {
3448       panic("aic7xxx_queue: couldn't find a free scb\n");
3449     }
3450     else
3451     {
3452       /*
3453        * Initialize the scb within the scb array. The
3454        * position within the array is the position on
3455        * the board that it will be loaded.
3456        */
3457       scb = &(p->scb_array[p->numscb]);
3458       memset(scb, 0, sizeof(*scb));
3459 
3460       scb->position = p->numscb;
3461       p->numscb = p->numscb + 1;
3462       scb->state = SCB_ACTIVE;
3463       scb->next_waiting = SCB_LIST_NULL;
3464       memcpy(scb->host_scb, &scb, sizeof(scb));
3465 #ifdef AIC7XXX_USE_DMA
3466       scb->control = SCB_NEEDDMA;
3467 #endif
3468       PAUSE_SEQUENCER(p);
3469       curscb = inb(SCBPTR(p->base));
3470       outb(scb->position, SCBPTR(p->base));
3471       aic7xxx_putdmascb(p->base, scb);
3472       outb(curscb, SCBPTR(p->base));
3473       UNPAUSE_SEQUENCER(p);
3474       scb->control = 0;
3475     }
3476   }
3477 
3478   scb->cmd = cmd;
3479   aic7xxx_position(cmd) = scb->position;
3480 
3481   /*
3482    * Construct the SCB beforehand, so the sequencer is
3483    * paused a minimal amount of time.
3484    */
3485   aic7xxx_buildscb(p, cmd, scb);
3486 
3487 #if 0
3488   if (scb != &p->scb_array[scb->position])
3489   {
3490     printk("aic7xxx_queue: address of scb by position does not match scb address\n");
3491   }
3492   printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
3493          scb->position, (unsigned int) scb->cmd,
3494          scb->state, (unsigned int) p->free_scb);
3495 #endif
3496   /*
3497    * Pause the sequencer so we can play with its registers -
3498    * wait for it to acknowledge the pause.
3499    *
3500    * XXX - should the interrupts be left on while doing this?
3501    */
3502   PAUSE_SEQUENCER(p);
3503 
3504   /*
3505    * Save the SCB pointer and put our own pointer in - this
3506    * selects one of the four banks of SCB registers. Load
3507    * the SCB, then write its pointer into the queue in FIFO
3508    * and restore the saved SCB pointer.
3509    */
3510 #ifdef AIC7XXX_USE_DMA
3511   aic7xxx_putscb(p->base, scb);
3512 #else
3513   old_scbptr = inb(SCBPTR(p->base));
3514   outb(scb->position, SCBPTR(p->base));
3515 
3516   aic7xxx_putscb(p->base, scb);
3517 
3518   outb(scb->position, QINFIFO(p->base));
3519   outb(old_scbptr, SCBPTR(p->base));
3520 #endif
3521   /*
3522    * Make sure the Scsi_Cmnd pointer is saved, the struct it
3523    * points to is set up properly, and the parity error flag
3524    * is reset, then unpause the sequencer and watch the fun
3525    * begin.
3526    */
3527   cmd->scsi_done = fn;
3528   aic7xxx_error(cmd) = DID_OK;
3529   aic7xxx_status(cmd) = 0;
3530 
3531   cmd->result = 0;
3532   memset (&cmd->sense_buffer, 0, sizeof (cmd->sense_buffer));
3533 
3534   UNPAUSE_SEQUENCER(p);
3535   restore_flags(flags);
3536   return(0);
3537 }
3538 
3539 /* return values from aic7xxx_kill */
3540 typedef enum {
3541   k_ok,             /* scb found and message sent */
3542   k_busy,           /* message already present */
3543   k_absent,         /* couldn't locate scb */
3544   k_disconnect,     /* scb found, but disconnected */
3545 } k_state;
3546 
3547 /*+F*************************************************************************
3548  * Function:
3549  *   aic7xxx_kill
3550  *
3551  * Description:
3552  *   This must be called with interrupts disabled - it's going to
3553  *   be messing around with the host data, and an interrupt being
3554  *   fielded in the middle could get ugly.
3555  *
3556  *   Since so much of the abort and reset code is shared, this
3557  *   function performs more magic than it really should. If the
3558  *   command completes ok, then it will call scsi_done with the
3559  *   result code passed in. The unpause parameter controls whether
3560  *   or not the sequencer gets unpaused - the reset function, for
3561  *   instance, may want to do something more aggressive.
3562  *
3563  *   Note that the command is checked for in our SCB_array first
3564  *   before the sequencer is paused, so if k_absent is returned,
3565  *   then the sequencer is NOT paused.
3566  *-F*************************************************************************/
3567 static k_state
3568 aic7xxx_kill(Scsi_Cmnd *cmd, unsigned char message,
     /*  */
3569              unsigned int result, int unpause)
3570 {
3571   struct aic7xxx_host *p;
3572   struct aic7xxx_scb *scb;
3573   int i, active_scb, found, queued;
3574   unsigned char scbsave[AIC7XXX_MAXSCB];
3575   unsigned char flags;
3576   int scb_control;
3577   k_state status;
3578 
3579   p = (struct aic7xxx_host *) cmd->host->hostdata;
3580   scb = &p->scb_array[aic7xxx_position(cmd)];
3581 
3582 #if 0
3583   printk("aic7xxx_kill: In the kill function...\n");
3584 #endif
3585   PAUSE_SEQUENCER(p);
3586 
3587   /*
3588    * Case 1: In the QINFIFO
3589    *
3590    * This is the best case, really. Check to see if the
3591    * command is still in the sequencer's input queue. If
3592    * so, simply remove it. Reload the queue afterward.
3593    */
3594   queued = inb(QINCNT(p->base));
3595 
3596   for (i = found = 0; i < (queued - found); i++)
3597   {
3598     scbsave[i] = inb(QINFIFO(p->base));
3599 
3600     if (scbsave[i] == scb->position)
3601     {
3602       found = 1;
3603       i = i - 1;
3604     }
3605   }
3606 
3607   for (queued = 0; queued < i; queued++)
3608   {
3609     outb(scbsave[queued], QINFIFO(p->base));
3610   }
3611 
3612   if (found)
3613   {
3614     status = k_ok;
3615     goto complete;
3616   }
3617 
3618   active_scb = inb(SCBPTR(p->base));
3619   /*
3620    * Case 2: Not the active command
3621    *
3622    * Check the current SCB bank. If it's not the one belonging
3623    * to the command we want to kill, select the scb we want to
3624    * abort and turn off the disconnected bit. The driver will
3625    * then abort the command and notify us of the abort.
3626    */
3627   if (active_scb != scb->position)
3628   {
3629     outb(scb->position, SCBPTR(p->base));
3630     scb_control = inb(SCBARRAY(p->base));
3631     scb_control = scb_control & ~SCB_DIS;
3632     outb(scb_control, SCBARRAY(p->base));
3633     outb(active_scb, SCBPTR(p->base));
3634     status = k_disconnect;
3635     goto complete;
3636   }
3637 
3638   scb_control = inb(SCBARRAY(p->base));
3639   if (scb_control & SCB_DIS)
3640   {
3641     scb_control = scb_control & ~SCB_DIS;
3642     outb(scb_control, SCBARRAY(p->base));
3643     status = k_disconnect;
3644     goto complete;
3645   }
3646 
3647   /*
3648    * Presumably at this point our target command is active. Check
3649    * to see if there's a message already in effect. If not, place
3650    * our message in and assert ATN so the target goes into MESSAGE
3651    * OUT phase.
3652    */
3653   flags = inb(HA_FLAGS(p->base));
3654   if (flags & ACTIVE_MSG)
3655   {
3656     /*
3657      * If there is a message in progress, reset the bus
3658      * and have all devices renegotiate.
3659      */
3660     if (cmd->channel & 0x01)
3661     {
3662       p->needsdtr = p->needsdtr_copy & 0xFF00;
3663       p->sdtr_pending = p->sdtr_pending & 0x00FF;
3664       outb(0, HA_ACTIVE1(p->base));
3665     }
3666     else
3667     {
3668       if (p->bus_type == AIC_WIDE)
3669       {
3670         p->needsdtr = p->needsdtr_copy;
3671         p->needwdtr = p->needwdtr_copy;
3672         p->sdtr_pending = 0;
3673         p->wdtr_pending = 0;
3674         outb(0, HA_ACTIVE0(p->base));
3675         outb(0, HA_ACTIVE1(p->base));
3676       }
3677       else
3678       {
3679         p->needsdtr = p->needsdtr_copy & 0x00FF;
3680         p->sdtr_pending = p->sdtr_pending & 0xFF00;
3681         outb(0, HA_ACTIVE0(p->base));
3682       }
3683     }
3684     /* Reset the bus. */
3685     outb(SCSIRSTO, SCSISEQ(p->base));
3686     udelay(1000);
3687     outb(0, SCSISEQ(p->base));
3688     aic7xxx_delay(AIC7XXX_RESET_DELAY);
3689 
3690     status = k_busy;
3691     goto complete;
3692   }
3693 
3694   outb(flags | ACTIVE_MSG, HA_FLAGS(p->base));    /* active message */
3695   outb(1, HA_MSG_LEN(p->base));                   /* length = 1 */
3696   outb(message, HA_MSG_START(p->base));           /* message body */
3697 
3698   /*
3699    * Assert ATN. Use the value of SCSISIGO saved by the
3700    * sequencer code so we don't alter its contents radically
3701    * in the middle of something critical.
3702    */
3703   outb(inb(HA_SIGSTATE(p->base)) | 0x10, SCSISIGO(p->base));
3704 
3705   status = k_ok;
3706 
3707   /*
3708    * The command has been killed. Do the bookkeeping, unpause
3709    * the sequencer, and notify the higher-level SCSI code.
3710    */
3711 complete:
3712   if (unpause)
3713   {
3714     UNPAUSE_SEQUENCER(p);
3715   }
3716 
3717   /*
3718    * Mark the scb as free and clear the scbs command pointer.
3719    * Add the scb to the head of the free list being careful
3720    * to preserve the next pointers.
3721    */
3722   scb->state = SCB_FREE;          /* mark the scb as free */
3723   scb->cmd = NULL;                /* clear the command pointer */
3724   scb->next = p->free_scb;        /* preserve next pointer */
3725   p->free_scb = scb;              /* add at head of free list */
3726   cmd->result = cmd->result << 16;
3727   cmd->scsi_done(cmd);
3728   return(status);
3729 }
3730 
3731 /*+F*************************************************************************
3732  * Function:
3733  *   aic7xxx_abort
3734  *
3735  * Description:
3736  *   Abort the current SCSI command(s).
3737  *-F*************************************************************************/
3738 int
3739 aic7xxx_abort(Scsi_Cmnd *cmd)
     /*  */
3740 {
3741   int rv;
3742   long flags;
3743 
3744   save_flags(flags);
3745   cli();
3746 
3747   switch (aic7xxx_kill(cmd, ABORT, DID_ABORT, !0))
3748   {
3749     case k_ok:          rv = SCSI_ABORT_SUCCESS;        break;
3750     case k_busy:        rv = SCSI_ABORT_BUSY;           break;
3751     case k_absent:      rv = SCSI_ABORT_NOT_RUNNING;    break;
3752     case k_disconnect:  rv = SCSI_ABORT_SNOOZE;         break;
3753     default:            panic("aic7xxx_abort: internal error\n");
3754   }
3755 
3756   restore_flags(flags);
3757   return(rv);
3758 }
3759 
3760 /*+F*************************************************************************
3761  * Function:
3762  *   aic7xxx_reset
3763  *
3764  * Description:
3765  *   Resetting the bus always succeeds - is has to, otherwise the
3766  *   kernel will panic! Try a surgical technique - sending a BUS
3767  *   DEVICE RESET message - on the offending target before pulling
3768  *   the SCSI bus reset line.
3769  *-F*************************************************************************/
3770 int
3771 aic7xxx_reset(Scsi_Cmnd *cmd)
     /*  */
3772 {
3773   long flags;
3774   struct aic7xxx_host *p;
3775 
3776   p = (struct aic7xxx_host *) cmd->host->hostdata;
3777   save_flags(flags);
3778   cli();
3779 
3780   switch (aic7xxx_kill(cmd, BUS_DEVICE_RESET, DID_RESET, 0))
3781   {
3782     case k_ok:
3783       /*
3784        * The RESET message was sent to the target
3785        * with no problems. Flag that target as
3786        * needing a SDTR negotiation on the next
3787        * connection and restart the sequencer.
3788        */
3789       p->needsdtr = p->needsdtr & (1 << cmd->target);
3790       UNPAUSE_SEQUENCER(p);
3791       break;
3792 
3793     case k_absent:
3794       /*
3795        * The sequencer will not be paused if aic7xxx_kill()
3796        * couldn't find the command.
3797        */
3798       PAUSE_SEQUENCER(p);
3799       /* falls through */
3800 
3801     case k_busy:
3802       cmd->result = DID_RESET << 16;  /* return reset code */
3803       cmd->scsi_done(cmd);
3804       break;
3805 
3806     case k_disconnect:
3807       /*
3808        * Do a hard reset of the SCSI bus. According to the
3809        * SCSI-2 draft specification, reset has to be asserted
3810        * for at least 25us. I'm invoking the kernel delay
3811        * function for 30us since I'm not totally trusting of
3812        * the busy loop timing.
3813        *
3814        * XXX - I'm not convinced this works. I tried resetting
3815        *       the bus before, trying to get the devices on the
3816        *       bus to revert to asynchronous transfer, and it
3817        *       never seemed to work.
3818        */
3819       debug("aic7xxx: attempting to reset scsi bus and card\n");
3820 
3821       outb(SCSIRSTO, SCSISEQ(p->base));
3822       udelay(1000);
3823       outb(0, SCSISEQ(p->base));
3824       aic7xxx_delay(AIC7XXX_RESET_DELAY);
3825 
3826       UNPAUSE_SEQUENCER(p);
3827 
3828       /*
3829        * Locate the command and return a "reset" status
3830        * for it. This is not completely correct and will
3831        * probably return to haunt me later.
3832        */
3833       cmd->result = DID_RESET << 16;  /* return reset code */
3834       cmd->scsi_done(cmd);
3835       break;
3836 
3837     default:
3838       panic("aic7xxx_reset: internal error\n");
3839   }
3840 
3841   restore_flags(flags);
3842   return(SCSI_RESET_SUCCESS);
3843 }
3844 
3845 /*+F*************************************************************************
3846  * Function:
3847  *   aic7xxx_biosparam
3848  *
3849  * Description:
3850  *   Return the disk geometry for the given SCSI device.
3851  *-F*************************************************************************/
3852 int
3853 aic7xxx_biosparam(Disk *disk, int devno, int geom[])
     /*  */
3854 {
3855   int heads, sectors, cylinders;
3856   struct aic7xxx_host *p;
3857 
3858   p = (struct aic7xxx_host *) disk->device->host->hostdata;
3859 
3860   /*
3861    * XXX - if I could portably find the card's configuration
3862    *       information, then this could be autodetected instead
3863    *       of left to a boot-time switch.
3864    */
3865   heads = 64;
3866   sectors = 32;
3867   cylinders = disk->capacity / (heads * sectors);
3868 
3869   if (p->extended && cylinders > 1024)
3870   {
3871     heads = 255;
3872     sectors = 63;
3873     cylinders = disk->capacity / (255 * 63);
3874   }
3875 
3876   geom[0] = heads;
3877   geom[1] = sectors;
3878   geom[2] = cylinders;
3879 
3880   return(0);
3881 }
3882 
3883 #ifdef MODULE
3884 /* Eventually this will go into an include file, but this will be later */
3885 Scsi_Host_Template driver_template = AIC7XXX;
3886 
3887 #include "scsi_module.c"
3888 #endif
3889
/* */
root/drivers/scsi/aic7xxx.c

DEFINITIONS
