include/asm-sparc/system.h

/* */
This source file includes following definitions.
xchg_u32
xchg_ptr
   1 #ifndef __SPARC_SYSTEM_H
   2 #define __SPARC_SYSTEM_H
   3 
   4 #include <asm/segment.h>
   5 
   6 /*
   7  * I wish the boot time image was as beautiful as the Alpha's
   8  * but no such luck. The icky PROM loads us at 0x0, and jumps
   9  * to magic address 0x4000 to start things going.
  10  *
  11  * Sorry, I can't impress people with cool looking 64-bit values
  12  * yet. Wait till V9 ;-)
  13  */
  14 
  15 #include <asm/page.h>
  16 #include <asm/openprom.h>
  17 #include <asm/psr.h>
  18 
  19 #define START_ADDR      (0x00004000)
  20 #define EMPTY_PGT       (&empty_bad_page)
  21 #define EMPTY_PGE       (&empty_bad_page_table)
  22 #define ZERO_PGE        (&empty_zero_page)
  23 
  24 #ifndef __ASSEMBLY__
  25 
  26 /*
  27  * Sparc (general) CPU types
  28  */
  29 enum sparc_cpu {
  30   sun4        = 0x00,
  31   sun4c       = 0x01,
  32   sun4m       = 0x02,
  33   sun4d       = 0x03,
  34   sun4e       = 0x04,
  35   sun4u       = 0x05,
  36   sun_unknown = 0x06,
  37 };
  38 
  39 extern enum sparc_cpu sparc_cpu_model;
  40 
  41 extern unsigned long empty_bad_page;
  42 extern unsigned long empty_bad_page_table;
  43 extern unsigned long empty_zero_page;
  44 
  45 extern void wrent(void *, unsigned long);
  46 extern void wrkgp(unsigned long);
  47 extern struct linux_romvec *romvec;
  48 
  49 #define halt() do { \
  50                          printk("Entering monitor in file %s at line %d\n", __FILE__, __LINE__); \
  51 romvec->pv_halt(); } while(0)
  52 
  53 #define move_to_user_mode() halt()
  54 
  55 #ifndef stbar  /* store barrier Sparc insn to synchronize stores in PSO */
  56 #define stbar() __asm__ __volatile__("stbar": : :"memory")
  57 #endif
  58 
  59 /* When a context switch happens we must flush all user windows so that
  60  * the windows of the current process are flushed onto it's stack. This
  61  * way the windows are all clean for the next process.
  62  */
  63 
  64 #define flush_user_windows() \
  65 do { __asm__ __volatile__( \
  66                           "save %sp, -64, %sp\n\t" \
  67                           "save %sp, -64, %sp\n\t" \
  68                           "save %sp, -64, %sp\n\t" \
  69                           "save %sp, -64, %sp\n\t" \
  70                           "save %sp, -64, %sp\n\t" \
  71                           "save %sp, -64, %sp\n\t" \
  72                           "save %sp, -64, %sp\n\t" \
  73                           "restore\n\t" \
  74                           "restore\n\t" \
  75                           "restore\n\t" \
  76                           "restore\n\t" \
  77                           "restore\n\t" \
  78                           "restore\n\t" \
  79                           "restore\n\t"); } while(0)
  80 
  81 extern void sparc_switch_to(void *new_task);
  82 
  83 #define switch_to(p) sparc_switch_to(p)
  84 
  85 /* Changing the PIL on the sparc is a bit hairy. I'll figure out some
  86  * more optimized way of doing this soon. This is bletcherous code.
  87  */
  88 
  89 #define swpipl(__new_ipl) \
  90 ({ unsigned long psr, retval; \
  91 __asm__ __volatile__( \
  92         "rd %%psr, %0\n\t" : "=&r" (psr)); \
  93 retval = psr; \
  94 psr = (psr & ~(PSR_PIL)); \
  95 psr |= ((__new_ipl << 8) & PSR_PIL); \
  96 __asm__ __volatile__( \
  97         "wr  %0, 0x0, %%psr\n\t" \
  98         : : "r" (psr)); \
  99 retval = ((retval>>8)&15); \
 100 retval; })
 101 
 102 #define cli()                   swpipl(15)  /* 15 = no int's except nmi's */
 103 #define sti()                   swpipl(0)   /* I'm scared */
 104 #define save_flags(flags)       do { flags = swpipl(15); } while (0)
 105 #define restore_flags(flags)    swpipl(flags)
 106 
 107 #define iret() __asm__ __volatile__ ("jmp %%l1\n\t" \
 108                                      "rett %%l2\n\t": : :"memory")
 109 
 110 /* Must this be atomic? */
 111 
 112 extern inline void *xchg_u32(int * m, unsigned long val)
     /*  */
 113 {
 114         unsigned long dummy;
 115 
 116         __asm__ __volatile__(
 117                 "ld %1,%2\n\t"
 118                 "st %0, %1\n\t"
 119                 "or %%g0, %2, %0"
 120                 : "=r" (val), "=m" (*m), "=r" (dummy)
 121                 : "0" (val));
 122         return (void *) val;
 123 }
 124 
 125 
 126 /* pointers are 32 bits on the sparc (at least the v8, and they'll work
 127  * on the V9 none the less). I don't need the xchg_u64 routine for now.
 128  */
 129 
 130 extern inline void *xchg_ptr(void *m, void *val)
     /*  */
 131 {
 132         return (void *) xchg_u32((int *) m, (unsigned long) val);
 133 }
 134 
 135 
 136 
 137 #endif /* __ASSEMBLY__ */
 138 
 139 #endif
/* */
root/include/asm-sparc/system.h

INCLUDED FROM

DEFINITIONS
