root/include/asm-sparc/cache.h

/* */

INCLUDED FROM

DEFINITIONS

1. get_icache_tag
2. put_icache_tag
3. get_icache_data
4. put_icache_data
5. flush_ei_page
6. flush_ei_seg
7. flush_ei_region
8. flush_ei_ctx
9. flush_ei_user

   1 /* cache.h:  Cache specific code for the Sparc.  These include flushing
   2  *           and direct tag/data line access.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_CACHE_H
   8 #define _SPARC_CACHE_H
   9 
  10 #include <asm/asi.h>
  11 
  12 /* Direct access to the instruction cache is provided through and
  13  * alternate address space.  The IDC bit must be off in the ICCR on
  14  * HyperSparcs for these accesses to work.  The code below does not do
  15  * any checking, the caller must do so.  These routines are for
  16  * diagnostics only, but coule end up being useful.  Use with care.
  17  * Also, you are asking for trouble if you execute these in one of the
  18  * three instructions following a %asr/%psr access or modification.
  19  */
  20 
  21 /* First, cache-tag access. */
  22 extern inline unsigned int get_icache_tag(int setnum, int tagnum)
     /*  */
  23 {
  24         unsigned int vaddr, retval;
  25 
  26         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  27         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
  28                              "=r" (retval) :
  29                              "r" (vaddr), "i" (ASI_M_TXTC_TAG));
  30         return retval;
  31 }
  32 
  33 extern inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
     /*  */
  34 {
  35         unsigned int vaddr;
  36 
  37         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  38         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
  39                              "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
  40                              "memory");
  41         return;
  42 }
  43 
  44 /* Second cache-data access.  The data is returned two-32bit quantities
  45  * at a time.
  46  */
  47 extern inline void get_icache_data(int setnum, int tagnum, int subblock,
     /*  */
  48                               unsigned int *data)
  49 {
  50         unsigned int value1, value2, vaddr;
  51 
  52         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | ((subblock&0x3) << 3);
  53         __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
  54                              "or %%g0, %%g2, %0\n\t"
  55                              "or %%g0, %%g3, %1\n\t" :
  56                              "=r" (value1), "=r" (value2) :
  57                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  58                              "g2", "g3");
  59         data[0] = value1; data[1] = value2;
  60         return;
  61 }
  62 
  63 extern inline void put_icache_data(int setnum, int tagnum, int subblock,
     /*  */
  64                               unsigned int *data)
  65 {
  66         unsigned int value1, value2, vaddr;
  67 
  68         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | ((subblock&0x3) << 3);
  69         value1 = data[0]; value2 = data[1];
  70         __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
  71                              "or %%g0, %1, %%g3\n\t"
  72                              "stda %%g2, [%2] %3\n\t" : :
  73                              "r" (value1), "r" (value2), 
  74                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  75                              "g2", "g3", "memory" /* no joke */);
  76         return;
  77 }
  78 
  79 /* Different types of flushes with the ICACHE.  Some of the flushes
  80  * affect both the ICACHE and the external cache.  Others only clear
  81  * the ICACHE entries on the cpu itself.  V8's (most) allow
  82  * granularity of flushes on the packet (element in line), whole line,
  83  * and entire cache (ie. all lines) level.  The ICACHE only flushes are
  84  * ROSS HyperSparc specific and are in ross.h
  85  */
  86 
  87 /* Flushes which clear out both the on-chip and external caches */
  88 extern inline void flush_ei_page(unsigned int addr)
     /*  */
  89 {
  90         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  91                              "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
  92                              "memory");
  93         return;
  94 }
  95 
  96 extern inline void flush_ei_seg(unsigned int addr)
     /*  */
  97 {
  98         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  99                              "r" (addr), "i" (ASI_M_FLUSH_SEG) :
 100                              "memory");
 101         return;
 102 }
 103 
 104 extern inline void flush_ei_region(unsigned int addr)
     /*  */
 105 {
 106         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 107                              "r" (addr), "i" (ASI_M_FLUSH_REGION) :
 108                              "memory");
 109         return;
 110 }
 111 
 112 extern inline void flush_ei_ctx(unsigned int addr)
     /*  */
 113 {
 114         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 115                              "r" (addr), "i" (ASI_M_FLUSH_CTX) :
 116                              "memory");
 117         return;
 118 }
 119 
 120 extern inline void flush_ei_user(unsigned int addr)
     /*  */
 121 {
 122         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 123                              "r" (addr), "i" (ASI_M_FLUSH_USER) :
 124                              "memory");
 125         return;
 126 }
 127 
 128 #endif /* !(_SPARC_CACHE_H) */

/* */