include/asm-sparc/ecc.h

/* */
   1 /* ecc.h: Definitions and defines for the external cache/memory
   2  *        controller on the sun4m.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_ECC_H
   8 #define _SPARC_ECC_H
   9 
  10 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
  11 #define ECC_ENABLE     0x00000000       /* ECC enable register */
  12 #define ECC_FSTATUS    0x00000008       /* ECC fault status register */
  13 #define ECC_FADDR      0x00000010       /* ECC fault address register */
  14 #define ECC_DIGNOSTIC  0x00000018       /* ECC diagnostics register */
  15 #define ECC_MBAENAB    0x00000020       /* MBus arbiter enable register */
  16 #define ECC_DMESG      0x00001000       /* Diagnostic message passing area */
  17 
  18 /* ECC MBus Arbiter Enable register:
  19  *
  20  * ----------------------------------------
  21  * |              |SBUS|MOD3|MOD2|MOD1|RSV|
  22  * ----------------------------------------
  23  *  31           5   4   3    2    1    0
  24  *
  25  * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
  26  * MOD3: Enable MBus Arbiter on MBus module 3  0=off 1=on
  27  * MOD2: Enable MBus Arbiter on MBus module 2  0=off 1=on
  28  * MOD1: Enable MBus Arbiter on MBus module 1  0=off 1=on
  29  */
  30 
  31 #define ECC_MBAE_SBUS     0x00000010
  32 #define ECC_MBAE_MOD3     0x00000008
  33 #define ECC_MBAE_MOD2     0x00000004
  34 #define ECC_MBAE_MOD1     0x00000002 
  35 
  36 /* ECC Fault Control Register layout:
  37  *
  38  * -----------------------------
  39  * |    RESV   | ECHECK | EINT |
  40  * -----------------------------
  41  *  31        2     1       0
  42  *
  43  * ECHECK:  Enable ECC checking.  0=off 1=on
  44  * EINT:  Enable Interrupts for correctable errors. 0=off 1=on
  45  */ 
  46 #define ECC_FCR_CHECK    0x00000002
  47 #define ECC_FCR_INTENAB  0x00000001
  48 
  49 /* ECC Fault Address Register Zero layout:
  50  *
  51  * -----------------------------------------------------
  52  * | MID | S | RSV |  VA   | BM |AT| C| SZ |TYP| PADDR |
  53  * -----------------------------------------------------
  54  *  31-28  27 26-22  21-14   13  12 11 10-8 7-4   3-0
  55  *
  56  * MID: ModuleID of the faulting processor. ie. who did it?
  57  * S: Supervisor/Privileged access? 0=no 1=yes
  58  * VA: Bits 19-12 of the virtual faulting address, these are the
  59  *     superset bits in the virtual cache and can be used for
  60  *     a flush operation if necessary.
  61  * BM: Boot mode? 0=no 1=yes  This is just like the SRMMU boot
  62  *     mode bit.
  63  * AT: Did this fault happen during an atomic instruction? 0=no
  64  *     1=yes.  This means either an 'ldstub' or 'swap' instruction
  65  *     was in progress (but not finished) when this fault happened.
  66  *     This indicated whether the bus was locked when the fault
  67  *     occurred.
  68  * C: Did the pte for this access indicate that it was cacheable?
  69  *    0=no 1=yes
  70  * SZ: The size of the transaction.
  71  * TYP: The transaction type.
  72  * PADDR: Bits 35-32 of the physical address for the fault.
  73  */
  74 #define ECC_FADDR0_MIDMASK   0xf0000000
  75 #define ECC_FADDR0_S         0x08000000
  76 #define ECC_FADDR0_VADDR     0x003fc000
  77 #define ECC_FADDR0_BMODE     0x00002000
  78 #define ECC_FADDR0_ATOMIC    0x00001000
  79 #define ECC_FADDR0_CACHE     0x00000800
  80 #define ECC_FADDR0_SIZE      0x00000700
  81 #define ECC_FADDR0_TYPE      0x000000f0
  82 #define ECC_FADDR0_PADDR     0x0000000f
  83 
  84 /* ECC Fault Address Register One layout:
  85  *
  86  * -------------------------------------
  87  * |          Physical Address 31-0    |
  88  * -------------------------------------
  89  *  31                               0
  90  *
  91  * You get the upper 4 bits of the physical address from the
  92  * PADDR field in ECC Fault Address Zero register.
  93  */
  94 
  95 /* ECC Fault Status Register layout:
  96  *
  97  * ----------------------------------------------
  98  * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
  99  * ----------------------------------------------
 100  *  31-18  17  16    15-8    7-4   3    2    1 0
 101  *
 102  * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
 103  * MULT: Multiple errors occurres ;-O 0=no 1=prom_panic(yes)
 104  * SYNDROME: Controller is mentally unstable.
 105  * DWORD:
 106  * UNC: Uncorrectable error.  0=no 1=yes
 107  * TIMEO: Timeout occurred. 0=no 1=yes
 108  * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
 109  * C: Correctable error? 0=no 1=yes
 110  */
 111 
 112 #define ECC_FSR_C2ERR    0x00020000
 113 #define ECC_FSR_MULT     0x00010000
 114 #define ECC_FSR_SYND     0x0000ff00
 115 #define ECC_FSR_DWORD    0x000000f0
 116 #define ECC_FSR_UNC      0x00000008
 117 #define ECC_FSR_TIMEO    0x00000004
 118 #define ECC_FSR_BADSLOT  0x00000002
 119 #define ECC_FSR_C        0x00000001
 120 
 121 #endif /* !(_SPARC_ECC_H) */
/* */
root/include/asm-sparc/ecc.h
