root/include/asm-sparc/tsunami.h

/* */

   1 /* tsunami.h:  Module specific definitions for Tsunami V8 Sparcs
   2  *
   3  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5 
   6 #ifndef _SPARC_TSUNAMI_H
   7 #define _SPARC_TSUNAMI_H
   8 
   9 /* The MMU control register on the Tsunami:
  10  *
  11  * -----------------------------------------------------------------------
  12  * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
  13  * -----------------------------------------------------------------------
  14  *  31      24 23 22 21 20 19-18 17  16 14  13-12 11 10-9  8  7 6-2  1  0
  15  *
  16  * SW: Enable Software Table Walks  0=off 1=on
  17  * AV: Address View bit
  18  * DV: Data View bit
  19  * MV: Memory View bit
  20  * PC: Parity Control
  21  * ITD: ITBR disable
  22  * ALC: Alternate Cacheable
  23  * PE: Parity Enable   0=off 1=on
  24  * RC: Refresh Control
  25  * IE: Instruction cache Enable  0=off 1=on
  26  * DE: Data cache Enable  0=off 1=on
  27  * NF: No Fault, same as all other SRMMUs
  28  * ME: MMU Enable, same as all other SRMMUs
  29  */
  30 
  31 #define TSUNAMI_SW        0x00800000
  32 #define TSUNAMI_AV        0x00400000
  33 #define TSUNAMI_DV        0x00200000
  34 #define TSUNAMI_MV        0x00100000
  35 #define TSUNAMI_PC        0x00020000
  36 #define TSUNAMI_ITD       0x00010000
  37 #define TSUNAMI_ALC       0x00008000
  38 #define TSUNAMI_PE        0x00001000
  39 #define TSUNAMI_RCMASK    0x00000C00
  40 #define TSUNAMI_IENAB     0x00000200
  41 #define TSUNAMI_DENAB     0x00000100
  42 #define TSUNAMI_NF        0x00000002
  43 #define TSUNAMI_ME        0x00000001
  44 
  45 #endif /* !(_SPARC_TSUNAMI_H) */

/* */