root/drivers/net/ibmtr.h

/* */

INCLUDED FROM

   1 /* Definitions for an IBM Token Ring card. */
   2 /* This file is distributed under the GNU GPL   */
   3 
   4 #define TR_RETRY_INTERVAL 500
   5 #define TR_ISA 1
   6 #define TR_MCA 2
   7 #define TR_ISAPNP 3
   8 #define NOTOK 0
   9 #define TOKDEBUG 1
  10 
  11 #ifndef IBMTR_SHARED_RAM_BASE
  12 #define IBMTR_SHARED_RAM_BASE 0xD0
  13 #define IBMTR_SHARED_RAM_SIZE 0x10
  14 #endif
  15 
  16 #define CHANNEL_ID      0X1F30
  17 #define AIP             0X1F00
  18 #define AIPCHKSUM1      0X1F60
  19 #define AIPCHKSUM2      0X1FF0
  20 #define AIPADAPTYPE     0X1FA0
  21 #define AIPDATARATE     0X1FA2
  22 #define AIPEARLYTOKEN   0X1FA4
  23 #define AIPAVAILSHRAM   0X1FA6
  24 #define AIPSHRAMPAGE    0X1FA8
  25 #define AIP4MBDHB       0X1FAA
  26 #define AIP16MBDHB      0X1FAC
  27 #define AIPFID          0X1FBA
  28 
  29 /* Note, 0xA20 == 0x220 since motherboard decodes 10 bits.  I left everything
  30    the way my documentation had it, ie: 0x0A20.     */
  31 #define ADAPTINTCNTRL   0x02f0  /* Adapter interrupt control */
  32 #define ADAPTRESET      0x1     /* Control Adapter reset (add to base) */
  33 #define ADAPTRESETREL   0x2     /* Release Adapter from reset ( """)  */
  34 #define ADAPTINTREL     0x3     /* Adapter interrupt release */
  35 
  36 #define MMIOStartLocP   0x0a20  /* Primary adapter's starting MMIO area */
  37 #define MMIOStartLocA   0x0a24  /* Alternate adapter's starting MMIO area */
  38 
  39 #define GLOBAL_INT_ENABLE 0x02f0
  40 
  41 /* MMIO bits 0-4 select register */
  42 #define RRR_EVEN        0x00    /* Shared RAM relocation registers - even and odd */
  43 /* Used to set the starting address of shared RAM  */
  44 /* Bits 1 through 7 of this register map to bits 13 through 19 of the shared RAM address.*/
  45 /* ie: 0x02 sets RAM address to ...ato!  issy su wazzoo !! GODZILLA!!! */
  46 #define RRR_ODD         0x01
  47 /* Bits 2 and 3 of this register can be read to determine shared RAM size */
  48 /* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k  */
  49 #define WRBR_EVEN       0x02    /* Write region base registers - even and odd */
  50 #define WRBR_ODD        0x03
  51 #define WWCR_EVEN       0x04    /* Write window close registers - even and odd */
  52 #define WWCR_ODD        0x05
  53 #define WWOR_EVEN       0x06    /* Write window open registers - even and odd */
  54 #define WWOR_ODD        0x07
  55 
  56 /* Interrupt status registers - PC system  - even and odd */
  57 #define ISRP_EVEN       0x08
  58 
  59 #define TCR_INT 0x10    /* Bit 4 - Timer interrupt.  The TVR_EVEN timer has
  60                                                                    expired. */
  61 #define ERR_INT 0x08    /* Bit 3 - Error interrupt.  The adapter has had an
  62                                                                    internal error. */
  63 #define ACCESS_INT 0x04    /* Bit 2 - Access interrupt.  You have attempted to
  64                                                            write to an invalid area of shared RAM or an invalid
  65                                                                    register within the MMIO. */
  66 /*      In addition, the following bits within ISRP_EVEN can be turned on or off by you */
  67 /*      to control the interrupt processing:   */
  68 #define INT_IRQ 0x80    /* Bit 7 - If 0 the adapter will issue a CHCK, if 1 and
  69                                                               IRQ.  This should normally be set (by you) to 1.  */
  70 #define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable.  If 0, no interrupts will
  71                                                                    occur.  If 1, interrupts will occur normally.
  72                                                                    Normally set to 1.  */
  73 /* Bit 0 - Primary or alternate adapter.  Set to zero if this adapter is the primary adapter,*/
  74 /*         1 if this adapter is the alternate adapter. */
  75 
  76 
  77 #define ISRP_ODD        0x09
  78 
  79 #define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check.  the adapter has
  80                              encountered a serious problem and has closed
  81                              itself.  Whoa.  */
  82 #define SRB_RESP_INT 0x20 /* Bit 5 - SRB response.  The adapter has accepted
  83                              an SRB request and set the return code withing
  84                              the SRB. */
  85 #define ASB_FREE_INT 0x10 /* Bit 4 - ASB free.  The adapter has read the ASB
  86                                                                           and this area can be safely reused. This interrupt
  87                                                                           is only used if your application has set the ASB
  88                                                                           free request bit in ISRA_ODD or if an error was
  89                                                                 detected in your response. */
  90 #define ARB_CMD_INT  0x08 /* Bit 3 - ARB command.  The adapter has given you a
  91                                                                           command for action.  The command is located in the
  92                                                                           ARB area of shared memory. */
  93 #define SSB_RESP_INT 0x04 /* Bit 2 - SSB response.  The adapter has posted a
  94                                                                           response to your SRB (the response is located in
  95                                                                           the SSB area of shared memory). */
  96 /* Bit 1 - Bridge frame forward complete. */
  97 
  98 
  99 
 100 #define ISRA_EVEN       0x0A    /* Interrupt status registers - adapter  - even and odd */
 101 /* Bit 7 - Internal parity error (on adapter's internal bus) */
 102 /* Bit 6 - Timer interrupt pending */
 103 /* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */
 104 /* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */
 105 /* Bit 3 - Adapter processor check status */
 106 /* Bit 2 - Reserved */
 107 /* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */
 108 /* Bit 0 - Adapter software interrupt mask (prevents internal software interrupts) */
 109 
 110 #define ISRA_ODD        0x0B
 111 #define CMD_IN_SRB 0x20 /* Bit 5  - Indicates that you have placed a new
 112                            command in the SRB and are ready for the adapter to
 113                            process the command. */
 114 #define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response
 115                                                                     (an ASB) in the shared RAM which is available for
 116                                                                          the adapter's use. */
 117 /* Bit 3 - Indicates that you are ready to ut an SRB in the shared RAM, but that a previous */
 118 /*         command is still pending.  The adapter will then interrupt you when the previous */
 119 /*         command is completed */
 120 /* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but that a previous */
 121 /*         ASB is still pending.  The adapter will then interrupt you when the previous ASB */
 122 /*         is copied.  */
 123 #define ARB_FREE 0x2
 124 #define SSB_FREE 0x1
 125 
 126 #define TCR_EVEN        0x0C    /* Timer control registers - even and odd */
 127 #define TCR_ODD         0x0D
 128 #define TVR_EVEN        0x0E    /* Timer value registers - even and odd */
 129 #define TVR_ODD         0x0F
 130 #define SRPR_EVEN       0x10    /* Shared RAM paging registers - even and odd */
 131 #define SRPR_ENABLE_PAGING 0xc0
 132 #define SRPR_ODD        0x11 /* Not used. */
 133 #define TOKREAD         0x60
 134 #define TOKOR           0x40
 135 #define TOKAND          0x20
 136 #define TOKWRITE        0x00
 137 
 138 /* MMIO bits 5-6 select operation */
 139 /* 00 is used to write to a register */
 140 /* 01 is used to bitwise AND a byte with a register */
 141 /* 10 is used to bitwise OR a byte with a register  */
 142 /* 11 is used to read from a register */
 143 
 144 /* MMIO bits 7-8 select area of interest.. see below */
 145 /* 00 selects attachment control area. */
 146 /* 01 is reserved. */
 147 /* 10 selects adapter identification area A containing the adapter encoded address. */
 148 /* 11 selects the adapter identification area B containing test patterns. */
 149 
 150 #define PCCHANNELID 5049434F3631313039393020
 151 #define MCCHANNELID 4D4152533633583435313820
 152 
 153 #define ACA_OFFSET 0x1e00
 154 #define ACA_SET 0x40
 155 #define ACA_RESET 0x20
 156 #define ACA_RW 0x00
 157 
 158 #ifdef ENABLE_PAGING
 159 #define SET_PAGE(x) (*(unsigned char *) \
 160                          (ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN)\
 161                                                 = (x>>8)&ti.page_mask)
 162 #else
 163 #define SET_PAGE(x)
 164 #endif
 165 
 166 typedef enum { IN_PROGRESS, SUCCES, FAILURE, CLOSED } open_state;
 167 
 168 struct tok_info {
 169         unsigned char irq;
 170         unsigned char *mmio;
 171         unsigned char hw_address[32];
 172         unsigned char adapter_type;
 173         unsigned char data_rate;
 174         unsigned char token_release;
 175         unsigned char avail_shared_ram;
 176         unsigned char shared_ram_paging;
 177         unsigned char dhb_size4mb;
 178         unsigned char dhb_size16mb;
 179 /* Additions by David Morris       */
 180         unsigned char do_tok_int;
 181 #define FIRST_INT 1
 182 #define NOT_FIRST 2
 183         struct wait_queue *wait_for_tok_int;
 184         struct wait_queue *wait_for_reset;
 185         unsigned char sram_base;
 186 /* Additions by Peter De Schrijver */
 187         unsigned char page_mask;     /* mask to select RAM page to Map*/
 188         unsigned char mapped_ram_size;  /* size of RAM page */
 189         unsigned char *sram; /* Shared memory base address */
 190         unsigned char *init_srb;  /* Initial System Request Block address */
 191         unsigned char *srb;  /* System Request Block address */
 192         unsigned char *ssb;  /* System Status Block address */
 193         unsigned char *arb;  /* Adapter Request Block address */
 194         unsigned char *asb;  /* Adapter Status Block address */
 195         unsigned short exsap_station_id;
 196         unsigned short global_int_enable;
 197         struct sk_buff *current_skb;
 198         struct tr_statistics tr_stats;
 199         unsigned char auto_ringspeedsave;
 200         open_state open_status;
 201         
 202 };
 203 
 204 struct srb_init_response {
 205         unsigned char command;
 206         unsigned char init_status;
 207         unsigned char init_status_2;
 208         unsigned char reserved[3];
 209         unsigned short bring_up_code;
 210         unsigned short encoded_address;
 211         unsigned short level_address;
 212         unsigned short adapter_address;
 213         unsigned short parms_address;
 214         unsigned short mac_address;
 215 };
 216 
 217 #define DIR_OPEN_ADAPTER 0x03
 218 
 219 struct dir_open_adapter {
 220         unsigned char command;
 221         char reserved[7];
 222         unsigned short open_options;
 223         unsigned char node_address[6];
 224         unsigned char group_address[4];
 225         unsigned char funct_address[4];
 226         unsigned short num_rcv_buf;
 227         unsigned short rcv_buf_len;
 228         unsigned short dhb_length;
 229         unsigned char num_dhb;
 230         char reserved2;
 231         unsigned char dlc_max_sap;
 232         unsigned char dlc_max_sta;
 233         unsigned char dlc_max_gsap;
 234         unsigned char dlc_max_gmem;
 235         unsigned char dlc_t1_tick_1;
 236         unsigned char dlc_t2_tick_1;
 237         unsigned char dlc_ti_tick_1;
 238         unsigned char dlc_t1_tick_2;
 239         unsigned char dlc_t2_tick_2;
 240         unsigned char dlc_ti_tick_2;
 241         unsigned char product_id[18];
 242 };
 243 
 244 struct srb_open_response {
 245         unsigned char command;
 246         unsigned char reserved1;
 247         unsigned char ret_code;
 248         unsigned char reserved2[3];
 249         unsigned short error_code;
 250         unsigned short asb_addr;
 251         unsigned short srb_addr;
 252         unsigned short arb_addr;
 253         unsigned short ssb_addr;
 254 };
 255 
 256 /* DIR_OPEN_ADAPTER options */
 257 
 258 #define OPEN_PASS_BCON_MAC 0x0100
 259 #define NUM_RCV_BUF 16
 260 #define RCV_BUF_LEN 136
 261 #define DHB_LENGTH 2048
 262 #define NUM_DHB 2
 263 #define DLC_MAX_SAP 2
 264 #define DLC_MAX_STA 1
 265 
 266 #define DLC_OPEN_SAP 0x15
 267 
 268 struct dlc_open_sap {
 269         unsigned char command;
 270         unsigned char reserved1;
 271         unsigned char ret_code;
 272         unsigned char reserved2;
 273         unsigned short station_id;
 274         unsigned char timer_t1;
 275         unsigned char timer_t2;
 276         unsigned char timer_ti;
 277         unsigned char maxout;
 278         unsigned char maxin;
 279         unsigned char maxout_incr;
 280         unsigned char max_retry_count;
 281         unsigned char gsap_max_mem;
 282         unsigned short max_i_field;
 283         unsigned char sap_value;
 284         unsigned char sap_options;
 285         unsigned char station_count;
 286         unsigned char sap_gsap_mem;
 287         unsigned char gsap[0];
 288 };
 289 
 290 /* DLC_OPEN_SAP options */
 291 
 292 #define MAX_I_FIELD 0x0088
 293 #define SAP_OPEN_IND_SAP 0x04
 294 #define SAP_OPEN_PRIORITY 0x20
 295 #define SAP_OPEN_STATION_CNT 0x1
 296 
 297 #define XMIT_DIR_FRAME 0x0a
 298 #define XMIT_UI_FRAME  0x0d
 299 #define XMIT_XID_CMD   0x0e
 300 #define XMIT_TEST_CMD  0x11
 301 
 302 struct srb_xmit {
 303         unsigned char command;
 304         unsigned char cmd_corr;
 305         unsigned char ret_code;
 306         unsigned char reserved1;
 307         unsigned short station_id;
 308 };
 309 
 310 #define DIR_INTERRUPT 0x00
 311 struct srb_interrupt {
 312         unsigned char command;
 313         unsigned char cmd_corr;
 314         unsigned char ret_code;
 315 };
 316 
 317 #define DIR_READ_LOG 0x08
 318 struct srb_read_log {
 319         unsigned char command;
 320         unsigned char reserved1;
 321         unsigned char ret_code;
 322         unsigned char reserved2;
 323         unsigned char line_errors;
 324         unsigned char internal_errors;
 325         unsigned char burst_errors;
 326         unsigned char A_C_errors;
 327         unsigned char abort_delimiters;
 328         unsigned char reserved3;
 329         unsigned char lost_frames;
 330         unsigned char recv_congest_count;
 331         unsigned char frame_copied_errors;
 332         unsigned char frequency_errors;
 333         unsigned char token_errors;
 334 };
 335 
 336 struct asb_xmit_resp {
 337         unsigned char command;
 338         unsigned char cmd_corr;
 339         unsigned char ret_code;
 340         unsigned char reserved;
 341         unsigned short station_id;
 342         unsigned short frame_length;
 343         unsigned char hdr_length;
 344         unsigned        char rsap_value;
 345 };
 346 
 347 #define XMIT_DATA_REQ 0x82
 348 struct arb_xmit_req {
 349         unsigned char command;
 350         unsigned char cmd_corr;
 351         unsigned char reserved1[2];
 352         unsigned short station_id;
 353         unsigned short dhb_address;
 354 };
 355 
 356 #define REC_DATA 0x81
 357 struct arb_rec_req {
 358         unsigned char command;
 359         unsigned char reserved1[3];
 360         unsigned short station_id;
 361         unsigned short rec_buf_addr;
 362         unsigned char lan_hdr_len;
 363         unsigned char dlc_hdr_len;
 364         unsigned short frame_len;
 365         unsigned char msg_type;
 366 };
 367 
 368 #define DATA_LOST 0x20
 369 struct asb_rec {
 370         unsigned char command;
 371         unsigned char reserved1;
 372         unsigned char ret_code;
 373         unsigned char reserved2;
 374         unsigned short station_id;
 375         unsigned short rec_buf_addr;
 376 };
 377 
 378 struct rec_buf {
 379         unsigned char reserved1[2];
 380         unsigned short buf_ptr;
 381         unsigned char reserved2;
 382         unsigned short buf_len;
 383         unsigned char data[0];
 384 };
 385 
 386 #define DLC_STATUS          0x83
 387 struct arb_dlc_status {
 388         unsigned char command;
 389         unsigned char reserved1[3];
 390         unsigned short station_id;
 391         unsigned short status;
 392         unsigned char frmr_data[5];
 393         unsigned char access_prio;
 394         unsigned char rem_addr[TR_ALEN];
 395         unsigned        char rsap_value;
 396 };
 397 
 398 #define RING_STAT_CHANGE    0x84
 399 struct arb_ring_stat_change {
 400         unsigned char command;
 401         unsigned char reserved1[5];
 402         unsigned short ring_status;
 403 };
 404 
 405 #define DIR_CLOSE_ADAPTER   0x04
 406 struct srb_close_adapter {
 407         unsigned char command;
 408         unsigned char reserved1;
 409         unsigned char ret_code;
 410 };
 411 
 412 #define DIR_MOD_OPEN_PARAMS 0x01
 413 #define DIR_SET_GRP_ADDR    0x06
 414 #define DIR_SET_FUNC_ADDR   0x07
 415 #define DLC_CLOSE_SAP       0x16
 416 
 417 
 418 #define SIGNAL_LOSS  0x8000
 419 #define HARD_ERROR   0x4000
 420 #define XMIT_BEACON  0x1000
 421 #define LOBE_FAULT   0x0800
 422 #define AUTO_REMOVAL 0x0400
 423 #define REMOVE_RECV  0x0100
 424 #define LOG_OVERFLOW 0x0080
 425 #define RING_RECOVER 0x0020
 426 

/* */