drivers/sound/ad1848.c

/* */
This source file includes following definitions.
ad_read
ad_write
wait_for_calibration
ad_mute
ad_unmute
ad_enter_MCE
ad_leave_MCE
ad1848_set_recmask
change_bits
ad1848_mixer_get
ad1848_mixer_set
ad1848_mixer_reset
ad1848_mixer_ioctl
ad1848_open
ad1848_close
set_speed
set_channels
set_format
ad1848_ioctl
ad1848_output_block
ad1848_start_input
ad1848_prepare_for_IO
ad1848_reset
ad1848_halt
ad1848_detect
ad1848_init
ad1848_interrupt
probe_ms_sound
attach_ms_sound
   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * Copyright by Hannu Savolainen 1994, 1995
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions are
  14  * met: 1. Redistributions of source code must retain the above copyright
  15  * notice, this list of conditions and the following disclaimer. 2.
  16  * Redistributions in binary form must reproduce the above copyright notice,
  17  * this list of conditions and the following disclaimer in the documentation
  18  * and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  21  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  22  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  23  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  26  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  27  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  * Modified:
  33  *  Riccardo Facchetti  24 Mar 1995
  34  *  - Added the Audio Excel DSP 16 initialization routine.
  35  */
  36 
  37 #define DEB(x)
  38 #define DEB1(x)
  39 #include "sound_config.h"
  40 
  41 #if defined(CONFIGURE_SOUNDCARD) && !defined(EXCLUDE_AD1848)
  42 
  43 #include "ad1848_mixer.h"
  44 
  45 #define IMODE_NONE              0
  46 #define IMODE_OUTPUT            1
  47 #define IMODE_INPUT             2
  48 #define IMODE_INIT              3
  49 #define IMODE_MIDI              4
  50 
  51 typedef struct
  52   {
  53     int             base;
  54     int             irq;
  55     int             dma_capture, dma_playback;
  56     int             dual_dma;   /* 1, when two DMA channels allocated */
  57     unsigned char   MCE_bit;
  58     unsigned char   saved_regs[16];
  59 
  60     int             speed;
  61     unsigned char   speed_bits;
  62     int             channels;
  63     int             audio_format;
  64     unsigned char   format_bits;
  65 
  66     int             xfer_count;
  67     int             irq_mode;
  68     int             intr_active;
  69     int             opened;
  70     char           *chip_name;
  71     int             mode;
  72 
  73     /* Mixer parameters */
  74     int             recmask;
  75     int             supported_devices;
  76     int             supported_rec_devices;
  77     unsigned short  levels[32];
  78   }
  79 
  80 ad1848_info;
  81 
  82 static int      nr_ad1848_devs = 0;
  83 static char     irq2dev[16] =
  84 {-1, -1, -1, -1, -1, -1, -1, -1,
  85  -1, -1, -1, -1, -1, -1, -1, -1};
  86 
  87 static char     mixer2codec[MAX_MIXER_DEV] =
  88 {0};
  89 
  90 static int      ad_format_mask[3 /*devc->mode */ ] =
  91 {
  92   0,
  93   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
  94   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM
  95 };
  96 
  97 static ad1848_info dev_info[MAX_AUDIO_DEV];
  98 
  99 #define io_Index_Addr(d)        ((d)->base)
 100 #define io_Indexed_Data(d)      ((d)->base+1)
 101 #define io_Status(d)            ((d)->base+2)
 102 #define io_Polled_IO(d)         ((d)->base+3)
 103 
 104 static int      ad1848_open (int dev, int mode);
 105 static void     ad1848_close (int dev);
 106 static int      ad1848_ioctl (int dev, unsigned int cmd, unsigned int arg, int local);
 107 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 108 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 109 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 110 static void     ad1848_reset (int dev);
 111 static void     ad1848_halt (int dev);
 112 void            ad1848_interrupt (INT_HANDLER_PARMS (irq, dummy));
 113 
 114 static int
 115 ad_read (ad1848_info * devc, int reg)
     /*  */
 116 {
 117   unsigned long   flags;
 118   int             x;
 119   int             timeout = 900000;
 120 
 121   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 122     timeout--;
 123 
 124   DISABLE_INTR (flags);
 125   OUTB ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 126   x = INB (io_Indexed_Data (devc));
 127   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 128   RESTORE_INTR (flags);
 129 
 130   return x;
 131 }
 132 
 133 static void
 134 ad_write (ad1848_info * devc, int reg, int data)
     /*  */
 135 {
 136   unsigned long   flags;
 137   int             timeout = 90000;
 138 
 139   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 140     timeout--;
 141 
 142   DISABLE_INTR (flags);
 143   OUTB ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 144   OUTB ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 145   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 146   RESTORE_INTR (flags);
 147 }
 148 
 149 static void
 150 wait_for_calibration (ad1848_info * devc)
     /*  */
 151 {
 152   int             timeout = 0;
 153 
 154   /*
 155      * Wait until the auto calibration process has finished.
 156      *
 157      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 158      * 2)       Wait until the ACI bit of I11 gets on and then off.
 159    */
 160 
 161   timeout = 100000;
 162   while (timeout > 0 && INB (devc->base) & 0x80)
 163     timeout--;
 164   if (INB (devc->base) & 0x80)
 165     printk ("ad1848: Auto calibration timed out(1).\n");
 166 
 167   timeout = 100;
 168   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 169     timeout--;
 170   if (!(ad_read (devc, 11) & 0x20))
 171     return;
 172 
 173   timeout = 20000;
 174   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 175     timeout--;
 176   if (ad_read (devc, 11) & 0x20)
 177     printk ("ad1848: Auto calibration timed out(3).\n");
 178 }
 179 
 180 static void
 181 ad_mute (ad1848_info * devc)
     /*  */
 182 {
 183   int             i;
 184   unsigned char   prev;
 185 
 186   /*
 187      * Save old register settings and mute output channels
 188    */
 189   for (i = 6; i < 8; i++)
 190     {
 191       prev = devc->saved_regs[i] = ad_read (devc, i);
 192       ad_write (devc, i, prev | 0x80);
 193     }
 194 }
 195 
 196 static void
 197 ad_unmute (ad1848_info * devc)
     /*  */
 198 {
 199   int             i;
 200 
 201   /*
 202      * Restore back old volume registers (unmute)
 203    */
 204   for (i = 6; i < 8; i++)
 205     {
 206       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 207     }
 208 }
 209 
 210 static void
 211 ad_enter_MCE (ad1848_info * devc)
     /*  */
 212 {
 213   unsigned long   flags;
 214   int             timeout = 1000;
 215   unsigned short  prev;
 216 
 217   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 218     timeout--;
 219 
 220   DISABLE_INTR (flags);
 221 
 222   devc->MCE_bit = 0x40;
 223   prev = INB (io_Index_Addr (devc));
 224   if (prev & 0x40)
 225     {
 226       RESTORE_INTR (flags);
 227       return;
 228     }
 229 
 230   OUTB (devc->MCE_bit, io_Index_Addr (devc));
 231   RESTORE_INTR (flags);
 232 }
 233 
 234 static void
 235 ad_leave_MCE (ad1848_info * devc)
     /*  */
 236 {
 237   unsigned long   flags;
 238   unsigned char   prev;
 239   int             timeout = 1000;
 240 
 241   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 242     timeout--;
 243 
 244   DISABLE_INTR (flags);
 245 
 246   devc->MCE_bit = 0x00;
 247   prev = INB (io_Index_Addr (devc));
 248   OUTB (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 249 
 250   if (prev & 0x40 == 0)         /* Not in MCE mode */
 251     {
 252       RESTORE_INTR (flags);
 253       return;
 254     }
 255 
 256   OUTB (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 257   wait_for_calibration (devc);
 258   RESTORE_INTR (flags);
 259 }
 260 
 261 
 262 static int
 263 ad1848_set_recmask (ad1848_info * devc, int mask)
     /*  */
 264 {
 265   unsigned char   recdev;
 266   int             i, n;
 267 
 268   mask &= devc->supported_rec_devices;
 269 
 270   n = 0;
 271   for (i = 0; i < 32; i++)      /* Count selected device bits */
 272     if (mask & (1 << i))
 273       n++;
 274 
 275   if (n == 0)
 276     mask = SOUND_MASK_MIC;
 277   else if (n != 1)              /* Too many devices selected */
 278     {
 279       mask &= ~devc->recmask;   /* Filter out active settings */
 280 
 281       n = 0;
 282       for (i = 0; i < 32; i++)  /* Count selected device bits */
 283         if (mask & (1 << i))
 284           n++;
 285 
 286       if (n != 1)
 287         mask = SOUND_MASK_MIC;
 288     }
 289 
 290   switch (mask)
 291     {
 292     case SOUND_MASK_MIC:
 293       recdev = 2;
 294       break;
 295 
 296     case SOUND_MASK_LINE:
 297     case SOUND_MASK_LINE3:
 298       recdev = 0;
 299       break;
 300 
 301     case SOUND_MASK_CD:
 302     case SOUND_MASK_LINE1:
 303       recdev = 1;
 304       break;
 305 
 306     default:
 307       mask = SOUND_MASK_MIC;
 308       recdev = 2;
 309     }
 310 
 311   recdev <<= 6;
 312   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 313   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 314 
 315   devc->recmask = mask;
 316   return mask;
 317 }
 318 
 319 static void
 320 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /*  */
 321 {
 322   unsigned char   mask;
 323   int             shift;
 324 
 325   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 326     newval = 100 - newval;
 327 
 328   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 329   shift = mix_devices[dev][chn].bitpos;
 330   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 331 
 332   *regval &= ~(mask << shift);  /* Clear bits */
 333   *regval |= (newval & mask) << shift;  /* Set new value */
 334 }
 335 
 336 static int
 337 ad1848_mixer_get (ad1848_info * devc, int dev)
     /*  */
 338 {
 339   if (!((1 << dev) & devc->supported_devices))
 340     return RET_ERROR (EINVAL);
 341 
 342   return devc->levels[dev];
 343 }
 344 
 345 static int
 346 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /*  */
 347 {
 348   int             left = value & 0x000000ff;
 349   int             right = (value & 0x0000ff00) >> 8;
 350 
 351   int             regoffs;
 352   unsigned char   val;
 353 
 354   if (left > 100)
 355     left = 100;
 356   if (right > 100)
 357     right = 100;
 358 
 359   if (dev > 31)
 360     return RET_ERROR (EINVAL);
 361 
 362   if (!(devc->supported_devices & (1 << dev)))
 363     return RET_ERROR (EINVAL);
 364 
 365   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 366     return RET_ERROR (EINVAL);
 367 
 368   /*
 369      * Set the left channel
 370    */
 371 
 372   regoffs = mix_devices[dev][LEFT_CHN].regno;
 373   val = ad_read (devc, regoffs);
 374   change_bits (&val, dev, LEFT_CHN, left);
 375   devc->levels[dev] = left | (left << 8);
 376   ad_write (devc, regoffs, val);
 377   devc->saved_regs[regoffs] = val;
 378 
 379   /*
 380      * Set the left right
 381    */
 382 
 383   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 384     return left | (left << 8);  /* Was just a mono channel */
 385 
 386   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 387   val = ad_read (devc, regoffs);
 388   change_bits (&val, dev, RIGHT_CHN, right);
 389   ad_write (devc, regoffs, val);
 390   devc->saved_regs[regoffs] = val;
 391 
 392   devc->levels[dev] = left | (right << 8);
 393   return left | (right << 8);
 394 }
 395 
 396 static void
 397 ad1848_mixer_reset (ad1848_info * devc)
     /*  */
 398 {
 399   int             i;
 400 
 401   devc->recmask = 0;
 402   if (devc->mode == 2)
 403     devc->supported_devices = MODE2_MIXER_DEVICES;
 404   else
 405     devc->supported_devices = MODE1_MIXER_DEVICES;
 406 
 407   devc->supported_rec_devices = MODE1_REC_DEVICES;
 408 
 409   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 410     ad1848_mixer_set (devc, i, devc->levels[i] = default_mixer_levels[i]);
 411   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 412 }
 413 
 414 static int
 415 ad1848_mixer_ioctl (int dev, unsigned int cmd, unsigned int arg)
     /*  */
 416 {
 417   ad1848_info    *devc;
 418 
 419   int             codec_dev = mixer2codec[dev];
 420 
 421   if (!codec_dev)
 422     return RET_ERROR (ENXIO);
 423 
 424   codec_dev--;
 425 
 426   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 427 
 428   if (((cmd >> 8) & 0xff) == 'M')
 429     {
 430       if (cmd & IOC_IN)
 431         switch (cmd & 0xff)
 432           {
 433           case SOUND_MIXER_RECSRC:
 434             return IOCTL_OUT (arg, ad1848_set_recmask (devc, IOCTL_IN (arg)));
 435             break;
 436 
 437           default:
 438             return IOCTL_OUT (arg, ad1848_mixer_set (devc, cmd & 0xff, IOCTL_IN (arg)));
 439           }
 440       else
 441         switch (cmd & 0xff)     /*
 442                                  * Return parameters
 443                                  */
 444           {
 445 
 446           case SOUND_MIXER_RECSRC:
 447             return IOCTL_OUT (arg, devc->recmask);
 448             break;
 449 
 450           case SOUND_MIXER_DEVMASK:
 451             return IOCTL_OUT (arg, devc->supported_devices);
 452             break;
 453 
 454           case SOUND_MIXER_STEREODEVS:
 455             return IOCTL_OUT (arg, devc->supported_devices &
 456                               ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 457             break;
 458 
 459           case SOUND_MIXER_RECMASK:
 460             return IOCTL_OUT (arg, devc->supported_rec_devices);
 461             break;
 462 
 463           case SOUND_MIXER_CAPS:
 464             return IOCTL_OUT (arg, SOUND_CAP_EXCL_INPUT);
 465             break;
 466 
 467           default:
 468             return IOCTL_OUT (arg, ad1848_mixer_get (devc, cmd & 0xff));
 469           }
 470     }
 471   else
 472     return RET_ERROR (EINVAL);
 473 }
 474 
 475 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 476 {
 477   {
 478     "Generic AD1848 codec",
 479     DMA_AUTOMODE,
 480     AFMT_U8,                    /* Will be set later */
 481     NULL,
 482     ad1848_open,
 483     ad1848_close,
 484     ad1848_output_block,
 485     ad1848_start_input,
 486     ad1848_ioctl,
 487     ad1848_prepare_for_IO,
 488     ad1848_prepare_for_IO,
 489     ad1848_reset,
 490     ad1848_halt,
 491     NULL,
 492     NULL
 493   }};
 494 
 495 static struct mixer_operations ad1848_mixer_operations =
 496 {
 497   "AD1848/CS4248/CS4231",
 498   ad1848_mixer_ioctl
 499 };
 500 
 501 static int
 502 ad1848_open (int dev, int mode)
     /*  */
 503 {
 504   int             err;
 505   ad1848_info    *devc = NULL;
 506   unsigned long   flags;
 507 
 508   DEB (printk ("ad1848_open(int mode = %X)\n", mode));
 509 
 510   if (dev < 0 || dev >= num_audiodevs)
 511     return RET_ERROR (ENXIO);
 512 
 513   devc = (ad1848_info *) audio_devs[dev]->devc;
 514 
 515   DISABLE_INTR (flags);
 516   if (devc->opened)
 517     {
 518       RESTORE_INTR (flags);
 519       printk ("ad1848: Already opened\n");
 520       return RET_ERROR (EBUSY);
 521     }
 522 
 523   if (devc->irq)                /* Not managed by another driver */
 524     if ((err = snd_set_irq_handler (devc->irq, ad1848_interrupt,
 525                                     audio_devs[dev]->name)) < 0)
 526       {
 527         printk ("ad1848: IRQ in use\n");
 528         RESTORE_INTR (flags);
 529         return err;
 530       }
 531 
 532 /*
 533  * Allocate DMA
 534  */
 535 
 536   if (mode & OPEN_WRITE)
 537     audio_devs[dev]->dmachan = devc->dma_playback;
 538   else
 539     audio_devs[dev]->dmachan = devc->dma_capture;
 540 
 541   if (DMAbuf_open_dma (dev) < 0)
 542     {
 543       RESTORE_INTR (flags);
 544       if (devc->irq)            /* Don't leave IRQ reserved */
 545         snd_release_irq (devc->irq);
 546 
 547       printk ("ad1848: DMA in use\n");
 548       return RET_ERROR (EBUSY);
 549     }
 550 
 551   devc->dual_dma = 0;
 552 
 553   if (devc->dma_capture != devc->dma_playback && mode == OPEN_READWRITE)
 554     {
 555       devc->dual_dma = 1;
 556 
 557       if (ALLOC_DMA_CHN (devc->dma_capture, "Sound System (capture)"))
 558         {
 559           if (devc->irq)        /* Don't leave IRQ reserved */
 560             snd_release_irq (devc->irq);
 561           DMAbuf_close_dma (dev);
 562           return RET_ERROR (EBUSY);
 563         }
 564     }
 565 
 566   devc->intr_active = 0;
 567   devc->opened = 1;
 568   RESTORE_INTR (flags);
 569 /*
 570  * Mute output until the playback really starts. This decreases clicking.
 571  */
 572   ad_mute (devc);
 573 
 574   return 0;
 575 }
 576 
 577 static void
 578 ad1848_close (int dev)
     /*  */
 579 {
 580   unsigned long   flags;
 581   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 582 
 583   DEB (printk ("ad1848_close(void)\n"));
 584 
 585   DISABLE_INTR (flags);
 586 
 587   devc->intr_active = 0;
 588   if (devc->irq)                /* Not managed by another driver */
 589     snd_release_irq (devc->irq);
 590   ad1848_reset (dev);
 591   DMAbuf_close_dma (dev);
 592 
 593   if (devc->dual_dma)           /* Release the second DMA channel */
 594     {
 595       if (audio_devs[dev]->dmachan == devc->dma_playback)
 596         RELEASE_DMA_CHN (devc->dma_capture);
 597       else
 598         RELEASE_DMA_CHN (devc->dma_playback);
 599     }
 600 
 601   devc->opened = 0;
 602 
 603   ad_unmute (devc);
 604   RESTORE_INTR (flags);
 605 }
 606 
 607 static int
 608 set_speed (ad1848_info * devc, int arg)
     /*  */
 609 {
 610   /*
 611      * The sampling speed is encoded in the least significant nible of I8. The
 612      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 613      * three bits select the divisor (indirectly):
 614      *
 615      * The available speeds are in the following table. Keep the speeds in
 616      * the increasing order.
 617    */
 618   typedef struct
 619   {
 620     int             speed;
 621     unsigned char   bits;
 622   }
 623   speed_struct;
 624 
 625   static speed_struct speed_table[] =
 626   {
 627     {5510, (0 << 1) | 1},
 628     {5510, (0 << 1) | 1},
 629     {6620, (7 << 1) | 1},
 630     {8000, (0 << 1) | 0},
 631     {9600, (7 << 1) | 0},
 632     {11025, (1 << 1) | 1},
 633     {16000, (1 << 1) | 0},
 634     {18900, (2 << 1) | 1},
 635     {22050, (3 << 1) | 1},
 636     {27420, (2 << 1) | 0},
 637     {32000, (3 << 1) | 0},
 638     {33075, (6 << 1) | 1},
 639     {37800, (4 << 1) | 1},
 640     {44100, (5 << 1) | 1},
 641     {48000, (6 << 1) | 0}
 642   };
 643 
 644   int             i, n, selected = -1;
 645 
 646   n = sizeof (speed_table) / sizeof (speed_struct);
 647 
 648   if (arg < speed_table[0].speed)
 649     selected = 0;
 650   if (arg > speed_table[n - 1].speed)
 651     selected = n - 1;
 652 
 653   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 654     if (speed_table[i].speed == arg)
 655       selected = i;
 656     else if (speed_table[i].speed > arg)
 657       {
 658         int             diff1, diff2;
 659 
 660         diff1 = arg - speed_table[i - 1].speed;
 661         diff2 = speed_table[i].speed - arg;
 662 
 663         if (diff1 < diff2)
 664           selected = i - 1;
 665         else
 666           selected = i;
 667       }
 668 
 669   if (selected == -1)
 670     {
 671       printk ("ad1848: Can't find speed???\n");
 672       selected = 3;
 673     }
 674 
 675   devc->speed = speed_table[selected].speed;
 676   devc->speed_bits = speed_table[selected].bits;
 677   return devc->speed;
 678 }
 679 
 680 static int
 681 set_channels (ad1848_info * devc, int arg)
     /*  */
 682 {
 683   if (arg != 1 && arg != 2)
 684     return devc->channels;
 685 
 686   devc->channels = arg;
 687   return arg;
 688 }
 689 
 690 static int
 691 set_format (ad1848_info * devc, int arg)
     /*  */
 692 {
 693 
 694   static struct format_tbl
 695   {
 696     int             format;
 697     unsigned char   bits;
 698   }
 699   format2bits[] =
 700   {
 701     {
 702       0, 0
 703     }
 704     ,
 705     {
 706       AFMT_MU_LAW, 1
 707     }
 708     ,
 709     {
 710       AFMT_A_LAW, 3
 711     }
 712     ,
 713     {
 714       AFMT_IMA_ADPCM, 5
 715     }
 716     ,
 717     {
 718       AFMT_U8, 0
 719     }
 720     ,
 721     {
 722       AFMT_S16_LE, 2
 723     }
 724     ,
 725     {
 726       AFMT_S16_BE, 6
 727     }
 728     ,
 729     {
 730       AFMT_S8, 0
 731     }
 732     ,
 733     {
 734       AFMT_U16_LE, 0
 735     }
 736     ,
 737     {
 738       AFMT_U16_BE, 0
 739     }
 740   };
 741   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 742 
 743   if (!(arg & ad_format_mask[devc->mode]))
 744     arg = AFMT_U8;
 745 
 746   devc->audio_format = arg;
 747 
 748   for (i = 0; i < n; i++)
 749     if (format2bits[i].format == arg)
 750       {
 751         if ((devc->format_bits = format2bits[i].bits) == 0)
 752           return devc->audio_format = AFMT_U8;  /* Was not supported */
 753 
 754         return arg;
 755       }
 756 
 757   /* Still hanging here. Something must be terribly wrong */
 758   devc->format_bits = 0;
 759   return devc->audio_format = AFMT_U8;
 760 }
 761 
 762 static int
 763 ad1848_ioctl (int dev, unsigned int cmd, unsigned int arg, int local)
     /*  */
 764 {
 765   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 766 
 767   switch (cmd)
 768     {
 769     case SOUND_PCM_WRITE_RATE:
 770       if (local)
 771         return set_speed (devc, arg);
 772       return IOCTL_OUT (arg, set_speed (devc, IOCTL_IN (arg)));
 773 
 774     case SOUND_PCM_READ_RATE:
 775       if (local)
 776         return devc->speed;
 777       return IOCTL_OUT (arg, devc->speed);
 778 
 779     case SNDCTL_DSP_STEREO:
 780       if (local)
 781         return set_channels (devc, arg + 1) - 1;
 782       return IOCTL_OUT (arg, set_channels (devc, IOCTL_IN (arg) + 1) - 1);
 783 
 784     case SOUND_PCM_WRITE_CHANNELS:
 785       if (local)
 786         return set_channels (devc, arg);
 787       return IOCTL_OUT (arg, set_channels (devc, IOCTL_IN (arg)));
 788 
 789     case SOUND_PCM_READ_CHANNELS:
 790       if (local)
 791         return devc->channels;
 792       return IOCTL_OUT (arg, devc->channels);
 793 
 794     case SNDCTL_DSP_SAMPLESIZE:
 795       if (local)
 796         return set_format (devc, arg);
 797       return IOCTL_OUT (arg, set_format (devc, IOCTL_IN (arg)));
 798 
 799     case SOUND_PCM_READ_BITS:
 800       if (local)
 801         return devc->audio_format;
 802       return IOCTL_OUT (arg, devc->audio_format);
 803 
 804     default:;
 805     }
 806   return RET_ERROR (EINVAL);
 807 }
 808 
 809 static void
 810 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 811 {
 812   unsigned long   flags, cnt;
 813   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 814 
 815   cnt = count;
 816 
 817   audio_devs[dev]->dmachan = devc->dma_playback;
 818 
 819   if (devc->audio_format == AFMT_IMA_ADPCM)
 820     {
 821       cnt /= 4;
 822     }
 823   else
 824     {
 825       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 826         cnt >>= 1;
 827     }
 828   if (devc->channels > 1)
 829     cnt >>= 1;
 830   cnt--;
 831 
 832   if (audio_devs[dev]->flags & DMA_AUTOMODE &&
 833       intrflag &&
 834       cnt == devc->xfer_count)
 835     {
 836       devc->irq_mode = IMODE_OUTPUT;
 837       devc->intr_active = 1;
 838       return;                   /*
 839                                  * Auto DMA mode on. No need to react
 840                                  */
 841     }
 842   DISABLE_INTR (flags);
 843 
 844   if (dma_restart)
 845     {
 846       /* ad1848_halt (dev); */
 847       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 848     }
 849 
 850   ad_enter_MCE (devc);
 851 
 852   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 853   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 854 
 855   if (devc->dma_playback == devc->dma_capture)
 856     {
 857       ad_write (devc, 9, 0x0d); /*
 858                                  * Playback enable, single DMA channel mode,
 859                                  * auto calibration on.
 860                                  */
 861     }
 862   else
 863     {
 864       ad_write (devc, 9, 0x09); /*
 865                                  * Playback enable, dual DMA channel mode.
 866                                  * auto calibration on.
 867                                  */
 868     }
 869 
 870   ad_leave_MCE (devc);          /*
 871                                  * Starts the calibration process and
 872                                  * enters playback mode after it.
 873                                  */
 874   ad_unmute (devc);
 875 
 876   devc->xfer_count = cnt;
 877   devc->irq_mode = IMODE_OUTPUT;
 878   devc->intr_active = 1;
 879   INB (io_Status (devc));
 880   OUTB (0, io_Status (devc));   /* Clear pending interrupts */
 881   RESTORE_INTR (flags);
 882 
 883 }
 884 
 885 static void
 886 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 887 {
 888   unsigned long   flags, cnt;
 889   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 890 
 891   audio_devs[dev]->dmachan = devc->dma_capture;
 892 
 893   cnt = count;
 894   if (devc->audio_format == AFMT_IMA_ADPCM)
 895     {
 896       cnt /= 4;
 897     }
 898   else
 899     {
 900       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 901         cnt >>= 1;
 902     }
 903   if (devc->channels > 1)
 904     cnt >>= 1;
 905   cnt--;
 906 
 907   if (audio_devs[dev]->flags & DMA_AUTOMODE &&
 908       intrflag &&
 909       cnt == devc->xfer_count)
 910     {
 911       devc->irq_mode = IMODE_INPUT;
 912       devc->intr_active = 1;
 913       return;                   /*
 914                                  * Auto DMA mode on. No need to react
 915                                  */
 916     }
 917   DISABLE_INTR (flags);
 918 
 919   if (dma_restart)
 920     {
 921       /* ad1848_halt (dev); */
 922       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 923     }
 924 
 925   ad_enter_MCE (devc);
 926 
 927   if (devc->dma_playback == devc->dma_capture)  /* Single DMA channel mode */
 928     {
 929       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 930       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 931 
 932       ad_write (devc, 9, 0x0e); /*
 933                                  * Capture enable, single DMA channel mode,
 934                                  * auto calibration on.
 935                                  */
 936     }
 937   else
 938     /* Dual DMA channel mode */
 939     {
 940       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 941       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 942 
 943       ad_write (devc, 9, 0x0a); /*
 944                                  * Capture enable, dual DMA channel mode,
 945                                  * auto calibration on.
 946                                  */
 947     }
 948 
 949   ad_leave_MCE (devc);          /*
 950                                  * Starts the calibration process and
 951                                  * enters playback mode after it.
 952                                  */
 953   ad_unmute (devc);
 954 
 955   devc->xfer_count = cnt;
 956   devc->irq_mode = IMODE_INPUT;
 957   devc->intr_active = 1;
 958   INB (io_Status (devc));
 959   OUTB (0, io_Status (devc));   /* Clear interrupt status */
 960   RESTORE_INTR (flags);
 961 }
 962 
 963 static int
 964 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /*  */
 965 {
 966   int             timeout;
 967   unsigned char   fs;
 968   unsigned long   flags;
 969   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 970 
 971   DISABLE_INTR (flags);
 972   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 973   fs = devc->speed_bits | (devc->format_bits << 5);
 974 
 975   if (devc->channels > 1)
 976     fs |= 0x10;
 977 
 978   ad_write (devc, 8, fs);
 979   /*
 980    * Write to I8 starts resyncronization. Wait until it completes.
 981    */
 982   timeout = 10000;
 983   while (timeout > 0 && INB (devc->base) == 0x80)
 984     timeout--;
 985 
 986   /*
 987      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
 988    */
 989   if (devc->mode == 2)
 990     {
 991       ad_write (devc, 28, fs);
 992 
 993       /*
 994          * Write to I28 starts resyncronization. Wait until it completes.
 995        */
 996       timeout = 10000;
 997       while (timeout > 0 && INB (devc->base) == 0x80)
 998         timeout--;
 999 
1000     }
1001 
1002   ad_leave_MCE (devc);          /*
1003                                  * Starts the calibration process.
1004                                  */
1005   RESTORE_INTR (flags);
1006   devc->xfer_count = 0;
1007   return 0;
1008 }
1009 
1010 static void
1011 ad1848_reset (int dev)
     /*  */
1012 {
1013   ad1848_halt (dev);
1014 }
1015 
1016 static void
1017 ad1848_halt (int dev)
     /*  */
1018 {
1019   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1020 
1021   ad_mute (devc);
1022   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1023   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1024 
1025   ad_enter_MCE (devc);
1026   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1027   ad_write (devc, 15, 0);       /* Clear DMA counter */
1028   ad_write (devc, 14, 0);       /* Clear DMA counter */
1029 
1030   if (devc->mode == 2)
1031     {
1032       ad_write (devc, 30, 0);   /* Clear DMA counter */
1033       ad_write (devc, 31, 0);   /* Clear DMA counter */
1034     }
1035 
1036   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1037 
1038   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1039   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1040   ad_leave_MCE (devc);
1041 
1042   DMAbuf_reset_dma (dev);
1043 }
1044 
1045 int
1046 ad1848_detect (int io_base)
     /*  */
1047 {
1048 
1049   unsigned char   tmp;
1050   int             i;
1051   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1052   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1053 
1054   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1055     {
1056       DDB (printk ("ad1848 detect error - step 0\n"));
1057       return 0;
1058     }
1059 
1060   devc->base = io_base;
1061   devc->MCE_bit = 0x40;
1062   devc->irq = 0;
1063   devc->dma_capture = 0;
1064   devc->dma_playback = 0;
1065   devc->opened = 0;
1066   devc->chip_name = "AD1848";
1067   devc->mode = 1;               /* MODE1 = original AD1848 */
1068 
1069   /*
1070      * Check that the I/O address is in use.
1071      *
1072      * The bit 0x80 of the base I/O port is known to be 0 after the
1073      * chip has performed it's power on initialization. Just assume
1074      * this has happened before the OS is starting.
1075      *
1076      * If the I/O address is unused, it typically returns 0xff.
1077    */
1078 
1079   if ((INB (devc->base) & 0x80) != 0x00)        /* Not a AD1884 */
1080     {
1081       DDB (printk ("ad1848 detect error - step A\n"));
1082       return 0;
1083     }
1084 
1085   /*
1086      * Test if it's possible to change contents of the indirect registers.
1087      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1088      * so try to avoid using it.
1089    */
1090 
1091   ad_write (devc, 0, 0xaa);
1092   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1093 
1094   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1095     {
1096       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1097       return 0;
1098     }
1099 
1100   ad_write (devc, 0, 0x45);
1101   ad_write (devc, 1, 0xaa);
1102 
1103   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1104     {
1105       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1106       return 0;
1107     }
1108 
1109   /*
1110      * The indirect register I12 has some read only bits. Lets
1111      * try to change them.
1112    */
1113 
1114   tmp = ad_read (devc, 12);
1115   ad_write (devc, 12, (~tmp) & 0x0f);
1116 
1117   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1118     {
1119       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1120       return 0;
1121     }
1122 
1123   /*
1124      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1125      *   0x01=RevB and 0x0A=RevC.
1126    */
1127 
1128   /*
1129      * The original AD1848/CS4248 has just 15 indirect registers. This means
1130      * that I0 and I16 should return the same value (etc.).
1131      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1132      * with CS4231.
1133    */
1134 
1135   ad_write (devc, 12, 0);       /* Mode2=disabled */
1136 
1137   for (i = 0; i < 16; i++)
1138     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1139       {
1140         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1141         return 0;
1142       }
1143 
1144   /*
1145      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1146      * The bit 0x80 is always 1 in CS4248 and CS4231.
1147    */
1148 
1149   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1150 
1151   tmp1 = ad_read (devc, 12);
1152   if (tmp1 & 0x80)
1153     devc->chip_name = "CS4248"; /* Our best knowledge just now */
1154 
1155   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1156     {
1157       /*
1158          *      CS4231 detected - is it?
1159          *
1160          *      Verify that setting I0 doesn't change I16.
1161        */
1162       ad_write (devc, 16, 0);   /* Set I16 to known value */
1163 
1164       ad_write (devc, 0, 0x45);
1165       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1166         {
1167 
1168           ad_write (devc, 0, 0xaa);
1169           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1170             {
1171               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1172               return 0;
1173             }
1174 
1175           /*
1176              * Verify that some bits of I25 are read only.
1177            */
1178 
1179           tmp1 = ad_read (devc, 25);    /* Original bits */
1180           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1181           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1182             {
1183               /*
1184                  *      It's a CS4231
1185                */
1186               devc->chip_name = "CS4231";
1187 
1188 
1189 #ifdef MOZART_PORT
1190               if (devc->base != MOZART_PORT + 4)
1191 #endif
1192                 devc->mode = 2;
1193 
1194 
1195             }
1196           ad_write (devc, 25, tmp1);    /* Restore bits */
1197         }
1198     }
1199 
1200   return 1;
1201 }
1202 
1203 void
1204 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture)
     /*  */
1205 {
1206   /*
1207      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1208      *   so that this driver doesn't need to allocate/deallocate it.
1209      *   The actually used IRQ is ABS(irq).
1210    */
1211 
1212   /*
1213      * Initial values for the indirect registers of CS4248/AD1848.
1214    */
1215   static int      init_values[] =
1216   {
1217     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x80, 0x80,
1218     0x00, 0x08, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1219 
1220   /* Positions 16 to 31 just for CS4231 */
1221     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1222     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1223   };
1224   int             i, my_dev;
1225   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1226 
1227   if (!ad1848_detect (io_base))
1228     return;
1229 
1230   devc->irq = (irq > 0) ? irq : 0;
1231   devc->dma_playback = dma_playback;
1232 
1233   if (devc->mode == 2)
1234     devc->dma_capture = dma_capture;
1235   else
1236     devc->dma_capture = dma_playback;   /* Use just single DMA */
1237 
1238   devc->opened = 0;
1239 
1240   if (nr_ad1848_devs != 0)
1241     {
1242       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1243               (char *) &ad1848_pcm_operations[0],
1244               sizeof (struct audio_operations));
1245     }
1246 
1247   for (i = 0; i < 16; i++)
1248     ad_write (devc, i, init_values[i]);
1249 
1250   ad_mute (devc);               /* Initialize some variables */
1251   ad_unmute (devc);             /* Leave it unmuted now */
1252 
1253   if (devc->mode == 2)
1254     {
1255       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1256       for (i = 16; i < 32; i++)
1257         ad_write (devc, i, init_values[i]);
1258     }
1259 
1260   OUTB (0, io_Status (devc));   /* Clear pending interrupts */
1261 
1262   if (name[0] != 0)
1263     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1264              "%s (%s)", name, devc->chip_name);
1265   else
1266     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1267              "Generic audio codec (%s)", devc->chip_name);
1268 
1269   printk (" <%s>", ad1848_pcm_operations[nr_ad1848_devs].name);
1270 
1271   if (num_audiodevs < MAX_AUDIO_DEV)
1272     {
1273       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1274       if (irq > 0)
1275         irq2dev[irq] = my_dev;
1276       else if (irq < 0)
1277         irq2dev[-irq] = my_dev;
1278 
1279       audio_devs[my_dev]->dmachan = dma_playback;
1280       audio_devs[my_dev]->buffcount = 1;
1281       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE * 2;
1282       audio_devs[my_dev]->devc = devc;
1283       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1284       nr_ad1848_devs++;
1285 
1286       /*
1287          * Toggle the MCE bit. It completes the initialization phase.
1288        */
1289 
1290       ad_enter_MCE (devc);      /* In case the bit was off */
1291       ad_leave_MCE (devc);
1292 
1293       if (num_mixers < MAX_MIXER_DEV)
1294         {
1295           mixer2codec[num_mixers] = my_dev + 1;
1296           audio_devs[my_dev]->mixer_dev = num_mixers;
1297           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1298           ad1848_mixer_reset (devc);
1299         }
1300     }
1301   else
1302     printk ("AD1848: Too many PCM devices available\n");
1303 }
1304 
1305 void
1306 ad1848_interrupt (INT_HANDLER_PARMS (irq, dummy))
     /*  */
1307 {
1308   unsigned char   status;
1309   ad1848_info    *devc;
1310   int             dev;
1311 
1312   if (irq < 0 || irq > 15)
1313     return;                     /* Bogus irq */
1314   dev = irq2dev[irq];
1315   if (dev < 0 || dev >= num_audiodevs)
1316     return;                     /* Bogus dev */
1317 
1318   devc = (ad1848_info *) audio_devs[dev]->devc;
1319   status = INB (io_Status (devc));
1320 
1321   if (status == 0x80)
1322     printk ("ad1848_interrupt: Why?\n");
1323 
1324   if (status & 0x01)
1325     {
1326       if (devc->opened && devc->irq_mode == IMODE_OUTPUT)
1327         {
1328           DMAbuf_outputintr (dev, 1);
1329         }
1330 
1331       if (devc->opened && devc->irq_mode == IMODE_INPUT)
1332         DMAbuf_inputintr (dev);
1333     }
1334 
1335   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1336 
1337   status = INB (io_Status (devc));
1338   if (status == 0x80 || status & 0x01)
1339     {
1340       printk ("ad1848: Problems when clearing interrupt, status=%x\n", status);
1341       OUTB (0, io_Status (devc));       /* Try again */
1342     }
1343 }
1344 
1345 /*
1346  * Some extra code for the MS Sound System
1347  */
1348 
1349 int
1350 probe_ms_sound (struct address_info *hw_config)
     /*  */
1351 {
1352 #if !defined(EXCLUDE_AEDSP16) && defined(AEDSP16_MSS)
1353   /*
1354      * Initialize Audio Excel DSP 16 to MSS: before any operation
1355      * we must enable MSS I/O ports.
1356    */
1357 
1358   InitAEDSP16_MSS (hw_config);
1359 #endif
1360 
1361   /*
1362      * Check if the IO port returns valid signature. The original MS Sound
1363      * system returns 0x04 while some cards (AudioTriX Pro for example)
1364      * return 0x00.
1365    */
1366 
1367   if ((INB (hw_config->io_base + 3) & 0x3f) != 0x04 &&
1368       (INB (hw_config->io_base + 3) & 0x3f) != 0x00)
1369     {
1370       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1371                    hw_config->io_base, INB (hw_config->io_base + 3)));
1372       return 0;
1373     }
1374 
1375   if (hw_config->irq > 11)
1376     {
1377       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1378       return 0;
1379     }
1380 
1381   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1382     {
1383       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1384       return 0;
1385     }
1386 
1387   /*
1388      * Check that DMA0 is not in use with a 8 bit board.
1389    */
1390 
1391   if (hw_config->dma == 0 && INB (hw_config->io_base + 3) & 0x80)
1392     {
1393       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1394       return 0;
1395     }
1396 
1397   if (hw_config->irq > 7 && hw_config->irq != 9 && INB (hw_config->io_base + 3) & 0x80)
1398     {
1399       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1400       return 0;
1401     }
1402 
1403   return ad1848_detect (hw_config->io_base + 4);
1404 }
1405 
1406 long
1407 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /*  */
1408 {
1409   static char     interrupt_bits[12] =
1410   {
1411     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1412   };
1413   char            bits;
1414 
1415   static char     dma_bits[4] =
1416   {
1417     1, 2, 0, 3
1418   };
1419 
1420   int             config_port = hw_config->io_base + 0, version_port = hw_config->io_base + 3;
1421 
1422   if (!ad1848_detect (hw_config->io_base + 4))
1423     return mem_start;
1424 
1425   /*
1426      * Set the IRQ and DMA addresses.
1427    */
1428 
1429   bits = interrupt_bits[hw_config->irq];
1430   if (bits == -1)
1431     return mem_start;
1432 
1433   OUTB (bits | 0x40, config_port);
1434   if ((INB (version_port) & 0x40) == 0)
1435     printk ("[IRQ Conflict?]");
1436 
1437   OUTB (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1438 
1439   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1440                hw_config->irq,
1441                hw_config->dma,
1442                hw_config->dma);
1443   return mem_start;
1444 }
1445 
1446 #endif
/* */
root/drivers/sound/ad1848.c

DEFINITIONS
