This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
1
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8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/bios32.h>
13 #include <linux/pci.h>
14 #include <linux/string.h>
15
16 #include <asm/page.h>
17
18 struct pci_bus pci_root;
19 struct pci_dev *pci_devices = 0;
20
21
22
23
24
25
26
27
28
29
30
31 #define DEVICE(vid,did,name) \
32 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
33
34 #define BRIDGE(vid,did,name,bridge) \
35 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
36
37 struct pci_dev_info dev_info[] = {
38 DEVICE( NCR, NCR_53C810, "53c810"),
39 DEVICE( NCR, NCR_53C815, "53c815"),
40 DEVICE( NCR, NCR_53C820, "53c820"),
41 DEVICE( NCR, NCR_53C825, "53c825"),
42 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
43 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
44 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
45 DEVICE( DPT, DPT, "SmartCache/Raid"),
46 DEVICE( S3, S3_864_1, "Vision 864-P"),
47 DEVICE( S3, S3_864_2, "Vision 864-P"),
48 DEVICE( S3, S3_868, "Vision 868"),
49 DEVICE( S3, S3_928, "Vision 928-P"),
50 DEVICE( S3, S3_964_1, "Vision 964-P"),
51 DEVICE( S3, S3_964_2, "Vision 964-P"),
52 DEVICE( S3, S3_811, "Trio32/Trio64"),
53 DEVICE( S3, S3_968, "Vision 968"),
54 DEVICE( OPTI, OPTI_82C822, "82C822"),
55 DEVICE( OPTI, OPTI_82C621, "82C621"),
56 DEVICE( OPTI, OPTI_82C557, "82C557"),
57 DEVICE( OPTI, OPTI_82C558, "82C558"),
58 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
59 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
60 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
61 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
62 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
65 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
66 DEVICE( DEC, DEC_FDDI, "DEFPA"),
67 DEVICE( DEC, DEC_BRD, "DC21050"),
68 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
69 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
70 DEVICE( INTEL, INTEL_82378, "82378IB"),
71 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
72 DEVICE( INTEL, INTEL_82375, "82375EB"),
73 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
74 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
75 DEVICE( INTEL, INTEL_82437, "82437 Triton"),
76 DEVICE( INTEL, INTEL_82371, "82471 Triton"),
77 DEVICE( INTEL, INTEL_82438, "82438"),
78 DEVICE( INTEL, INTEL_7116, "SAA7116"),
79 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
80 DEVICE( ATI, ATI_M32, "Mach 32"),
81 DEVICE( ATI, ATI_M64, "Mach 64"),
82 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
83 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
84 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
85 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
86 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
87 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
88 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
89 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
90 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
91 DEVICE( N9, N9_I128, "Imagine 128"),
92 DEVICE( AI, AI_M1435, "M1435"),
93 DEVICE( AL, AL_M1445, "M1445"),
94 DEVICE( AL, AL_M1449, "M1449"),
95 DEVICE( AL, AL_M1451, "M1451"),
96 DEVICE( AL, AL_M4803, "M4803"),
97 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
98 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
99 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
100 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
101 DEVICE( CMD, CMD_640, "640A"),
102 DEVICE( VISION, VISION_QD8500, "QD-8500"),
103 DEVICE( VISION, VISION_QD8580, "QD-8580"),
104 DEVICE( AMD, AMD_LANCE, "79C970"),
105 DEVICE( AMD, AMD_SCSI, "53C974"),
106 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
107 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
108 DEVICE( ADL, ADL_2301, "2301"),
109 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
110 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
111 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
112 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
113 DEVICE( NS, NS_87410, "87410"),
114 DEVICE( VIA, VIA_82C505, "VT 82C505"),
115 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
116 DEVICE( VIA, VIA_82C561, "VT 82C561"),
117 DEVICE( SI, SI_496, "85C496"),
118 DEVICE( SI, SI_501, "85C501"),
119 DEVICE( SI, SI_503, "85C503"),
120 DEVICE( SI, SI_601, "85C601"),
121 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
122 DEVICE( IMS, IMS_8849, "8849"),
123 DEVICE( ZEINET, ZEINET_1221, "1221"),
124 DEVICE( EF, EF_ATM, "155P-MF1"),
125 DEVICE( HER, HER_STING, "Stingray"),
126 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
127 DEVICE( CT, CT_65545, "65545"),
128 DEVICE( FD, FD_36C70, "TMC-18C30"),
129 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
130 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
131 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
132 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
133 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
134 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
135 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
136 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
137 DEVICE( X, X_AGX016, "ITT AGX016"),
138 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b")
139 };
140
141
142 #ifdef CONFIG_PCI_OPTIMIZE
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159 struct optimization_type {
160 char *type;
161 char *off;
162 char *on;
163 } bridge_optimization[] = {
164 {"Cache L2", "write trough", "write back"},
165 {"CPU-PCI posted write", "off", "on"},
166 {"CPU-Memory posted write", "off", "on"},
167 {"PCI-Memory posted write", "off", "on"},
168 {"PCI burst", "off", "on"}
169 };
170
171 #define NUM_OPTIMIZATIONS \
172 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
173
174 struct bridge_mapping_type {
175 unsigned char addr;
176 unsigned char mask;
177 unsigned char value;
178 } bridge_mapping[] = {
179
180
181
182
183
184
185
186 {0x0 ,0x02 ,0x02 },
187 {0x53 ,0x02 ,0x02 },
188 {0x53 ,0x01 ,0x01 },
189 {0x54 ,0x01 ,0x01 },
190 {0x54 ,0x02 ,0x02 },
191
192
193
194
195
196 {0x50 ,0x10 ,0x00 },
197 {0x51 ,0x40 ,0x40 },
198 {0x0 ,0x0 ,0x0 },
199 {0x0 ,0x0 ,0x0 },
200 {0x0 ,0x0 ,0x0 },
201
202
203
204
205
206
207 {0x0 ,0x1 ,0x1 },
208 {0x0 ,0x2 ,0x0 },
209 {0x0 ,0x0 ,0x0 },
210 {0x0 ,0x0 ,0x0 },
211 {0x0 ,0x0 ,0x0 }
212 };
213
214 #endif
215
216
217
218
219
220
221 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
222 {
223 int i;
224
225 for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
226 if (dev_info[i].vendor == vendor &&
227 dev_info[i].device == dev)
228 {
229 return &dev_info[i];
230 }
231 }
232 return 0;
233 }
234
235
236 char *pci_strbioserr (int error)
237 {
238 switch (error) {
239 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
240 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
241 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
242 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
243 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
244 case PCIBIOS_SET_FAILED: return "SET_FAILED";
245 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
246 default: return "Unknown error status";
247 }
248 }
249
250
251 const char *pci_strclass (unsigned int class)
252 {
253 switch (class >> 8) {
254 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
255 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
256
257 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
258 case PCI_CLASS_STORAGE_IDE: return "IDE controller";
259 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
260 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
261 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
262
263 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
264 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
265 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
266 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
267
268 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
269 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
270 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
271
272 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
273 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
274 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
275
276 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
277 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
278 case PCI_CLASS_MEMORY_OTHER: return "Memory";
279
280 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
281 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
282 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
283 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
284 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
285 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
286 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
287
288 default: return "Unknown class";
289 }
290 }
291
292
293 const char *pci_strvendor(unsigned int vendor)
294 {
295 switch (vendor) {
296 case PCI_VENDOR_ID_NCR: return "NCR";
297 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
298 case PCI_VENDOR_ID_DPT: return "DPT";
299 case PCI_VENDOR_ID_S3: return "S3 Inc.";
300 case PCI_VENDOR_ID_OPTI: return "OPTI";
301 case PCI_VENDOR_ID_UMC: return "UMC";
302 case PCI_VENDOR_ID_DEC: return "DEC";
303 case PCI_VENDOR_ID_MATROX: return "Matrox";
304 case PCI_VENDOR_ID_INTEL: return "Intel";
305 case PCI_VENDOR_ID_SMC: return "SMC";
306 case PCI_VENDOR_ID_ATI: return "ATI";
307 case PCI_VENDOR_ID_WEITEK: return "Weitek";
308 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
309 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
310 case PCI_VENDOR_ID_N9: return "Number Nine";
311 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
312 case PCI_VENDOR_ID_AL: return "Acer Labs";
313 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
314 case PCI_VENDOR_ID_CMD: return "CMD";
315 case PCI_VENDOR_ID_VISION: return "Vision";
316 case PCI_VENDOR_ID_AMD: return "AMD";
317 case PCI_VENDOR_ID_VLSI: return "VLSI";
318 case PCI_VENDOR_ID_ADL: return "Advance Logic";
319 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
320 case PCI_VENDOR_ID_TRIDENT: return "Trident";
321 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
322 case PCI_VENDOR_ID_NS: return "NS";
323 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
324 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
325 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
326 case PCI_VENDOR_ID_IMS: return "IMS";
327 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
328 case PCI_VENDOR_ID_EF: return "Efficient Networks";
329 case PCI_VENDOR_ID_HER: return "Hercules";
330 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
331 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
332 case PCI_VENDOR_ID_FD: return "Future Domain";
333 case PCI_VENDOR_ID_WINBOND: return "Winbond";
334 case PCI_VENDOR_ID_3COM: return "3Com";
335 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
336 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
337 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
338 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
339 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
340 default: return "Unknown vendor";
341 }
342 }
343
344
345 const char *pci_strdev(unsigned int vendor, unsigned int device)
346 {
347 struct pci_dev_info *info;
348
349 info = pci_lookup_dev(vendor, device);
350 return info ? info->name : "Unknown device";
351 }
352
353
354
355
356
357
358 static void burst_bridge(unsigned char bus, unsigned char devfn,
359 unsigned char pos, int turn_on)
360 {
361 #ifdef CONFIG_PCI_OPTIMIZE
362 struct bridge_mapping_type *bmap;
363 unsigned char val;
364 int i;
365
366 pos *= NUM_OPTIMIZATIONS;
367 printk("PCI bridge optimization.\n");
368 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
369 printk(" %s: ", bridge_optimization[i].type);
370 bmap = &bridge_mapping[pos + i];
371 if (!bmap->addr) {
372 printk("Not supported.");
373 } else {
374 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
375 if ((val & bmap->mask) == bmap->value) {
376 printk("%s.", bridge_optimization[i].on);
377 if (!turn_on) {
378 pcibios_write_config_byte(bus, devfn,
379 bmap->addr,
380 (val | bmap->mask)
381 - bmap->value);
382 printk("Changed! Now %s.", bridge_optimization[i].off);
383 }
384 } else {
385 printk("%s.", bridge_optimization[i].off);
386 if (turn_on) {
387 pcibios_write_config_byte(bus, devfn,
388 bmap->addr,
389 (val & (0xff - bmap->mask))
390 + bmap->value);
391 printk("Changed! Now %s.", bridge_optimization[i].on);
392 }
393 }
394 }
395 printk("\n");
396 }
397 #endif
398 }
399
400
401
402
403
404
405
406
407 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
408 {
409 unsigned long base;
410 unsigned int l, class_rev, bus, devfn;
411 unsigned short vendor, device, status;
412 unsigned char bist, latency, min_gnt, max_lat;
413 int reg, len = 0;
414 const char *str;
415
416 bus = dev->bus->number;
417 devfn = dev->devfn;
418
419 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
420 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
421 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
422 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
423 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
424 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
425 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
426 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
427 if (len + 80 > size) {
428 return -1;
429 }
430 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
431 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
432
433 if (len + 80 > size) {
434 return -1;
435 }
436 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
437 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
438 pci_strdev(vendor, device), class_rev & 0xff);
439
440 if (!pci_lookup_dev(vendor, device)) {
441 len += sprintf(buf + len,
442 "Vendor id=%x. Device id=%x.\n ",
443 vendor, device);
444 }
445
446 str = 0;
447 switch (status & PCI_STATUS_DEVSEL_MASK) {
448 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
449 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
450 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
451 }
452 if (len + strlen(str) > size) {
453 return -1;
454 }
455 len += sprintf(buf + len, str);
456
457 if (status & PCI_STATUS_FAST_BACK) {
458 # define fast_b2b_capable "Fast back-to-back capable. "
459 if (len + strlen(fast_b2b_capable) > size) {
460 return -1;
461 }
462 len += sprintf(buf + len, fast_b2b_capable);
463 # undef fast_b2b_capable
464 }
465
466 if (bist & PCI_BIST_CAPABLE) {
467 # define BIST_capable "BIST capable. "
468 if (len + strlen(BIST_capable) > size) {
469 return -1;
470 }
471 len += sprintf(buf + len, BIST_capable);
472 # undef BIST_capable
473 }
474
475 if (dev->irq) {
476 if (len + 40 > size) {
477 return -1;
478 }
479 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
480 }
481
482 if (dev->master) {
483 if (len + 80 > size) {
484 return -1;
485 }
486 len += sprintf(buf + len, "Master Capable. ");
487 if (latency)
488 len += sprintf(buf + len, "Latency=%d. ", latency);
489 else
490 len += sprintf(buf + len, "No bursts. ");
491 if (min_gnt)
492 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
493 if (max_lat)
494 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
495 }
496
497 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
498 if (len + 40 > size) {
499 return -1;
500 }
501 pcibios_read_config_dword(bus, devfn, reg, &l);
502 base = l;
503 if (!base) {
504 continue;
505 }
506
507 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
508 len += sprintf(buf + len,
509 "\n I/O at 0x%lx.",
510 base & PCI_BASE_ADDRESS_IO_MASK);
511 } else {
512 const char *pref, *type = "unknown";
513
514 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
515 pref = "P";
516 } else {
517 pref = "Non-p";
518 }
519 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
520 case PCI_BASE_ADDRESS_MEM_TYPE_32:
521 type = "32 bit"; break;
522 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
523 type = "20 bit"; break;
524 case PCI_BASE_ADDRESS_MEM_TYPE_64:
525 type = "64 bit";
526
527 reg += 4;
528 pcibios_read_config_dword(bus, devfn, reg, &l);
529 base |= ((u64) l) << 32;
530 break;
531 }
532 len += sprintf(buf + len,
533 "\n %srefetchable %s memory at "
534 "0x%lx.", pref, type,
535 base & PCI_BASE_ADDRESS_MEM_MASK);
536 }
537 }
538
539 len += sprintf(buf + len, "\n");
540 return len;
541 }
542
543
544
545
546
547
548 int get_pci_list(char *buf)
549 {
550 int nprinted, len, size;
551 struct pci_dev *dev;
552 # define MSG "\nwarning: page-size limit reached!\n"
553
554
555 size = PAGE_SIZE - (strlen(MSG) + 1);
556 len = sprintf(buf, "PCI devices found:\n");
557
558 for (dev = pci_devices; dev; dev = dev->next) {
559 nprinted = sprint_dev_config(dev, buf + len, size - len);
560 if (nprinted < 0) {
561 return len + sprintf(buf + len, MSG);
562 }
563 len += nprinted;
564 }
565 return len;
566 }
567
568
569
570
571
572
573 static void *pci_malloc(long size, unsigned long *mem_startp)
574 {
575 void *mem;
576
577 #ifdef DEBUG
578 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
579 #endif
580 mem = (void*) *mem_startp;
581 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
582 memset(mem, 0, size);
583 return mem;
584 }
585
586
587 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
588 {
589 unsigned int devfn, l, max;
590 unsigned char cmd, tmp, hdr_type = 0;
591 struct pci_dev_info *info;
592 struct pci_dev *dev;
593 struct pci_bus *child;
594
595 #ifdef DEBUG
596 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
597 #endif
598
599 max = bus->secondary;
600 for (devfn = 0; devfn < 0xff; ++devfn) {
601 if (PCI_FUNC(devfn) == 0) {
602 pcibios_read_config_byte(bus->number, devfn,
603 PCI_HEADER_TYPE, &hdr_type);
604 } else if (!(hdr_type & 0x80)) {
605
606 continue;
607 }
608
609 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
610 &l);
611
612 if (l == 0xffffffff || l == 0x00000000) {
613 hdr_type = 0;
614 continue;
615 }
616
617 dev = pci_malloc(sizeof(*dev), mem_startp);
618 dev->bus = bus;
619
620
621
622
623
624 dev->next = pci_devices;
625 pci_devices = dev;
626
627 dev->devfn = devfn;
628 dev->vendor = l & 0xffff;
629 dev->device = (l >> 16) & 0xffff;
630
631
632
633
634
635
636 info = pci_lookup_dev(dev->vendor, dev->device);
637 if (!info) {
638 printk("Warning : Unknown PCI device. Please read include/linux/pci.h \n");
639 } else {
640
641 if (info->bridge_type != 0xff) {
642 burst_bridge(bus->number, devfn,
643 info->bridge_type, 1);
644 }
645 }
646
647
648 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
649 &cmd);
650 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
651 cmd | PCI_COMMAND_MASTER);
652 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
653 &tmp);
654 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
655 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
656 cmd);
657
658
659 pcibios_read_config_byte(bus->number, devfn,
660 PCI_INTERRUPT_LINE, &dev->irq);
661
662
663 pcibios_read_config_dword(bus->number, devfn,
664 PCI_CLASS_REVISION, &l);
665 l = l >> 8;
666 dev->class = l;
667
668
669
670
671 dev->sibling = bus->devices;
672 bus->devices = dev;
673
674 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
675 unsigned int buses;
676
677
678
679
680 child = pci_malloc(sizeof(*child), mem_startp);
681 child->next = bus->children;
682 bus->children = child;
683 child->self = dev;
684 child->parent = bus;
685
686
687
688
689
690 child->number = child->secondary = ++max;
691 child->primary = bus->secondary;
692 child->subordinate = 0xff;
693
694
695
696
697 pcibios_write_config_word(bus->number, devfn,
698 PCI_COMMAND, 0x0000);
699 pcibios_write_config_word(bus->number, devfn,
700 PCI_STATUS, 0xffff);
701
702
703
704 pcibios_read_config_dword(bus->number, devfn, 0x18,
705 &buses);
706 buses &= 0xff000000;
707 buses |= (((unsigned int)(child->primary) << 0) |
708 ((unsigned int)(child->secondary) << 8) |
709 ((unsigned int)(child->subordinate) << 16));
710 pcibios_write_config_dword(bus->number, devfn, 0x18,
711 buses);
712
713
714
715 max = scan_bus(child, mem_startp);
716
717
718
719
720 child->subordinate = max;
721 buses = (buses & 0xff00ffff)
722 | ((unsigned int)(child->subordinate) << 16);
723 pcibios_write_config_dword(bus->number, devfn, 0x18,
724 buses);
725 }
726 }
727
728
729
730
731
732
733
734 return max;
735 }
736
737
738 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
739 {
740 mem_start = pcibios_init(mem_start, mem_end);
741
742 if (!pcibios_present()) {
743 printk("pci_init: no BIOS32 detected\n");
744 return mem_start;
745 }
746
747 printk("Probing PCI hardware.\n");
748
749 memset(&pci_root, 0, sizeof(pci_root));
750 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
751
752
753 mem_start = pcibios_fixup(mem_start, mem_end);
754
755 #ifdef DEBUG
756 {
757 int len = get_pci_list(mem_start);
758 if (len) {
759 ((char*)mem_start)[len] = '\0';
760 printk("%s\n", mem_start);
761 }
762 }
763 #endif
764 return mem_start;
765 }
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