1 /*+M************************************************************************* 2 * Adaptec 274x/284x/294x device driver for Linux. 3 * 4 * Copyright (c) 1994 John Aycock 5 * The University of Calgary Department of Computer Science. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; see the file COPYING. If not, write to 19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F 22 * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA 23 * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide, 24 * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux, 25 * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file 26 * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual, 27 * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the 28 * ANSI SCSI-2 specification (draft 10c), ... 29 * 30 * ---------------------------------------------------------------- 31 * Modified to include support for wide and twin bus adapters, 32 * DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes, 33 * and other rework of the code. 34 * 35 * Parts of this driver are based on the FreeBSD driver by Justin 36 * T. Gibbs. 37 * 38 * A Boot time option was also added for not resetting the scsi bus. 39 * 40 * Form: aic7xxx=extended,no_reset 41 * 42 * -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95 43 * 44 * $Id: aic7xxx.c,v 2.0 1995/08/02 05:28:42 deang Exp $ 45 *-M*************************************************************************/ 46
47 #ifdefMODULE 48 #include <linux/module.h>
49 #endif 50
51 #include <stdarg.h>
52 #include <asm/io.h>
53 #include <linux/string.h>
54 #include <linux/errno.h>
55 #include <linux/kernel.h>
56 #include <linux/ioport.h>
57 #include <linux/bios32.h>
58 #include <linux/delay.h>
59 #include <linux/sched.h>
60 #include <linux/pci.h>
61 #include <linux/proc_fs.h>
62 #include "../block/blk.h"
63 #include "sd.h"
64 #include "scsi.h"
65 #include "hosts.h"
66 #include "aic7xxx.h"
67
68 #defineAIC7XXX_C_VERSION "$Revision: 2.0 $"
69
70 #defineNUMBER(arr) (sizeof(arr) / sizeof(arr[0]))
71 #defineMIN(a,b) ((a < b) ? a : b)
72 #ifndefTRUE 73 # defineTRUE 1
74 #endif 75 #ifndefFALSE 76 # defineFALSE 0
77 #endif 78
79 /* 80 * Defines for PCI bus support, testing twin bus support, DMAing of 81 * SCBs, and tagged queueing. 82 * 83 * o PCI bus support - this has been implemented and working since 84 * the December 1, 1994 release of this driver. If you don't have 85 * a PCI bus and do not wish to configure your kernel with PCI 86 * support, then make sure this define is set to the cprrect 87 * define for PCI support (CONFIG_PCI) and configure your kernel 88 * without PCI support (make config). 89 * 90 * o Twin bus support - this has been tested and does work. 91 * 92 * o DMAing of SCBs - thanks to Kai Makisara, this now works 93 * 94 * o Tagged queueing - this driver is capable of tagged queueing 95 * but I am unsure as to how well the higher level driver implements 96 * tagged queueing. Therefore, the maximum commands per lun is 97 * set to 2. If you want to implement tagged queueing, ensure 98 * this define is not commented out. 99 * 100 * o Sharing IRQs - allowed for sharing of IRQs. This will allow 101 * for multiple aic7xxx host adapters sharing the same IRQ, but 102 * not for sharing IRQs with other devices. The higher level 103 * PCI code and interrupt handling needs to be modified to 104 * support this. 105 * 106 * Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95 107 */ 108
109 /* Uncomment this for testing twin bus support. */ 110 #defineAIC7XXX_TWIN_SUPPORT 111
112 /* Uncomment this for DMAing of SCBs. */ 113 #defineAIC7XXX_USE_DMA 114
115 /* Uncomment this for tagged queueing. */ 116 /* #define AIC7XXX_TAGGED_QUEUEING */ 117
118 /* Uncomment this for allowing sharing of IRQs. */ 119 #defineAIC7XXX_SHARE_IRQS 120
121 /* Set this to the delay in seconds after SCSI bus reset. */ 122 #defineAIC7XXX_RESET_DELAY 15
123
124 /* 125 * Uncomment this to always use scatter/gather lists. 126 * *NOTE: The sequencer must be changed also! 127 */ 128 #defineAIC7XXX_USE_SG 129
130 /* 131 * Controller type and options 132 */ 133 typedefenum{ 134 AIC_NONE,
135 AIC_274x, /* EISA aic7770 */ 136 AIC_284x, /* VLB aic7770 */ 137 AIC_7870, /* PCI aic7870 */ 138 AIC_7850, /* PCI aic7850 */ 139 AIC_7872/* PCI aic7870 on 394x */ 140 }aha_type;
141
142 typedefenum{ 143 AIC_SINGLE, /* Single Channel */ 144 AIC_TWIN, /* Twin Channel */ 145 AIC_WIDE/* Wide Channel */ 146 }aha_bus_type;
147
148 typedefenum{ 149 AIC_UNKNOWN,
150 AIC_ENABLED,
151 AIC_DISABLED 152 }aha_status_type;
153
154 /* 155 * There should be a specific return value for this in scsi.h, but 156 * it seems that most drivers ignore it. 157 */ 158 #define DID_UNDERFLOW DID_ERROR 159
160 /* 161 * What we want to do is have the higher level scsi driver requeue 162 * the command to us. There is no specific driver status for this 163 * condition, but the higher level scsi driver will requeue the 164 * command on a DID_BUS_BUSY error. 165 */ 166 #defineDID_RETRY_COMMANDDID_BUS_BUSY 167
168 /* 169 * EISA/VL-bus stuff 170 */ 171 #defineMINSLOT 1
172 #defineMAXSLOT 15
173 #defineSLOTBASE(x) ((x) << 12)
174 #defineMAXIRQ 15
175
176 /* 177 * Standard EISA Host ID regs (Offset from slot base) 178 */ 179 #defineHID0(x) ((x) + 0xC80) /* 0,1: msb of ID2, 2-7: ID1 */ 180 #defineHID1(x) ((x) + 0xC81) /* 0-4: ID3, 5-7: LSB ID2 */ 181 #defineHID2(x) ((x) + 0xC82) /* product */ 182 #define HID3(x) ((x) + 0xC83) /* firmware revision */ 183
184 /* 185 * AIC-7770 I/O range to reserve for a card 186 */ 187 #defineMINREG(x) ((x) + 0xC00ul)
188 #defineMAXREG(x) ((x) + 0xCBFul)
189
190 /* -------------------- AIC-7770 offset definitions ----------------------- */ 191
192 /* 193 * SCSI Sequence Control (p. 3-11). 194 * Each bit, when set starts a specific SCSI sequence on the bus 195 */ 196 #defineSCSISEQ(x) ((x) + 0xC00ul)
197 #defineTEMODEO 0x80
198 #defineENSELO 0x40
199 #defineENSELI 0x20
200 #defineENRSELI 0x10
201 #defineENAUTOATNO 0x08
202 #defineENAUTOATNI 0x04
203 #defineENAUTOATNP 0x02
204 #defineSCSIRSTO 0x01
205
206 /* 207 * SCSI Transfer Control 1 Register (pp. 3-14,15). 208 * Controls the SCSI module data path. 209 */ 210 #defineSXFRCTL1(x) ((x) + 0xC02ul)
211 #define BITBUCKET 0x80
212 #define SWRAPEN 0x40
213 #defineENSPCHK 0x20
214 #defineSTIMESEL 0x18
215 #defineENSTIMER 0x04
216 #defineACTNEGEN 0x02
217 #defineSTPWEN 0x01 /* Powered Termination */ 218
219 /* 220 * SCSI Control Signal Read Register (p. 3-15). 221 * Reads the actual state of the SCSI bus pins 222 */ 223 #defineSCSISIGI(x) ((x) + 0xC03ul)
224 #defineCDI 0x80
225 #defineIOI 0x40
226 #defineMSGI 0x20
227 #defineATNI 0x10
228 #defineSELI 0x08
229 #defineBSYI 0x04
230 #defineREQI 0x02
231 #defineACKI 0x01
232
233 /* 234 * SCSI Contol Signal Write Register (p. 3-16). 235 * Writing to this register modifies the control signals on the bus. Only 236 * those signals that are allowed in the current mode (Initiator/Target) are 237 * asserted. 238 */ 239 #defineSCSISIGO(x) ((x) + 0xC03ul)
240 #defineCDO 0x80
241 #define IOO 0x40
242 #defineMSGO 0x20
243 #defineATNO 0x10
244 #define SELO 0x08
245 #define BSYO 0x04
246 #define REQO 0x02
247 #define ACKO 0x01
248
249 /* 250 * SCSI Rate 251 */ 252 #defineSCSIRATE(x) ((x) + 0xC04ul)
253
254 /* 255 * SCSI ID (p. 3-18). 256 * Contains the ID of the board and the current target on the 257 * selected channel 258 */ 259 #defineSCSIID(x) ((x) + 0xC05ul)
260 #define TID 0xF0 /* Target ID mask */ 261 #define OID 0x0F /* Our ID mask */ 262
263 /* 264 * SCSI Status 0 (p. 3-21) 265 * Contains one set of SCSI Interrupt codes 266 * These are most likely of interest to the sequencer 267 */ 268 #defineSSTAT0(x) ((x) + 0xC0Bul)
269 #defineTARGET 0x80 /* Board is a target */ 270 #defineSELDO 0x40 /* Selection Done */ 271 #defineSELDI 0x20 /* Board has been selected */ 272 #defineSELINGO 0x10 /* Selection In Progress */ 273 #defineSWRAP 0x08 /* 24bit counter wrap */ 274 #defineSDONE 0x04 /* STCNT = 0x000000 */ 275 #defineSPIORDY 0x02 /* SCSI PIO Ready */ 276 #defineDMADONE 0x01 /* DMA transfer completed */ 277
278 /* 279 * Clear SCSI Interrupt 1 (p. 3-23) 280 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 281 */ 282 #defineCLRSINT1(x) ((x) + 0xC0Cul)
283 #defineCLRSELTIMEO 0x80
284 #defineCLRATNO 0x40
285 #define CLRSCSIRSTI 0x20
286 /* UNUSED 0x10 */ 287 #defineCLRBUSFREE 0x08
288 #defineCLRSCSIPERR 0x04
289 #defineCLRPHASECHG 0x02
290 #define CLRREQINIT 0x01
291
292 /* 293 * SCSI Status 1 (p. 3-24) 294 * These interrupt bits are of interest to the kernel driver 295 */ 296 #defineSSTAT1(x) ((x) + 0xC0Cul)
297 #defineSELTO 0x80
298 #defineATNTARG 0x40
299 #defineSCSIRSTI 0x20
300 #definePHASEMIS 0x10
301 #defineBUSFREE 0x08
302 #defineSCSIPERR 0x04
303 #definePHASECHG 0x02
304 #defineREQINIT 0x01
305
306 /* 307 * SCSI Interrrupt Mode 1 (pp. 3-28,29). 308 * Set bits in this register enable the corresponding 309 * interrupt source. 310 */ 311 #defineSIMODE1(x) ((x) + 0xC11ul)
312 #defineENSELTIMO 0x80
313 #defineENATNTARG 0x40
314 #define ENSCSIRST 0x20
315 #defineENPHASEMIS 0x10
316 #defineENBUSFREE 0x08
317 #defineENSCSIPERR 0x04
318 #defineENPHASECHG 0x02
319 #defineENREQINIT 0x01
320
321 /* 322 * Selection/Reselection ID (p. 3-31) 323 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 324 * device did not set its own ID. 325 */ 326 #defineSELID(x) ((x) + 0xC19ul)
327 #define SELID_MASK 0xF0
328 #define ONEBIT 0x08
329 /* UNUSED 0x07 */ 330
331 /* 332 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 333 * Controls the reading and writing of an external serial 1-bit 334 * EEPROM Device. In order to access the serial EEPROM, you must 335 * first set the SEEMS bit that generates a request to the memory 336 * port for access to the serial EEPROM device. When the memory 337 * port is not busy servicing another request, it reconfigures 338 * to allow access to the serial EEPROM. When this happens, SEERDY 339 * gets set high to verify that the memory port access has been 340 * granted. See aic7xxx_read_eprom for detailed information on 341 * the protocol necessary to read the serial EEPROM. 342 */ 343 #defineSEECTL(x) ((x) + 0xC1Eul)
344 #define EXTARBACK 0x80
345 #define EXTARBREQ 0x40
346 #defineSEEMS 0x20
347 #defineSEERDY 0x10
348 #defineSEECS 0x08
349 #defineSEECK 0x04
350 #define SEEDO 0x02
351 #defineSEEDI 0x01
352
353 /* 354 * SCSI Block Control (p. 3-32) 355 * Controls Bus type and channel selection. In a twin channel configuration 356 * addresses 0x00-0x1E are gated to the appropriate channel based on this 357 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 358 * on a wide bus. 359 */ 360 #defineSBLKCTL(x) ((x) + 0xC1Ful)
361 /* UNUSED 0xC0 */ 362 #defineAUTOFLUSHDIS 0x20 /* used for Rev C check */ 363 /* UNUSED 0x10 */ 364 #defineSELBUSB 0x08
365 /* UNUSED 0x04 */ 366 #define SELWIDE 0x02
367 /* UNUSED 0x01 */ 368 #define SELSINGLE 0x00
369
370 /* 371 * Sequencer Control (p. 3-33) 372 * Error detection mode and speed configuration 373 */ 374 #defineSEQCTL(x) ((x) + 0xC60ul)
375 #definePERRORDIS 0x80
376 #define PAUSEDIS 0x40
377 #define FAILDIS 0x20
378 #defineFASTMODE 0x10
379 #define BRKADRINTEN 0x08
380 #define STEP 0x04
381 #defineSEQRESET 0x02
382 #defineLOADRAM 0x01
383
384 /* 385 * Sequencer RAM Data (p. 3-34) 386 * Single byte window into the Scratch Ram area starting at the address 387 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 388 * four bytes in sucessesion. The SEQADDRs will increment after the most 389 * significant byte is written 390 */ 391 #defineSEQRAM(x) ((x) + 0xC61ul)
392
393 /* 394 * Sequencer Address Registers (p. 3-35) 395 * Only the first bit of SEQADDR1 holds addressing information 396 */ 397 #defineSEQADDR0(x) ((x) + 0xC62ul)
398 #defineSEQADDR1(x) ((x) + 0xC63ul)
399
400 #defineACCUM(x) ((x) + 0xC64ul) /* accumulator */ 401
402 /* 403 * Board Control (p. 3-43) 404 */ 405 #defineBCTL(x) ((x) + 0xC84ul)
406 /* RSVD 0xF0 */ 407 #define ACE 0x08 /* Support for external processors */ 408 /* RSVD 0x06 */ 409 #defineENABLE 0x01
410
411 /* 412 * Bus On/Off Time (p. 3-44) 413 */ 414 #defineBUSTIME(x) ((x) + 0xC85ul)
415 #defineBOFF 0xF0
416 #define BON 0x0F
417
418 /* 419 * Bus Speed (p. 3-45) 420 */ 421 #defineBUSSPD(x) ((x) + 0xC86ul)
422 #defineDFTHRSH 0xC0
423 #define STBOFF 0x38
424 #define STBON 0x07
425
426 /* 427 * Host Control (p. 3-47) R/W 428 * Overal host control of the device. 429 */ 430 #defineHCNTRL(x) ((x) + 0xC87ul)
431 /* UNUSED 0x80 */ 432 #define POWRDN 0x40
433 /* UNUSED 0x20 */ 434 #defineSWINT 0x10
435 #defineIRQMS 0x08
436 #definePAUSE 0x04
437 #defineINTEN 0x02
438 #defineCHIPRST 0x01
439 #defineREQ_PAUSEIRQMS | PAUSE | INTEN 440 #define UNPAUSE_274X IRQMS | INTEN 441 #defineUNPAUSE_284XINTEN 442 #defineUNPAUSE_294XIRQMS | INTEN 443
444 /* 445 * SCB Pointer (p. 3-49) 446 * Gate one of the four SCBs into the SCBARRAY window. 447 */ 448 #defineSCBPTR(x) ((x) + 0xC90ul)
449
450 /* 451 * Interrupt Status (p. 3-50) 452 * Status for system interrupts 453 */ 454 #defineINTSTAT(x) ((x) + 0xC91ul)
455 #defineSEQINT_MASK 0xF0 /* SEQINT Status Codes */ 456 #defineBAD_PHASE 0x00
457 #defineSEND_REJECT 0x10
458 #defineNO_IDENT 0x20
459 #defineNO_MATCH 0x30
460 #defineMSG_SDTR 0x40
461 #defineMSG_WDTR 0x50
462 #defineMSG_REJECT 0x60
463 #defineBAD_STATUS 0x70
464 #defineRESIDUAL 0x80
465 #defineABORT_TAG 0x90
466 #defineAWAITING_MSG 0xa0
467 #defineBRKADRINT 0x08
468 #defineSCSIINT 0x04
469 #defineCMDCMPLT 0x02
470 #defineSEQINT 0x01
471 #defineINT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
472
473 /* 474 * Hard Error (p. 3-53) 475 * Reporting of catastrophic errors. You usually cannot recover from 476 * these without a full board reset. 477 */ 478 #defineERROR(x) ((x) + 0xC92ul)
479 /* UNUSED 0xF0 */ 480 #definePARERR 0x08
481 #defineILLOPCODE 0x04
482 #defineILLSADDR 0x02
483 #defineILLHADDR 0x01
484
485 /* 486 * Clear Interrupt Status (p. 3-52) 487 */ 488 #defineCLRINT(x) ((x) + 0xC92ul)
489 #define CLRBRKADRINT 0x08
490 #defineCLRSCSIINT 0x04
491 #defineCLRCMDINT 0x02
492 #defineCLRSEQINT 0x01
493
494 /* 495 * SCB Auto Increment (p. 3-59) 496 * Byte offset into the SCB Array and an optional bit to allow auto 497 * incrementing of the address during download and upload operations 498 */ 499 #defineSCBCNT(x) ((x) + 0xC9Aul)
500 #defineSCBAUTO 0x80
501 #define SCBCNT_MASK 0x1F
502
503 /* 504 * Queue In FIFO (p. 3-60) 505 * Input queue for queued SCBs (commands that the seqencer has yet to start) 506 */ 507 #defineQINFIFO(x) ((x) + 0xC9Bul)
508
509 /* 510 * Queue In Count (p. 3-60) 511 * Number of queued SCBs 512 */ 513 #defineQINCNT(x) ((x) + 0xC9Cul)
514
515 /* 516 * Queue Out FIFO (p. 3-61) 517 * Queue of SCBs that have completed and await the host 518 */ 519 #defineQOUTFIFO(x) ((x) + 0xC9Dul)
520
521 /* 522 * Queue Out Count (p. 3-61) 523 * Number of queued SCBs in the Out FIFO 524 */ 525 #defineQOUTCNT(x) ((x) + 0xC9Eul)
526
527 #defineSCBARRAY(x) ((x) + 0xCA0ul)
528
529 /* ---------------- END AIC-7770 Register Definitions ----------------- */ 530
531 /* --------------------- AIC-7870-only definitions -------------------- */ 532
533 #defineDSPCISTATUS(x) ((x) + 0xC86ul)
534 #defineDFTHRESH 0xC0
535
536 /* Scratch RAM offset definitions */ 537
538 /* ---------------------- Scratch RAM Offsets ------------------------- */ 539 /* These offsets are either to values that are initialized by the board's 540 * BIOS or are specified by the Linux sequencer code. If I can figure out 541 * how to read the EISA configuration info at probe time, the cards could 542 * be run without BIOS support installed 543 */ 544
545 /* 546 * 1 byte per target starting at this address for configuration values 547 */ 548 #defineHA_TARG_SCRATCH(x) ((x) + 0xC20ul)
549
550 /* 551 * The sequencer will stick the first byte of any rejected message here so 552 * we can see what is getting thrown away. 553 */ 554 #defineHA_REJBYTE(x) ((x) + 0xC31ul)
555
556 /* 557 * Bit vector of targets that have disconnection disabled. 558 */ 559 #define HA_DISC_DSB ((x) + 0xc32ul)
560
561 /* 562 * Length of pending message 563 */ 564 #defineHA_MSG_LEN(x) ((x) + 0xC34ul)
565
566 /* 567 * Outgoing Message Body 568 */ 569 #defineHA_MSG_START(x) ((x) + 0xC35ul)
570
571 /* 572 * These are offsets into the card's scratch ram. Some of the values are 573 * specified in the AHA2742 technical reference manual and are initialized 574 * by the BIOS at boot time. 575 */ 576 #defineHA_ARG_1(x) ((x) + 0xC4Aul) /* sdtr <-> rate parameters */ 577 #defineHA_RETURN_1(x) ((x) + 0xC4Aul)
578 #defineSEND_SENSE 0x80
579 #defineSEND_SDTR 0x80
580 #defineSEND_WDTR 0x80
581 #defineSEND_REJ 0x40
582
583 #defineHA_SIGSTATE(x) ((x) + 0xC4Bul) /* value in SCSISIGO */ 584 #defineHA_SCBCOUNT(x) ((x) + 0xC52ul) /* number of hardware SCBs */ 585
586 #defineHA_FLAGS(x) ((x) + 0xC53ul) /* TWIN and WIDE bus flags */ 587 #define SINGLE_BUS 0x00
588 #defineTWIN_BUS 0x01
589 #defineWIDE_BUS 0x02
590 #defineACTIVE_MSG 0x20
591 #define IDENTIFY_SEEN 0x40
592 #define RESELECTING 0x80
593
594 #defineHA_ACTIVE0(x) ((x) + 0xC54ul) /* Active bits; targets 0-7 */ 595 #defineHA_ACTIVE1(x) ((x) + 0xC55ul) /* Active bits; targets 8-15 */ 596 #define SAVED_TCL(x) ((x) + 0xC56ul) /* Saved target, channel, LUN */ 597 #defineWAITING_SCBH(x) ((x) + 0xC57ul) /* Head of disconnected targets list. */ 598 #defineWAITING_SCBT(x) ((x) + 0xC58ul) /* Tail of disconnected targets list. */ 599
600 #defineHA_SCSICONF(x) ((x) + 0xC5Aul) /* SCSI config register */ 601 #defineHA_INTDEF(x) ((x) + 0xC5Cul) /* interrupt def'n register */ 602 #defineHA_HOSTCONF(x) ((x) + 0xC5Dul) /* host config def'n register */ 603
604 #define MSG_ABORT 0x06
605 #defineMSG_BUS_DEVICE_RESET 0x0c
606 #defineBUS_8_BIT 0x00
607 #defineBUS_16_BIT 0x01
608 #defineBUS_32_BIT 0x02
609
610
611 /* 612 * 613 * Define the format of the SEEPROM registers (16 bits). 614 * 615 */ 616 structseeprom_config{ 617
618 /* 619 * SCSI ID Configuration Flags 620 */ 621 #defineCFXFER 0x0007 /* synchronous transfer rate */ 622 #defineCFSYNCH 0x0008 /* enable synchronous transfer */ 623 #define CFDISC 0x0010 /* enable disconnection */ 624 #defineCFWIDEB 0x0020 /* wide bus device */ 625 /* UNUSED 0x00C0 */ 626 #define CFSTART 0x0100 /* send start unit SCSI command */ 627 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 628 #define CFRNFOUND 0x0400 /* report even if not found */ 629 /* UNUSED 0xF800 */ 630 unsignedshortdevice_flags[16]; /* words 0-15 */ 631
632 /* 633 * BIOS Control Bits 634 */ 635 #define CFSUPREM 0x0001 /* support all removeable drives */ 636 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 637 #define CFBIOSEN 0x0004 /* BIOS enabled */ 638 /* UNUSED 0x0008 */ 639 #define CFSM2DRV 0x0010 /* support more than two drives */ 640 /* UNUSED 0x0060 */ 641 #defineCFEXTEND 0x0080 /* extended translation enabled */ 642 /* UNUSED 0xFF00 */ 643 unsignedshortbios_control; /* word 16 */ 644
645 /* 646 * Host Adapter Control Bits 647 */ 648 /* UNUSED 0x0003 */ 649 #defineCFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 650 #defineCFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 651 #defineCFSPARITY 0x0010 /* SCSI parity */ 652 /* UNUSED 0x0020 */ 653 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 654 /* UNUSED 0xFF80 */ 655 unsignedshortadapter_control; /* word 17 */ 656
657 /* 658 * Bus Release, Host Adapter ID 659 */ 660 #defineCFSCSIID 0x000F /* host adapter SCSI ID */ 661 /* UNUSED 0x00F0 */ 662 #defineCFBRTIME 0xFF00 /* bus release time */ 663 unsignedshortbrtime_id; /* word 18 */ 664
665 /* 666 * Maximum targets 667 */ 668 #define CFMAXTARG 0x00FF /* maximum targets */ 669 /* UNUSED 0xFF00 */ 670 unsignedshortmax_targets; /* word 19 */ 671
672 unsignedshort res_1[11]; /* words 20-30 */ 673 unsignedshortchecksum; /* word 31 */ 674
675 };
676
677
678 #defineAIC7XXX_DEBUG 679
680 /* 681 * Pause the sequencer and wait for it to actually stop - this 682 * is important since the sequencer can disable pausing for critical 683 * sections. 684 */ 685 #definePAUSE_SEQUENCER(p) \
686 outb(p->pause, HCNTRL(p->base)); \
687 while ((inb(HCNTRL(p->base)) & PAUSE) == 0) \
688 ; \
689
690 /* 691 * Unpause the sequencer. Unremarkable, yet done often enough to 692 * warrant an easy way to do it. 693 */ 694 #defineUNPAUSE_SEQUENCER(p) \
695 outb(p->unpause, HCNTRL(p->base))
696
697 /* 698 * Restart the sequencer program from address zero 699 */ 700 #defineRESTART_SEQUENCER(p) \
701 do{ \
702 outb(SEQRESET | FASTMODE, SEQCTL(p->base)); \
703 }while (inb(SEQADDR0(p->base)) != 0 && \
704 inb(SEQADDR1(p->base)) != 0); \
705 UNPAUSE_SEQUENCER(p);
706
707 /* 708 * If an error occurs during a data transfer phase, run the comand 709 * to completion - it's easier that way - making a note of the error 710 * condition in this location. This then will modify a DID_OK status 711 * into an appropriate error for the higher-level SCSI code. 712 */ 713 #defineaic7xxx_error(cmd) ((cmd)->SCp.Status)
714
715 /* 716 * Keep track of the targets returned status. 717 */ 718 #defineaic7xxx_status(cmd) ((cmd)->SCp.sent_command)
719
720 /* 721 * The position of the SCSI commands scb within the scb array. 722 */ 723 #defineaic7xxx_position(cmd) ((cmd)->SCp.have_data_in)
724
725 /* 726 * Since the sequencer code DMAs the scatter-gather structures 727 * directly from memory, we use this macro to assert that the 728 * kernel structure hasn't changed. 729 */ 730 #defineSG_STRUCT_CHECK(sg) \
731 ((char *)&(sg).address - (char *)&(sg) != 0 || \
732 (char *)&(sg).length - (char *)&(sg) != 8 || \
733 sizeof((sg).address) != 4 || \
734 sizeof((sg).length) != 4 || \
735 sizeof(sg) != 12)
736
737 /* 738 * "Static" structures. Note that these are NOT initialized 739 * to zero inside the kernel - we have to initialize them all 740 * explicitly. 741 * 742 * We support multiple adapter cards per interrupt, but keep a 743 * linked list of Scsi_Host structures for each IRQ. On an interrupt, 744 * use the IRQ as an index into aic7xxx_boards[] to locate the card 745 * information. 746 */ 747 staticstructScsi_Host *aic7xxx_boards[MAXIRQ + 1];
748
749 /* 750 * When we detect and register the card, it is possible to 751 * have the card raise a spurious interrupt. Because we need 752 * to support multiple cards, we cannot tell which card caused 753 * the spurious interrupt. And, we might not even have added 754 * the card info to the linked list at the time the spurious 755 * interrupt gets raised. This variable is suppose to keep track 756 * of when we are registering a card and how many spurious 757 * interrupts we have encountered. 758 * 759 * 0 - do not allow spurious interrupts. 760 * 1 - allow 1 spurious interrupt 761 * 2 - have 1 spurious interrupt, do not allow any more. 762 * 763 * I've made it an integer instead of a boolean in case we 764 * want to allow more than one spurious interrupt for debugging 765 * purposes. Otherwise, it could just go from true to false to 766 * true (or something like that). 767 * 768 * When the driver detects the cards, we'll set the count to 1 769 * for each card detection and registration. After the registration 770 * of a card completes, we'll set the count back to 0. So far, it 771 * seems to be enough to allow a spurious interrupt only during 772 * card registration; if a spurious interrupt is going to occur, 773 * this is where it happens. 774 * 775 * We should be able to find a way to avoid getting the spurious 776 * interrupt. But until we do, we have to keep this ugly code. 777 */ 778 staticintaic7xxx_spurious_count;
779
780 /* 781 * The driver keeps up to four scb structures per card in memory. Only the 782 * first 26 bytes of the structure are valid for the hardware, the rest used 783 * for driver level bookeeping. The driver is further optimized 784 * so that we only have to download the first 19 bytes since as long 785 * as we always use S/G, the last fields should be zero anyway. 786 */ 787 #ifdefAIC7XXX_USE_SG 788 #defineSCB_DOWNLOAD_SIZE 19 /* amount to actually download */ 789 #else 790 #defineSCB_DOWNLOAD_SIZE 26
791 #endif 792
793 #defineSCB_UPLOAD_SIZE 19 /* amount to actually upload */ 794
795 structaic7xxx_scb{ 796 /* ------------ Begin hardware supported fields ---------------- */ 797 /*1 */unsignedcharcontrol;
798 #defineSCB_NEEDWDTR 0x80 /* Initiate Wide Negotiation */ 799 #defineSCB_NEEDSDTR 0x40 /* Initiate Sync Negotiation */ 800 #defineSCB_NEEDDMA 0x08 /* SCB needs to be DMA'd from 801 * from host memory 802 */ 803 #define SCB_REJ_MDP 0x80 /* Reject MDP message */ 804 #define SCB_DISEN 0x40 /* SCB Disconnect enable */ 805 #defineSCB_TE 0x20 /* Tag enable */ 806 /* RESERVED 0x10 */ 807 #define SCB_WAITING 0x08 /* Waiting */ 808 #defineSCB_DIS 0x04 /* Disconnected */ 809 #define SCB_TAG_TYPE 0x03
810 #define SIMPLE_QUEUE 0x00 /* Simple Queue */ 811 #define HEAD_QUEUE 0x01 /* Head of Queue */ 812 #define ORD_QUEUE 0x02 /* Ordered Queue */ 813 /* ILLEGAL 0x03 */ 814 /*2 */unsignedchartarget_channel_lun; /* 4/1/3 bits */ 815 /*3 */unsignedcharSG_segment_count;
816 /*7 */unsignedcharSG_list_pointer[4] __attribute__ ((packed));
817 /*11*/unsignedcharSCSI_cmd_pointer[4] __attribute__ ((packed));
818 /*12*/unsignedcharSCSI_cmd_length;
819 /*14*/unsignedcharRESERVED[2]; /* must be zero */ 820 /*15*/unsignedchartarget_status;
821 /*18*/unsignedchar residual_data_count[3];
822 /*19*/unsignedcharresidual_SG_segment_count;
823 /*23*/unsignedchardata_pointer[4] __attribute__ ((packed));
824 /*26*/unsignedchardata_count[3];
825 /*30*/unsignedcharhost_scb[4] __attribute__ ((packed));
826 /*31*/u_charnext_waiting; /* Used to thread SCBs awaiting selection. */ 827 #defineSCB_LIST_NULL 0x10 /* SCB list equivelent to NULL */ 828 #if 0
829 /* 830 * No real point in transferring this to the 831 * SCB registers. 832 */ 833 unsignedcharRESERVED[1];
834 #endif 835
836 /*-----------------end of hardware supported fields----------------*/ 837 structaic7xxx_scb *next; /* next ptr when in free list */ 838 Scsi_Cmnd *cmd; /* Scsi_Cmnd for this scb */ 839 intstate; /* current state of scb */ 840 #defineSCB_FREE 0x00
841 #defineSCB_ACTIVE 0x01
842 #define SCB_ABORTED 0x02
843 #defineSCB_DEVICE_RESET 0x04
844 #define SCB_IMMED 0x08
845 #define SCB_SENSE 0x10
846 unsignedintposition; /* Position in scb array */ 847 #ifdefAIC7XXX_USE_SG 848 structscatterlistsg;
849 structscatterlistsense_sg;
850 #endif 851 unsignedcharsense_cmd[6]; /* Allocate 6 characters for sense command */ 852 };
853
854 staticstruct{ 855 unsignedcharerrno;
856 constchar *errmesg;
857 }hard_error[] = { 858 {ILLHADDR, "Illegal Host Access" },
859 {ILLSADDR, "Illegal Sequencer Address referrenced" },
860 {ILLOPCODE, "Illegal Opcode in sequencer program" },
861 {PARERR, "Sequencer Ram Parity Error" } 862 };
863
864 staticunsignedchar 865 generic_sense[] = {REQUEST_SENSE, 0, 0, 0, 255, 0 };
866
867 /* 868 * The maximum number of SCBs we could have for ANY type 869 * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE 870 * SEQUENCER CODE IF THIS IS MODIFIED! 871 */ 872 #defineAIC7XXX_MAXSCB 16
873
874 /* 875 * Define a structure used for each host adapter, only one per IRQ. 876 */ 877 structaic7xxx_host{ 878 intbase; /* card base address */ 879 intmaxscb; /* hardware SCBs */ 880 intnumscb; /* current number of scbs */ 881 intextended; /* extended xlate? */ 882 aha_typetype; /* card type */ 883 aha_bus_typebus_type; /* normal/twin/wide bus */ 884 unsignedchara_scanned; /* 0 not scanned, 1 scanned */ 885 unsignedcharb_scanned; /* 0 not scanned, 1 scanned */ 886 unsignedintisr_count; /* Interrupt count */ 887 volatileunsignedcharunpause; /* unpause value for HCNTRL */ 888 volatileunsignedcharpause; /* pause value for HCNTRL */ 889 volatileunsignedshortneedsdtr_copy; /* default config */ 890 volatileunsignedshortneedsdtr;
891 volatileunsignedshortsdtr_pending;
892 volatileunsignedshortneedwdtr_copy; /* default config */ 893 volatileunsignedshortneedwdtr;
894 volatileunsignedshortwdtr_pending;
895 structseeprom_configseeprom;
896 inthave_seeprom;
897 structScsi_Host *next; /* allow for multiple IRQs */ 898 structaic7xxx_scbscb_array[AIC7XXX_MAXSCB]; /* active commands */ 899 structaic7xxx_scb *free_scb; /* list of free SCBs */ 900 };
901
902 structaic7xxx_host_config{ 903 intirq; /* IRQ number */ 904 intbase; /* I/O base */ 905 intmaxscb; /* hardware SCBs */ 906 intunpause; /* unpause value for HCNTRL */ 907 intpause; /* pause value for HCNTRL */ 908 intscsi_id; /* host SCSI ID */ 909 intscsi_id_b; /* host SCSI ID B channel for twin cards */ 910 intextended; /* extended xlate? */ 911 intbusrtime; /* bus release time */ 912 aha_typetype; /* card type */ 913 aha_bus_typebus_type; /* normal/twin/wide bus */ 914 aha_status_typeparity; /* bus parity enabled/disabled */ 915 aha_status_typelow_term; /* bus termination low byte */ 916 aha_status_typehigh_term; /* bus termination high byte (wide cards only) */ 917 };
918
919 /* 920 * Valid SCSIRATE values. (p. 3-17) 921 * Provides a mapping of tranfer periods in ns to the proper value to 922 * stick in the scsiscfr reg to use that transfer rate. 923 */ 924 staticstruct{ 925 shortperiod;
926 shortrate;
927 constchar *english;
928 }aic7xxx_syncrates[] = { 929 { 100, 0, "10.0" },
930 { 125, 1, "8.0" },
931 { 150, 2, "6.67" },
932 { 175, 3, "5.7" },
933 { 200, 4, "5.0" },
934 { 225, 5, "4.4" },
935 { 250, 6, "4.0" },
936 { 275, 7, "3.6" } 937 };
938
939 staticintnum_aic7xxx_syncrates =
940 sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
941
942 #ifdefAIC7XXX_DEBUG 943 externintvsprintf(char *, constchar *, va_list);
944
945 staticvoid 946 debug(constchar *fmt, ...)
/* */ 947 { 948 va_listap;
949 charbuf[256];
950
951 va_start(ap, fmt);
952 vsprintf(buf, fmt, ap);
953 printk(buf);
954 va_end(ap);
955 } 956
957 staticvoid 958 debug_config(structaic7xxx_host_config *p)
/* */ 959 { 960 inthost_conf, scsi_conf;
961 unsignedcharbrelease;
962 unsignedchardfthresh;
963
964 staticintDFT[] = { 0, 50, 75, 100 };
965 staticintSST[] = { 256, 128, 64, 32 };
966 staticconstchar *BUSW[] = { "", "-TWIN", "-WIDE" };
967
968 host_conf = inb(HA_HOSTCONF(p->base));
969 scsi_conf = inb(HA_SCSICONF(p->base));
970
971 /* 972 * The 7870 gets the bus release time and data FIFO threshold 973 * from the serial EEPROM (stored in the config structure) and 974 * scsi_conf register respectively. The 7770 gets the bus 975 * release time and data FIFO threshold from the scsi_conf and 976 * host_conf registers respectively. 977 */ 978 if ((p->type == AIC_274x) || (p->type == AIC_284x))
979 { 980 dfthresh = host_conf >> 6;
981 } 982 else 983 { 984 dfthresh = scsi_conf >> 6;
985 } 986
987 brelease = p->busrtime;
988 if (brelease == 0)
989 { 990 brelease = 2;
991 } 992
993 switch (p->type)
994 { 995 caseAIC_274x:
996 printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
997 break;
998
999 caseAIC_284x:
1000 printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1001 break;
1002
1003 caseAIC_7870:
1004 printk("AIC7870%s (PCI-bus):\n", BUSW[p->bus_type]);
1005 break;
1006
1007 caseAIC_7850:
1008 printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
1009 break;
1010
1011 caseAIC_7872:
1012 printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
1013 break;
1014
1015 default:
1016 panic("aic7xxx debug_config: internal error\n");
1017 }1018
1019 printk(" irq %d\n"
1020 " bus release time %d bclks\n"
1021 " data fifo threshold %d%%\n",
1022 p->irq,
1023 brelease,
1024 DFT[dfthresh]);
1025
1026 printk(" SCSI CHANNEL A:\n"
1027 " scsi id %d\n"
1028 " scsi selection timeout %d ms\n"
1029 " scsi bus reset at power-on %sabled\n",
1030 scsi_conf & 0x07,
1031 SST[(scsi_conf >> 3) & 0x03],
1032 (scsi_conf & 0x40) ? "en" : "dis");
1033
1034 if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
1035 {/* Set the parity for 7770 based cards. */1036 p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
1037 }1038 if (p->parity != AIC_UNKNOWN)
1039 {1040 printk(" scsi bus parity %sabled\n",
1041 (p->parity == AIC_ENABLED) ? "en" : "dis");
1042 }1043
1044 if (p->type == AIC_274x)
1045 {1046 p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
1047 }1048 if (p->low_term != AIC_UNKNOWN)
1049 {1050 printk(" scsi bus termination (low byte) %sabled\n",
1051 (p->low_term == AIC_ENABLED) ? "en" : "dis");
1052 }1053 if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1054 {1055 printk(" scsi bus termination (high byte) %sabled\n",
1056 (p->high_term == AIC_ENABLED) ? "en" : "dis");
1057 }1058 }1059 #else1060 # definedebug(fmt, args...)
1061 # definedebug_config(x)
1062 #endifAIC7XXX_DEBUG1063
1064 /*1065 * XXX - these options apply unilaterally to _all_ 274x/284x/294x1066 * cards in the system. This should be fixed, but then,1067 * does anyone really have more than one in a machine?1068 */1069 staticintaic7xxx_extended = 0; /* extended translation on? */1070 staticintaic7xxx_no_reset = 0; /* no resetting of SCSI bus */1071
1072 /*+F*************************************************************************1073 * Function:1074 * aic7xxx_setup1075 *1076 * Description:1077 * Handle Linux boot parameters.1078 *-F*************************************************************************/1079 void1080 aic7xxx_setup(char *s, int *dummy)
/* */1081 {1082 inti;
1083 char *p;
1084
1085 staticstruct{1086 constchar *name;
1087 int *flag;
1088 }options[] = {1089 { "extended", &aic7xxx_extended},
1090 { "no_reset", &aic7xxx_no_reset},
1091 {NULL, NULL}1092 };
1093
1094 for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1095 {1096 for (i = 0; options[i].name; i++)
1097 {1098 if (!strcmp(options[i].name, p))
1099 {1100 *(options[i].flag) = !0;
1101 }1102 }1103 }1104 }1105
1106 /*+F*************************************************************************1107 * Function:1108 * aic7xxx_loadseq1109 *1110 * Description:1111 * Load the sequencer code into the controller memory.1112 *-F*************************************************************************/1113 staticvoid1114 aic7xxx_loadseq(intbase)
/* */1115 {1116 staticunsignedcharseqprog[] = {1117 /*1118 * Each sequencer instruction is 29 bits1119 * long (fill in the excess with zeroes)1120 * and has to be loaded from least -> most1121 * significant byte, so this table has the1122 * byte ordering reversed.1123 */1124 # include "aic7xxx_seq.h"
1125 };
1126
1127 /*1128 * When the AIC-7770 is paused (as on chip reset), the1129 * sequencer address can be altered and a sequencer1130 * program can be loaded by writing it, byte by byte, to1131 * the sequencer RAM port - the Adaptec documentation1132 * recommends using REP OUTSB to do this, hence the inline1133 * assembly. Since the address autoincrements as we load1134 * the program, reset it back to zero afterward. Disable1135 * sequencer RAM parity error detection while loading, and1136 * make sure the LOADRAM bit is enabled for loading.1137 */1138 outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1139
1140 asmvolatile("cld\n\t"
1141 "rep\n\t"
1142 "outsb"
1143 : /* no output */1144 :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1145 :"si", "cx", "dx");
1146
1147 /*1148 * WARNING! This is a magic sequence! After extensive1149 * experimentation, it seems that you MUST turn off the1150 * LOADRAM bit before you play with SEQADDR again, else1151 * you will end up with parity errors being flagged on1152 * your sequencer program. (You would also think that1153 * turning off LOADRAM and setting SEQRESET to reset the1154 * address to zero would work, but you need to do it twice1155 * for it to take effect on the address. Timing problem?)1156 */1157 do{1158 /*1159 * Actually, reset it until1160 * the address shows up as1161 * zero just to be safe..1162 */1163 outb(SEQRESET | FASTMODE, SEQCTL(base));
1164 }while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1165 }1166
1167 /*+F*************************************************************************1168 * Function:1169 * aic7xxx_delay1170 *1171 * Description:1172 * Delay for specified amount of time.1173 *-F*************************************************************************/1174 staticvoid1175 aic7xxx_delay(intseconds)
/* */1176 {1177 unsignedlongi;
1178
1179 i = jiffies + (seconds * HZ); /* compute time to stop */1180
1181 while (jiffies < i)
1182 {1183 ; /* Do nothing! */1184 }1185 }1186
1187 /*+F*************************************************************************1188 * Function:1189 * rcs_version1190 *1191 * Description:1192 * Return a string containing just the RCS version number from either1193 * an Id or Revison RCS clause.1194 *-F*************************************************************************/1195 constchar *
1196 rcs_version(constchar *version_info)
/* */1197 {1198 staticcharbuf[10];
1199 char *bp, *ep;
1200
1201 bp = NULL;
1202 strcpy(buf, "????");
1203 if (!strncmp(version_info, "$Id: ", 5))
1204 {1205 if ((bp = strchr(version_info, ' ')) != NULL)
1206 {1207 bp++;
1208 if ((bp = strchr(bp, ' ')) != NULL)
1209 {1210 bp++;
1211 }1212 }1213 }1214 else1215 {1216 if (!strncmp(version_info, "$Revision: ", 11))
1217 {1218 if ((bp = strchr(version_info, ' ')) != NULL)
1219 {1220 bp++;
1221 }1222 }1223 }1224
1225 if (bp != NULL)
1226 {1227 if ((ep = strchr(bp, ' ')) != NULL)
1228 {1229 registerintlen = ep - bp;
1230
1231 strncpy(buf, bp, len);
1232 buf[len] = '\0';
1233 }1234 }1235
1236 returnbuf;
1237 }1238
1239 /*+F*************************************************************************1240 * Function:1241 * aic7xxx_info1242 *1243 * Description:1244 * Return a string describing the driver.1245 *-F*************************************************************************/1246 constchar *
1247 aic7xxx_info(structScsi_Host *notused)
/* */1248 {1249 staticcharbuffer[128];
1250
1251 strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1252 strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1253 strcat(buffer, "/");
1254 strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1255 strcat(buffer, "/");
1256 strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1257
1258 returnbuffer;
1259 }1260
1261 /*+F*************************************************************************1262 * Function:1263 * aic7xxx_putscb1264 *1265 * Description:1266 * Transfer a SCB to the controller.1267 *-F*************************************************************************/1268 staticvoid1269 aic7xxx_putscb(intbase, structaic7xxx_scb *scb)
/* */1270 {1271 #ifdefAIC7XXX_USE_DMA1272 /*1273 * All we need to do, is to output the position1274 * of the SCB in the SCBARRAY to the QINFIFO1275 * of the host adapter.1276 */1277 outb(scb->position, QINFIFO(base));
1278 #else1279 /*1280 * By turning on the SCB auto increment, any reference1281 * to the SCB I/O space postincrements the SCB address1282 * we're looking at. So turn this on and dump the relevant1283 * portion of the SCB to the card.1284 */1285 outb(SCBAUTO, SCBCNT(base));
1286
1287 asmvolatile("cld\n\t"
1288 "rep\n\t"
1289 "outsb"
1290 : /* no output */1291 :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1292 :"si", "cx", "dx");
1293
1294 outb(0, SCBCNT(base));
1295 #endif1296 }1297
1298 /*+F*************************************************************************1299 * Function:1300 * aic7xxx_putdmascb1301 *1302 * Description:1303 * DMA a SCB to the controller.1304 *-F*************************************************************************/1305 staticvoid1306 aic7xxx_putdmascb(intbase, structaic7xxx_scb *scb)
/* */1307 {1308 /*1309 * By turning on the SCB auto increment, any reference1310 * to the SCB I/O space postincrements the SCB address1311 * we're looking at. So turn this on and dump the relevant1312 * portion of the SCB to the card.1313 */1314 outb(SCBAUTO, SCBCNT(base));
1315
1316 asmvolatile("cld\n\t"
1317 "rep\n\t"
1318 "outsb"
1319 : /* no output */1320 :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1321 :"si", "cx", "dx");
1322
1323 outb(0, SCBCNT(base));
1324 }1325
1326 /*+F*************************************************************************1327 * Function:1328 * aic7xxx_getscb1329 *1330 * Description:1331 * Get a SCB from the controller.1332 *-F*************************************************************************/1333 staticvoid1334 aic7xxx_getscb(intbase, structaic7xxx_scb *scb)
/* */1335 {1336 /*1337 * This is almost identical to aic7xxx_putscb().1338 */1339 outb(SCBAUTO, SCBCNT(base));
1340
1341 asmvolatile("cld\n\t"
1342 "rep\n\t"
1343 "insb"
1344 : /* no output */1345 :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1346 :"di", "cx", "dx");
1347
1348 outb(0, SCBCNT(base));
1349 }1350
1351 /*+F*************************************************************************1352 * Function:1353 * aic7xxx_length1354 *1355 * Description:1356 * How much data should be transferred for this SCSI command? Stop1357 * at segment sg_last if it's a scatter-gather command so we can1358 * compute underflow easily.1359 *-F*************************************************************************/1360 staticunsigned1361 aic7xxx_length(Scsi_Cmnd *cmd, intsg_last)
/* */1362 {1363 inti, segments;
1364 unsignedlength;
1365 structscatterlist *sg;
1366
1367 segments = cmd->use_sg - sg_last;
1368 sg = (structscatterlist *) cmd->buffer;
1369
1370 if (cmd->use_sg)
1371 {1372 for (i = length = 0; i < cmd->use_sg && i < segments; i++)
1373 {1374 length += sg[i].length;
1375 }1376 }1377 else1378 {1379 length = cmd->request_bufflen;
1380 }1381
1382 return (length);
1383 }1384
1385 /*+F*************************************************************************1386 * Function:1387 * aic7xxx_scsirate1388 *1389 * Description:1390 * Look up the valid period to SCSIRATE conversion in our table1391 *-F*************************************************************************/1392 staticvoid1393 aic7xxx_scsirate(unsignedchar *scsirate, unsignedcharperiod,
/* */1394 unsignedcharoffset, inttarget)
1395 {1396 inti;
1397
1398 for (i = 0; i < num_aic7xxx_syncrates; i++)
1399 {1400 if ((aic7xxx_syncrates[i].period - period) >= 0)
1401 {1402 *scsirate = (aic7xxx_syncrates[i].rate << 4) | (offset & 0x0F);
1403 printk("aic7xxx: target %d now synchronous at %sMb/s, offset = 0x%x\n",
1404 target, aic7xxx_syncrates[i].english, offset);
1405 return;
1406 }1407 }1408
1409 /*1410 * Default to asyncronous transfer1411 */1412 *scsirate = 0;
1413 printk("aic7xxx: target %d using asynchronous transfers\n", target);
1414 }1415
1416 /*+F*************************************************************************1417 * Function:1418 * aic7xxx_isr1419 *1420 * Description:1421 * SCSI controller interrupt handler.1422 *1423 * NOTE: Since we declared this using SA_INTERRUPT, interrupts should1424 * be disabled all through this function unless we say otherwise.1425 *-F*************************************************************************/1426 staticvoid1427 aic7xxx_isr(intirq, structpt_regs * regs)
/* */1428 {1429 intbase, intstat;
1430 structaic7xxx_host *p;
1431 structaic7xxx_scb *scb;
1432 unsignedcharactive, ha_flags, transfer;
1433 unsignedcharscsi_id, bus_width;
1434 unsignedcharoffset, rate, scratch;
1435 unsignedcharmax_offset, rej_byte;
1436 unsignedcharhead, tail;
1437 unsignedshorttarget_mask;
1438 longflags;
1439 void *addr;
1440 intactual;
1441 inttarget, tcl;
1442 intscbptr;
1443 Scsi_Cmnd *cmd;
1444
1445 p = (structaic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1446
1447 /*1448 * Search for the host with a pending interrupt. If we can't find1449 * one, then we've encountered a spurious interrupt.1450 */1451 while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
1452 {1453 if (p->next == NULL)
1454 {1455 p = NULL;
1456 }1457 else1458 {1459 p = (structaic7xxx_host *) p->next->hostdata;
1460 }1461 }1462
1463 if (p == NULL)
1464 {1465 if (aic7xxx_spurious_count == 1)
1466 {1467 aic7xxx_spurious_count = 2;
1468 printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1469 return;
1470 }1471 else1472 {1473 /*1474 * The best we can do is to set p back to head of list and process1475 * the erroneous interrupt - most likely a BRKADRINT.1476 */1477 p = (structaic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1478 }1479 }1480
1481 p->isr_count++; /* Keep track of interrupts for /proc/scsi */1482
1483 if ((p->a_scanned == 0) && (p->isr_count == 1))
1484 {1485 /*1486 * We must only have one card at this IRQ and it must have been1487 * added to the board data before the spurious interrupt occurred.1488 * It is sufficient that we check isr_count and not the spurious1489 * interrupt count.1490 */1491 printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1492 return;
1493 }1494
1495 base = p->base;
1496 /*1497 * Handle all the interrupt sources - especially for SCSI1498 * interrupts, we won't get a second chance at them.1499 */1500 intstat = inb(INTSTAT(base));
1501
1502 if (intstat & BRKADRINT)
1503 {1504 inti;
1505 unsignedcharerrno = inb(ERROR(base));
1506
1507 printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
1508 for (i = 0; i < NUMBER(hard_error); i++)
1509 {1510 if (errno & hard_error[i].errno)
1511 {1512 printk(" %s\n", hard_error[i].errmesg);
1513 }1514 }1515
1516 panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
1517 inb(ERROR(base)),
1518 inb(SEQADDR1(base)) << 8 | inb(SEQADDR0(base)));
1519 }1520
1521 if (intstat & SEQINT)
1522 {1523 /*1524 * Although the sequencer is paused immediately on1525 * a SEQINT, an interrupt for a SCSIINT or a CMDCMPLT1526 * condition will have unpaused the sequencer before1527 * this point.1528 */1529 PAUSE_SEQUENCER(p);
1530
1531 switch (intstat & SEQINT_MASK)
1532 {1533 caseBAD_PHASE:
1534 panic("aic7xxx_isr: unknown scsi bus phase\n");
1535 break;
1536
1537 caseSEND_REJECT:
1538 rej_byte = inb(HA_REJBYTE(base));
1539 scsi_id = inb(SCSIID(base)) >> 0x04;
1540 scbptr = inb(SCBPTR(base));
1541 scb = &(p->scb_array[scbptr]);
1542 if (rej_byte != 0x20)
1543 {1544 debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
1545 rej_byte);
1546 }1547 else1548 {1549 printk("aic7xxx_isr warning: Tagged message rejected for target %d,"
1550 " channel %c.\n",
1551 scsi_id, (inb(SBLKCTL(base)) & SELBUSB ? 'B': 'A'));
1552 scb->cmd->device->tagged_supported = 0;
1553 scb->cmd->device->tagged_queue = 0;
1554 }1555 break;
1556
1557 caseNO_IDENT:
1558 panic("aic7xxx_isr: reconnecting target %d at seqaddr 0x%x "
1559 "didn't issue IDENTIFY message\n",
1560 (inb(SELID(base)) >> 4) & 0x0F,
1561 (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
1562 break;
1563
1564 caseNO_MATCH:
1565 tcl = inb(SCBARRAY(base) + 1);
1566 target = (tcl >> 4) & 0x0F;
1567 /* Purposefully mask off the top bit of targets 8-15. */1568 target_mask = 0x01 << (target & 0x07);
1569
1570 debug("aic7xxx_isr: sequencer couldn't find match "
1571 "for reconnecting target %d, channel %d, lun %d - "
1572 "issuing ABORT\n", target, (tcl & 0x08) >> 3, tcl & 0x07);
1573 if (tcl & 0x88)
1574 {1575 /* Second channel stores its info in byte1576 * two of HA_ACTIVE1577 */1578 active = inb(HA_ACTIVE1(base));
1579 active = active & ~(target_mask);
1580 outb(active, HA_ACTIVE1(base));
1581 }1582 else1583 {1584 active = inb(HA_ACTIVE0(base));
1585 active = active & ~(target_mask);
1586 outb(active, HA_ACTIVE0(base));
1587 }1588 #ifdefAIC7XXX_USE_DMA1589 outb(SCB_NEEDDMA, SCBARRAY(base));
1590 #endif1591
1592 /*1593 * Check out why this use to be outb(0x80, CLRINT(base))1594 * clear the timeout1595 */1596 outb(CLRSELTIMEO, CLRSINT1(base));
1597 RESTART_SEQUENCER(p);
1598 break;
1599
1600 caseMSG_SDTR:
1601 /*1602 * Help the sequencer to translate the negotiated1603 * transfer rate. Transfer is 1/4 the period1604 * in ns as is returned by the sync negotiation1605 * message. So, we must multiply by four.1606 */1607 transfer = (inb(HA_ARG_1(base)) << 2);
1608 offset = inb(ACCUM(base));
1609 scsi_id = inb(SCSIID(base)) >> 0x04;
1610 if (inb(SBLKCTL(base)) & 0x08)
1611 {1612 scsi_id = scsi_id + 8; /* B channel */1613 }1614 target_mask = (0x01 << scsi_id);
1615 scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1616 /*1617 * The maximum offset for a wide device is 0x08; for a1618 * 8-bit bus device the maximum offset is 0x0f.1619 */1620 if (scratch & 0x80)
1621 {1622 max_offset = 0x08;
1623 }1624 else1625 {1626 max_offset = 0x0f;
1627 }1628 aic7xxx_scsirate(&rate, transfer, MIN(offset, max_offset), scsi_id);
1629 /*1630 * Preserve the wide transfer flag.1631 */1632 rate = rate | (scratch & 0x80);
1633 outb(rate, HA_TARG_SCRATCH(base) + scsi_id);
1634 outb(rate, SCSIRATE(base));
1635 if ((rate & 0xf) == 0)
1636 {/*1637 * The requested rate was so low that asynchronous transfers1638 * are faster (not to mention the controller won't support1639 * them), so we issue a reject to ensure we go to asynchronous1640 * transfers.1641 */1642 outb(SEND_REJ, HA_RETURN_1(base));
1643 }1644 else1645 {1646 /*1647 * See if we initiated Sync Negotiation1648 */1649 if (p->sdtr_pending & target_mask)
1650 {1651 /*1652 * Don't send an SDTR back to the target.1653 */1654 outb(0, HA_RETURN_1(base));
1655 }1656 else1657 {1658 /*1659 * Send our own SDTR in reply.1660 */1661 printk("aic7xxx_isr: Sending SDTR!!\n");
1662 outb(SEND_SDTR, HA_RETURN_1(base));
1663 }1664 }1665 /*1666 * Clear the flags.1667 */1668 p->needsdtr = p->needsdtr & ~target_mask;
1669 p->sdtr_pending = p->sdtr_pending & ~target_mask;
1670 break;
1671
1672 caseMSG_WDTR:
1673 {1674 bus_width = inb(ACCUM(base));
1675 scsi_id = inb(SCSIID(base)) >> 0x04;
1676 if (inb(SBLKCTL(base)) & 0x08)
1677 {1678 scsi_id = scsi_id + 8; /* B channel */1679 }1680 printk("aic7xxx_isr: Received MSG_WDTR, scsi_id = %d, "
1681 "needwdtr = 0x%x\n", scsi_id, p->needwdtr);
1682 scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1683
1684 target_mask = (0x01 << scsi_id);
1685 if (p->wdtr_pending & target_mask)
1686 {1687 /*1688 * Don't send an WDTR back to the target, since we asked first.1689 */1690 outb(0, HA_RETURN_1(base));
1691 switch (bus_width)
1692 {1693 caseBUS_8_BIT:
1694 scratch = scratch & 0x7F;
1695 break;
1696
1697 caseBUS_16_BIT:
1698 printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1699 scsi_id);
1700 scratch = scratch | 0x80;
1701 break;
1702 }1703 }1704 else1705 {1706 /*1707 * Send our own WDTR in reply.1708 */1709 printk("aic7xxx_isr: Will send WDTR!!\n");
1710 switch (bus_width)
1711 {1712 caseBUS_8_BIT:
1713 scratch = scratch & 0x7F;
1714 break;
1715
1716 caseBUS_32_BIT:
1717 /* Negotiate 16 bits. */1718 bus_width = BUS_16_BIT;
1719 /* Yes, we mean to fall thru here */1720
1721 caseBUS_16_BIT:
1722 printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1723 scsi_id);
1724 scratch = scratch | 0x80;
1725 break;
1726 }1727 outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
1728 }1729 p->needwdtr = p->needwdtr & ~target_mask;
1730 p->wdtr_pending = p->wdtr_pending & ~target_mask;
1731 outb(scratch, HA_TARG_SCRATCH(base) + scsi_id);
1732 outb(scratch, SCSIRATE(base));
1733 break;
1734 }1735
1736 caseMSG_REJECT:
1737 {1738 /*1739 * What we care about here is if we had an1740 * outstanding SDTR or WDTR message for this1741 * target. If we did, this is a signal that1742 * the target is refusing negotiation.1743 */1744
1745 unsignedchartarg_scratch, scsi_id;
1746 unsignedshortmask;
1747
1748 scsi_id = inb(SCSIID(base)) >> 0x04;
1749 if (inb(SBLKCTL(base)) & 0x08)
1750 {1751 scsi_id = scsi_id + 8;
1752 }1753
1754 mask = (0x01 << scsi_id);
1755
1756 targ_scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1757
1758 if (p->wdtr_pending & mask)
1759 {1760 /*1761 * note 8bit xfers and clear flag1762 */1763 targ_scratch = targ_scratch & 0x7F;
1764 p->needwdtr = p->needwdtr & ~mask;
1765 p->wdtr_pending = p->wdtr_pending & ~mask;
1766 outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1767 printk("aic7xxx: target %d refusing WIDE negotiation. Using "
1768 "8 bit transfers\n", scsi_id);
1769 }1770 else1771 {1772 if (p->sdtr_pending & mask)
1773 {1774 /*1775 * note asynch xfers and clear flag1776 */1777 targ_scratch = targ_scratch & 0xF0;
1778 p->needsdtr = p->needsdtr & ~mask;
1779 p->sdtr_pending = p->sdtr_pending & ~mask;
1780 outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1781 printk("aic7xxx: target %d refusing syncronous negotiation. Using "
1782 "asyncronous transfers\n", scsi_id);
1783 }1784 /*1785 * Otherwise, we ignore it.1786 */1787 }1788 outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1789 outb(targ_scratch, SCSIRATE(base));
1790 break;
1791 }1792
1793 caseBAD_STATUS:
1794 scsi_id = inb(SCSIID(base)) >> 0x04;
1795 scbptr = inb(SCBPTR(base));
1796 scb = &(p->scb_array[scbptr]);
1797 outb(0, HA_RETURN_1(base)); /* CHECK_CONDITION may change this */1798 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1799 {1800 printk("aic7xxx_isr: referenced scb not valid "
1801 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1802 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1803 }1804 else1805 {1806 cmd = scb->cmd;
1807 aic7xxx_getscb(base, scb);
1808 aic7xxx_status(cmd) = scb->target_status;
1809
1810 cmd->result = cmd->result | scb->target_status;
1811
1812 /*1813 * This test is just here for debugging purposes.1814 * It will go away when the timeout problem is resolved.1815 */1816 switch (status_byte(scb->target_status))
1817 {1818 caseGOOD:
1819 break;
1820
1821 caseCHECK_CONDITION:
1822 if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
1823 {1824 void *req_buf;
1825 #ifndefAIC7XXX_USE_SG1826 unsignedintreq_buflen;
1827 #endif1828
1829 /* Update the timeout for the SCSI command. */1830 /* update_timeout(cmd, SENSE_TIMEOUT); */1831
1832 /* Send a sense command to the requesting target. */1833 cmd->flags = cmd->flags | WAS_SENSE;
1834 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
1835 sizeof(generic_sense));
1836
1837 scb->sense_cmd[1] = cmd->lun << 5;
1838 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
1839
1840 #ifdefAIC7XXX_USE_SG1841 scb->sense_sg.address = (char *) &cmd->sense_buffer;
1842 scb->sense_sg.length = sizeof(cmd->sense_buffer);
1843 req_buf = &scb->sense_sg;
1844 #else1845 req_buf = &cmd->sense_buffer;
1846 req_buflen = sizeof(cmd->sense_buffer);
1847 #endif1848 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
1849 memset(scb, 0, SCB_DOWNLOAD_SIZE);
1850 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
1851 ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
1852 addr = scb->sense_cmd;
1853 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
1854 memcpy(scb->SCSI_cmd_pointer, &addr,
1855 sizeof(scb->SCSI_cmd_pointer));
1856 #ifdefAIC7XXX_USE_SG1857 scb->SG_segment_count = 1;
1858 memcpy(scb->SG_list_pointer, &req_buf,
1859 sizeof(scb->SG_list_pointer));
1860 #else1861 scb->SG_segment_count = 0;
1862 memcpy(scb->data_pointer, &req_buf,
1863 sizeof(scb->data_pointer));
1864 memcpy(scb->data_count, &req_buflen, 3);
1865 #endif1866
1867 outb(SCBAUTO, SCBCNT(base));
1868 asmvolatile("cld\n\t"
1869 "rep\n\t"
1870 "outsb"
1871 : /* no output */1872 :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1873 :"si", "cx", "dx");
1874 outb(0, SCBCNT(base));
1875 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
1876
1877 /*1878 * Add this SCB to the "waiting for selection" list.1879 */1880 head = inb(WAITING_SCBH(base));
1881 tail = inb(WAITING_SCBT(base));
1882 if (head & SCB_LIST_NULL)
1883 {/* list is empty */1884 head = scb->position;
1885 tail = SCB_LIST_NULL;
1886 }1887 else1888 {1889 if (tail & SCB_LIST_NULL)
1890 {/* list has one element */1891 tail = scb->position;
1892 outb(head, SCBPTR(base));
1893 outb(tail, (SCBARRAY(base) + 30));
1894 }1895 else1896 {/* list has more than one element */1897 outb(tail, SCBPTR(base));
1898 tail = scb->position;
1899 outb(tail, (SCBARRAY(base) + 30));
1900 }1901 }1902 outb(head, WAITING_SCBH(base));
1903 outb(tail, WAITING_SCBT(base));
1904 outb(SEND_SENSE, HA_RETURN_1(base));
1905 }/* first time sense, no errors */1906 else1907 {1908 /*1909 * Indicate that we asked for sense, have the sequencer do1910 * a normal command complete, and have the scsi driver handle1911 * this condition.1912 */1913 cmd->flags = cmd->flags | ASKED_FOR_SENSE;
1914 }1915 break;
1916
1917 caseBUSY:
1918 printk("aic7xxx_isr: Target busy\n");
1919 if (!aic7xxx_error(cmd))
1920 {1921 aic7xxx_error(cmd) = DID_BUS_BUSY;
1922 }1923 break;
1924
1925 caseQUEUE_FULL:
1926 printk("aic7xxx_isr: Queue full\n");
1927 if (!aic7xxx_error(cmd))
1928 {1929 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1930 }1931 break;
1932
1933 default:
1934 printk("aic7xxx_isr: Unexpected target status 0x%x\n",
1935 scb->target_status);
1936 if (!aic7xxx_error(cmd))
1937 {1938 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1939 }1940 break;
1941 }/* end switch */1942 }/* end else of */1943 break;
1944
1945 caseRESIDUAL:
1946 scbptr = inb(SCBPTR(base));
1947 scb = &(p->scb_array[scbptr]);
1948 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1949 {1950 printk("aic7xxx_isr: referenced scb not valid "
1951 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1952 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1953 }1954 else1955 {1956 cmd = scb->cmd;
1957 /*1958 * Don't destroy valid residual information with1959 * residual coming from a check sense operation.1960 */1961 if (!(cmd->flags & WAS_SENSE))
1962 {1963 /*1964 * We had an underflow. At this time, there's only1965 * one other driver that bothers to check for this,1966 * and cmd->underflow seems to be set rather half-1967 * heartedly in the higher-level SCSI code.1968 */1969 actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
1970
1971 actual -= ((inb(SCBARRAY(base + 17)) << 16) |
1972 (inb(SCBARRAY(base + 16)) << 8) |
1973 inb(SCBARRAY(base + 15)));
1974
1975 if (actual < cmd->underflow)
1976 {1977 printk("aic7xxx: target %d underflow - "
1978 "wanted (at least) %u, got %u\n",
1979 cmd->target, cmd->underflow, actual);
1980
1981 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1982 aic7xxx_status(cmd) = scb->target_status;
1983 }1984 }1985 }1986 break;
1987
1988 caseABORT_TAG:
1989 scbptr = inb(SCBPTR(base));
1990 scb = &(p->scb_array[scbptr]);
1991 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1992 {1993 printk("aic7xxx_isr: referenced scb not valid "
1994 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1995 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1996 }1997 else1998 {1999 cmd = scb->cmd;
2000 /*2001 * We didn't recieve a valid tag back from the target2002 * on a reconnect.2003 */2004 printk("aic7xxx_isr: invalid tag recieved on channel %c "
2005 "target %d, lun %d -- sending ABORT_TAG\n",
2006 (cmd->channel & 0x01) ? 'B':'A',
2007 cmd->target, cmd->lun & 0x07);
2008 /*2009 * This is a critical section, since we don't want the2010 * queue routine mucking with the host data.2011 */2012 save_flags(flags);
2013 cli();
2014
2015 /*2016 * Process the command after marking the scb as free2017 * and adding it to the free list.2018 */2019 scb->state = SCB_FREE;
2020 scb->cmd = NULL;
2021 scb->next = p->free_scb; /* preserve next pointer */2022 p->free_scb = scb; /* add at head of list */2023
2024 restore_flags(flags);
2025 cmd->result = (DID_RETRY_COMMAND << 16);
2026 cmd->scsi_done(cmd);
2027 }2028 break;
2029
2030 caseAWAITING_MSG:
2031 scbptr = inb(SCBPTR(base));
2032 scb = &(p->scb_array[scbptr]);
2033 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2034 {2035 printk("aic7xxx_isr: referenced scb not valid "
2036 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2037 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
2038 }2039 else2040 {2041 /*2042 * This SCB had a zero length command, informing the sequencer2043 * that we wanted to send a special message to this target.2044 * We only do this for BUS_DEVICE_RESET messages currently.2045 */2046 if (scb->state & SCB_DEVICE_RESET)
2047 {2048 outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
2049 outb(1, HA_MSG_LEN(base));
2050 }2051 else2052 {2053 panic("aic7xxx_isr: AWAITING_SCB for an SCB that does "
2054 "not have a waiting message");
2055 }2056 }2057 break;
2058
2059 default: /* unknown */2060 debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
2061 intstat, inb(SCSISIGI(base)));
2062 break;
2063 }2064 outb(CLRSEQINT, CLRINT(base));
2065 UNPAUSE_SEQUENCER(p);
2066 }2067
2068 if (intstat & SCSIINT)
2069 {2070 intstatus = inb(SSTAT1(base));
2071
2072 scbptr = inb(SCBPTR(base));
2073 scb = &p->scb_array[scbptr];
2074 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2075 {2076 printk("aic7xxx_isr: no command for scb (scsiint)\n");
2077 /*2078 * Turn off the interrupt and set status2079 * to zero, so that it falls through the2080 * reset of the SCSIINT code.2081 */2082 outb(status, CLRSINT1(base));
2083 UNPAUSE_SEQUENCER(p);
2084 outb(CLRSCSIINT, CLRINT(base));
2085 status = 0;
2086 scb = NULL;
2087 }2088 else2089 {2090 cmd = scb->cmd;
2091
2092 /*2093 * Only the SCSI Status 1 register has information2094 * about exceptional conditions that we'd have a2095 * SCSIINT about; anything in SSTAT0 will be handled2096 * by the sequencer. Note that there can be multiple2097 * bits set.2098 */2099 if (status & SELTO)
2100 {2101 unsignedchartarget_mask = (1 << (cmd->target & 0x07));
2102 unsignedcharwaiting;
2103
2104 /*2105 * Hardware selection timer has expired. Turn2106 * off SCSI selection sequence.2107 */2108 outb(ENRSELI, SCSISEQ(base));
2109 cmd->result = (DID_TIME_OUT << 16);
2110 /*2111 * Clear an pending messages for the timed out2112 * target and mark the target as free.2113 */2114 ha_flags = inb(HA_FLAGS(base));
2115 outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2116
2117 if (scb->target_channel_lun & 0x88)
2118 {2119 active = inb(HA_ACTIVE1(base));
2120 active = active & ~(target_mask);
2121 outb(active, HA_ACTIVE1(base));
2122 }2123 else2124 {2125 active = inb(HA_ACTIVE0(base));
2126 active = active & ~(target_mask);
2127 outb(active, HA_ACTIVE0(base));
2128 }2129
2130 #ifdefAIC7XXX_USE_DMA2131 outb(SCB_NEEDDMA, SCBARRAY(base));
2132 #endif2133
2134 /*2135 * Shut off the offending interrupt sources, reset2136 * the sequencer address to zero and unpause it,2137 * then call the high-level SCSI completion routine.2138 *2139 * WARNING! This is a magic sequence! After many2140 * hours of guesswork, turning off the SCSI interrupts2141 * in CLRSINT? does NOT clear the SCSIINT bit in2142 * INTSTAT. By writing to the (undocumented, unused2143 * according to the AIC-7770 manual) third bit of2144 * CLRINT, you can clear INTSTAT. But, if you do it2145 * while the sequencer is paused, you get a BRKADRINT2146 * with an Illegal Host Address status, so the2147 * sequencer has to be restarted first.2148 */2149 outb(CLRSELTIMEO, CLRSINT1(base));
2150
2151 outb(CLRSCSIINT, CLRINT(base));
2152
2153 /* Shift the waiting for selection queue forward */2154 waiting = inb(WAITING_SCBH(base));
2155 outb(waiting, SCBPTR(base));
2156 waiting = inb(SCBARRAY(base) + 30);
2157 outb(waiting, WAITING_SCBH(base));
2158
2159 RESTART_SEQUENCER(p);
2160 /*2161 * This is a critical section, since we don't want the2162 * queue routine mucking with the host data.2163 */2164 save_flags(flags);
2165 cli();
2166
2167 /*2168 * Process the command after marking the scb as free2169 * and adding it to the free list.2170 */2171 scb->state = SCB_FREE;
2172 scb->cmd = NULL;
2173 scb->next = p->free_scb; /* preserve next pointer */2174 p->free_scb = scb; /* add at head of list */2175
2176 restore_flags(flags);
2177
2178 cmd->scsi_done(cmd);
2179 #if 0
2180 printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2181 scb->position, scb->state, (unsignedint) scb->cmd);
2182 #endif2183 }2184 else2185 {2186 if (status & SCSIPERR)
2187 {2188 /*2189 * A parity error has occurred during a data2190 * transfer phase. Flag it and continue.2191 */2192 printk("aic7xxx: parity error on target %d, "
2193 "channel %d, lun %d\n",
2194 cmd->target,
2195 cmd->channel & 0x01,
2196 cmd->lun & 0x07);
2197 aic7xxx_error(cmd) = DID_PARITY;
2198
2199 /*2200 * Clear interrupt and resume as above.2201 */2202 outb(CLRSCSIPERR, CLRSINT1(base));
2203 UNPAUSE_SEQUENCER(p);
2204
2205 outb(CLRSCSIINT, CLRINT(base));
2206 scb = NULL;
2207 }2208 else2209 {2210 if (!(status & BUSFREE))
2211 {2212 /*2213 * We don't know what's going on. Turn off the2214 * interrupt source and try to continue.2215 */2216 printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2217 outb(status, CLRSINT1(base));
2218 UNPAUSE_SEQUENCER(p);
2219 outb(CLRSCSIINT, CLRINT(base));
2220 scb = NULL;
2221 }2222 }2223 }2224 }/* else */2225 }2226
2227 if (intstat & CMDCMPLT)
2228 {2229 intcomplete;
2230
2231 /*2232 * The sequencer will continue running when it2233 * issues this interrupt. There may be >1 commands2234 * finished, so loop until we've processed them all.2235 */2236 do{2237 complete = inb(QOUTFIFO(base));
2238
2239 scb = &(p->scb_array[complete]);
2240 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2241 {2242 printk("aic7xxx warning: "
2243 "no command for scb %d (cmdcmplt)\n"
2244 "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x\n",
2245 complete, inb(QOUTFIFO(base)),
2246 scb->state, (unsignedint) scb->cmd);
2247 outb(CLRCMDINT, CLRINT(base));
2248 continue;
2249 }2250 cmd = scb->cmd;
2251
2252 cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2253 if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2254 {/* Got sense information. */2255 cmd->flags = cmd->flags & ASKED_FOR_SENSE;
2256 }2257 #if 0
2258 printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2259 scb->state, (unsignedint) scb->cmd, (unsignedint) p->free_scb);
2260 #endif2261 /*2262 * This is a critical section, since we don't want the2263 * queue routine mucking with the host data.2264 */2265 save_flags(flags);
2266 cli();
2267
2268 scb->state = SCB_FREE;
2269 scb->next = p->free_scb;
2270 scb->cmd = NULL;
2271 p->free_scb = &(p->scb_array[scb->position]);
2272
2273 restore_flags(flags);
2274 #if 0
2275 if (scb != &p->scb_array[scb->position])
2276 {2277 printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
2278 }2279 printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2280 scb->state, (unsignedint) scb->cmd, (unsignedint) p->free_scb);
2281 #endif2282
2283 cmd->scsi_done(cmd);
2284
2285 /*2286 * Clear interrupt status before checking2287 * the output queue again. This eliminates2288 * a race condition whereby a command could2289 * complete between the queue poll and the2290 * interrupt clearing, so notification of the2291 * command being complete never made it back2292 * up to the kernel.2293 */2294 outb(CLRCMDINT, CLRINT(base));
2295 }while (inb(QOUTCNT(base)));
2296 }2297 }2298
2299 /*+F*************************************************************************2300 * Function:2301 * aic7xxx_probe2302 *2303 * Description:2304 * Probing for EISA boards: it looks like the first two bytes2305 * are a manufacturer code - three characters, five bits each:2306 *2307 * BYTE 0 BYTE 1 BYTE 2 BYTE 32308 * ?1111122 22233333 PPPPPPPP RRRRRRRR2309 *2310 * The characters are baselined off ASCII '@', so add that value2311 * to each to get the real ASCII code for it. The next two bytes2312 * appear to be a product and revision number, probably vendor-2313 * specific. This is what is being searched for at each port,2314 * and what should probably correspond to the ID= field in the2315 * ECU's .cfg file for the card - if your card is not detected,2316 * make sure your signature is listed in the array.2317 *2318 * The fourth byte's lowest bit seems to be an enabled/disabled2319 * flag (rest of the bits are reserved?).2320 *-F*************************************************************************/2321 staticaha_type2322 aic7xxx_probe(intslot, intbase)
/* */2323 {2324 inti;
2325 unsignedcharbuf[4];
2326
2327 staticstruct{2328 intn;
2329 unsignedcharsignature[sizeof(buf)];
2330 aha_typetype;
2331 }AIC7xxx[] = {2332 { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x}, /* host adapter 274x */2333 { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x}, /* motherboard 274x */2334 { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x}, /* 284x, BIOS enabled */2335 { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x}/* 284x, BIOS disabled */2336 };
2337
2338 /*2339 * The VL-bus cards need to be primed by2340 * writing before a signature check.2341 */2342 for (i = 0; i < sizeof(buf); i++)
2343 {2344 outb(0x80 + i, base);
2345 buf[i] = inb(base + i);
2346 }2347
2348 for (i = 0; i < NUMBER(AIC7xxx); i++)
2349 {2350 /*2351 * Signature match on enabled card?2352 */2353 if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
2354 {2355 if (inb(base + 4) & 1)
2356 {2357 return (AIC7xxx[i].type);
2358 }2359
2360 printk("aic7xxx disabled at slot %d, ignored\n", slot);
2361 }2362 }2363
2364 return (AIC_NONE);
2365 }2366
2367 /*+F*************************************************************************2368 * Function:2369 * read_seeprom2370 *2371 * Description:2372 * Reads the serial EEPROM and returns 1 if successful and 0 if2373 * not successful.2374 *2375 * The instruction set of the 93C46 chip is as follows:2376 *2377 * Start OP2378 * Function Bit Code Address Data Description2379 * -------------------------------------------------------------------2380 * READ 1 10 A5 - A0 Reads data stored in memory,2381 * starting at specified address2382 * EWEN 1 00 11XXXX Write enable must preceed2383 * all programming modes2384 * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A02385 * WRITE 1 01 A5 - A0 D15 - D0 Writes register2386 * ERAL 1 00 10XXXX Erase all registers2387 * WRAL 1 00 01XXXX D15 - D0 Writes to all registers2388 * EWDS 1 00 00XXXX Disables all programming2389 * instructions2390 * *Note: A value of X for address is a don't care condition.2391 *2392 * The 93C46 has a four wire interface: clock, chip select, data in, and2393 * data out. In order to perform one of the above functions, you need2394 * to enable the chip select for a clock period (typically a minimum of2395 * 1 usec, with the clock high and low a minimum of 750 and 250 nsec2396 * respectively. While the chip select remains high, you can clock in2397 * the instructions (above) starting with the start bit, followed by the2398 * OP code, Address, and Data (if needed). For the READ instruction, the2399 * requested 16-bit register contents is read from the data out line but2400 * is preceded by an initial zero (leading 0, followed by 16-bits, MSB2401 * first). The clock cycling from low to high initiates the next data2402 * bit to be sent from the chip.2403 *2404 * The 7870 interface to the 93C46 serial EEPROM is through the SEECTL2405 * register. After successful arbitration for the memory port, the2406 * SEECS bit of the SEECTL register is connected to the chip select.2407 * The SEECK, SEEDO, and SEEDI are connected to the clock, data out,2408 * and data in lines respectively. The SEERDY bit of SEECTL is useful2409 * in that it gives us an 800 nsec timer. After a write to the SEECTL2410 * register, the SEERDY goes high 800 nsec later. The one exception2411 * to this is when we first request access to the memory port. The2412 * SEERDY goes high to signify that access has been granted and, for2413 * this case, has no implied timing.2414 *2415 *-F*************************************************************************/2416 staticint2417 read_seeprom(intbase, structseeprom_config *sc)
/* */2418 {2419 inti = 0, k = 0;
2420 unsignedlongtimeout;
2421 unsignedchartemp;
2422 unsignedshortchecksum = 0;
2423 unsignedshort *seeprom = (unsignedshort *) sc;
2424 structseeprom_cmd{2425 unsignedcharlen;
2426 unsignedcharbits[3];
2427 };
2428 structseeprom_cmdseeprom_read = {3, {1, 1, 0}};
2429
2430 #defineCLOCK_PULSE(p) \
2431 while ((inb(SEECTL(base)) & SEERDY) == 0) \
2432 { \
2433 ; /* Do nothing */ \
2434 }2435
2436 /*2437 * Request access of the memory port. When access is2438 * granted, SEERDY will go high. We use a 1 second2439 * timeout which should be near 1 second more than2440 * is needed. Reason: after the 7870 chip reset, there2441 * should be no contention.2442 */2443 outb(SEEMS, SEECTL(base));
2444 timeout = jiffies + 100; /* 1 second timeout */2445 while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
2446 {2447 ; /* Do nothing! Wait for access to be granted. */2448 }2449 if ((inb(SEECTL(base)) & SEERDY) == 0)
2450 {2451 outb(0, SEECTL(base));
2452 return (0);
2453 }2454
2455 /*2456 * Read the first 32 registers of the seeprom. For the 7870,2457 * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers2458 * but only the first 32 are used by Adaptec BIOS. The loop2459 * will range from 0 to 31.2460 */2461 for (k = 0; k < (sizeof(*sc) / 2); k++)
2462 {2463 /* Send chip select for one clock cycle. */2464 outb(SEEMS | SEECK | SEECS, SEECTL(base));
2465 CLOCK_PULSE(base);
2466
2467 /*2468 * Now we're ready to send the read command followed by the2469 * address of the 16-bit register we want to read.2470 */2471 for (i = 0; i < seeprom_read.len; i++)
2472 {2473 temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
2474 outb(temp, SEECTL(base));
2475 CLOCK_PULSE(base);
2476 temp = temp ^ SEECK;
2477 outb(temp, SEECTL(base));
2478 CLOCK_PULSE(base);
2479 }2480 /* Send the 6 bit address (MSB first, LSB last). */2481 for (i = 5; i >= 0; i--)
2482 {2483 temp = k;
2484 temp = (temp >> i) & 1; /* Mask out all but lower bit. */2485 temp = SEEMS | SEECS | (temp << 1);
2486 outb(temp, SEECTL(base));
2487 CLOCK_PULSE(base);
2488 temp = temp ^ SEECK;
2489 outb(temp, SEECTL(base));
2490 CLOCK_PULSE(base);
2491 }2492
2493 /*2494 * Now read the 16 bit register. An initial 0 precedes the2495 * register contents which begins with bit 15 (MSB) and ends2496 * with bit 0 (LSB). The initial 0 will be shifted off the2497 * top of our word as we let the loop run from 0 to 16.2498 */2499 for (i = 0; i <= 16; i++)
2500 {2501 temp = SEEMS | SEECS;
2502 outb(temp, SEECTL(base));
2503 CLOCK_PULSE(base);
2504 temp = temp ^ SEECK;
2505 seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
2506 outb(temp, SEECTL(base));
2507 CLOCK_PULSE(base);
2508 }2509
2510 /*2511 * The serial EEPROM has a checksum in the last word. Keep a2512 * running checksum for all words read except for the last2513 * word. We'll verify the checksum after all words have been2514 * read.2515 */2516 if (k < (sizeof(*sc) / 2) - 1)
2517 {2518 checksum = checksum + seeprom[k];
2519 }2520
2521 /* Reset the chip select for the next command cycle. */2522 outb(SEEMS, SEECTL(base));
2523 CLOCK_PULSE(base);
2524 outb(SEEMS | SEECK, SEECTL(base));
2525 CLOCK_PULSE(base);
2526 outb(SEEMS, SEECTL(base));
2527 CLOCK_PULSE(base);
2528 }2529
2530 if (checksum != sc->checksum)
2531 {2532 printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
2533 return (0);
2534 }2535
2536 #if 0
2537 printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
2538 printk("Serial EEPROM:");
2539 for (k = 0; k < (sizeof(*sc) / 2); k++)
2540 {2541 if (((k % 8) == 0) && (k != 0))
2542 {2543 printk("\n ");
2544 }2545 printk(" 0x%x", seeprom[k]);
2546 }2547 printk("\n");
2548 #endif2549
2550 /* Release access to the memory port and the serial EEPROM. */2551 outb(0, SEECTL(base));
2552 return (1);
2553 }2554
2555 /*+F*************************************************************************2556 * Function:2557 * detect_maxscb2558 *2559 * Description:2560 * Return the maximum number of SCB's allowed for a given controller.2561 *-F*************************************************************************/2562 staticint2563 detect_maxscb(aha_typetype, intbase)
/* */2564 {2565 unsignedcharsblkctl_reg;
2566 intmaxscb = 0;
2567
2568 switch (type)
2569 {2570 caseAIC_274x:
2571 caseAIC_284x:
2572 /*2573 * Check for Rev C or E boards. Rev E boards can supposedly have2574 * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.2575 * Until we know how to access more than 4 SCBs for the Rev E chips,2576 * we limit them, along with the Rev C chips, to 4 SCBs.2577 *2578 * The Rev E boards have a read/write autoflush bit in the2579 * SBLKCTL registor, while in the Rev C boards it is read only.2580 */2581 sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
2582 outb(sblkctl_reg, SBLKCTL(base));
2583 if (inb(SBLKCTL(base)) == sblkctl_reg)
2584 {/* We detected a Rev E board. */2585 printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
2586 outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
2587 maxscb = 4;
2588 }2589 else2590 {2591 printk("aic7770: Rev C and previous; using 4 SCB's\n");
2592 maxscb = 4;
2593 }2594 break;
2595
2596 caseAIC_7850:
2597 maxscb = 3;
2598 break;
2599
2600 caseAIC_7870:
2601 maxscb = 16;
2602 break;
2603
2604 caseAIC_7872:
2605 /*2606 * Really has 255, but we'll wait to verify that we access2607 * them the same way and do not have to set the card to2608 * use the memory port to access external SCB RAM.2609 */2610 maxscb = 16;
2611 break;
2612
2613 caseAIC_NONE:
2614 /*2615 * This should never happen... But just in case.2616 */2617 break;
2618 }2619
2620 return (maxscb);
2621 }2622
2623 /*+F*************************************************************************2624 * Function:2625 * aic7xxx_register2626 *2627 * Description:2628 * Register a Adaptec aic7xxx chip SCSI controller with the kernel.2629 *-F*************************************************************************/2630 staticint2631 aic7xxx_register(Scsi_Host_Template *template, aha_typetype,
/* */2632 intbase, unsignedcharirq)
2633 {2634 staticconstchar * board_name[] = {"", "274x", "284x", "7870", "7850", "7872"};
2635 inti;
2636 unsignedcharsblkctl;
2637 intmax_targets;
2638 intfound = 1;
2639 unsignedchartarget_settings;
2640 unsignedcharscsi_conf, host_conf;
2641 inthave_seeprom = 0;
2642 structScsi_Host *host;
2643 structaic7xxx_host *p;
2644 structaic7xxx_host_configconfig;
2645 structseeprom_configsc;
2646
2647 config.type = type;
2648 config.base = base;
2649 config.irq = irq;
2650 config.parity = AIC_UNKNOWN;
2651 config.low_term = AIC_UNKNOWN;
2652 config.high_term = AIC_UNKNOWN;
2653 config.busrtime = 0;
2654
2655 /*2656 * Lock out other contenders for our i/o space.2657 */2658 request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
2659
2660 switch (type)
2661 {2662 caseAIC_274x:
2663 #if 0
2664 printk("aha274x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2665 #endif2666 /*2667 * For some 274x boards, we must clear the CHIPRST bit2668 * and pause the sequencer. For some reason, this makes2669 * the driver work. For 284x boards, we give it a2670 * CHIPRST just like the 294x boards.2671 *2672 * Use the BIOS settings to determine the interrupt2673 * trigger type (level or edge) and use this value2674 * for pausing and unpausing the sequencer.2675 */2676 config.unpause = (inb(HCNTRL(config.base)) & IRQMS) | INTEN;
2677 config.pause = config.unpause | PAUSE;
2678 config.extended = aic7xxx_extended;
2679
2680 /*2681 * I don't think we need to kick the reset again, the initial probe2682 * does a reset, it seems that this is kicking a dead horse here.2683 * So... I will try to just verify that the chip has come out of the2684 * reset state and continue the same as the 284x.2685 * In the Calgary version of the driver:2686 * 1) Chip Reset2687 * 2) Set unpause to IRQMS | INTEN2688 * 3) If an interrupt occured without any commands queued, the2689 * unpause was set to just INTEN2690 * I changed the initial reset code to just mask in the CHIPRST bit2691 * and try to leave the other settings alone.2692 *2693 * I don't think we need the warning about chip reset not being clear.2694 * On both my test machines (2842 & 2940), they work just fine with a2695 * HCNTRL() of 0x5 (PAUSE | CHIPRST). Notice though, the 274x also2696 * adds the INTEN flag, where neither the 284x or 294x do.2697 */2698 outb(config.pause | CHIPRST, HCNTRL(config.base));
2699 aic7xxx_delay(1);
2700 if (inb(HCNTRL(config.base)) & CHIPRST)
2701 {2702 printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
2703 }2704 outb(config.pause, HCNTRL(config.base));
2705
2706 /*2707 * Just to be on the safe side with the 274x, we will re-read the irq2708 * since there was some issue about reseting the board.2709 */2710 config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2711 host_conf = inb(HA_HOSTCONF(config.base));
2712 config.busrtime = host_conf & 0x3C;
2713 /* XXX Is this valid for motherboard based controllers? */2714 /* Setup the FIFO threshold and the bus off time */2715 outb(host_conf & DFTHRSH, BUSSPD(config.base));
2716 outb((host_conf << 2) & BOFF, BUSTIME(config.base));
2717
2718 /*2719 * A reminder until this can be detected automatically.2720 */2721 printk("aha274x: extended translation %sabled\n",
2722 config.extended ? "en" : "dis");
2723 break;
2724
2725 caseAIC_284x:
2726 #if 0
2727 printk("aha284x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2728 #endif2729 outb(CHIPRST, HCNTRL(config.base));
2730 config.unpause = UNPAUSE_284X;
2731 config.pause = REQ_PAUSE; /* DWG would like to be like the rest */2732 config.extended = aic7xxx_extended;
2733 config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2734 host_conf = inb(HA_HOSTCONF(config.base));
2735 config.busrtime = host_conf & 0x3C;
2736 /* XXX Is this valid for motherboard based controllers? */2737 /* Setup the FIFO threshold and the bus off time */2738 outb(host_conf & DFTHRSH, BUSSPD(config.base));
2739 outb((host_conf << 2) & BOFF, BUSTIME(config.base));
2740
2741 /*2742 * A reminder until this can be detected automatically.2743 */2744 printk("aha284x: extended translation %sabled\n",
2745 config.extended ? "en" : "dis");
2746 break;
2747
2748 caseAIC_7850:
2749 caseAIC_7870:
2750 caseAIC_7872:
2751 #if 0
2752 printk("aic%s hcntrl=0x%x\n", board_name[type], inb(HCNTRL(config.base)));
2753 #endif2754
2755 outb(CHIPRST, HCNTRL(config.base));
2756 config.unpause = UNPAUSE_294X;
2757 config.pause = config.unpause | PAUSE;
2758 config.extended = aic7xxx_extended;
2759 config.scsi_id = 7;
2760
2761 printk("aic78xx: Reading SEEPROM... ");
2762 have_seeprom = read_seeprom(base, &sc);
2763 if (!have_seeprom)
2764 {2765 printk("aic78xx: unable to read SEEPROM\n");
2766 }2767 else2768 {2769 printk("done\n");
2770 config.extended = (sc.bios_control & CFEXTEND) >> 7;
2771 config.scsi_id = (sc.brtime_id & CFSCSIID);
2772 config.parity = (sc.adapter_control & CFSPARITY) ?
2773 AIC_ENABLED : AIC_DISABLED;
2774 config.low_term = (sc.adapter_control & CFSTERM) ?
2775 AIC_ENABLED : AIC_DISABLED;
2776 config.high_term = (sc.adapter_control & CFWSTERM) ?
2777 AIC_ENABLED : AIC_DISABLED;
2778 config.busrtime = (sc.brtime_id & CFBRTIME) >> 8;
2779 }2780
2781 /*2782 * XXX - force data fifo threshold to 100%. Why does this2783 * need to be done?2784 */2785 outb(inb(DSPCISTATUS(config.base)) | DFTHRESH, DSPCISTATUS(config.base));
2786 outb(config.scsi_id | DFTHRESH, HA_SCSICONF(config.base));
2787
2788 /*2789 * In case we are a wide card, place scsi ID in second conf byte.2790 */2791 outb(config.scsi_id, (HA_SCSICONF(config.base) + 1));
2792
2793 /*2794 * A reminder until this can be detected automatically.2795 */2796 printk("aic%s: extended translation %sabled\n", board_name[type],
2797 config.extended ? "en" : "dis");
2798 break;
2799
2800 default:
2801 panic("aic7xxx_register: internal error\n");
2802 }2803
2804 config.maxscb = detect_maxscb(type, base);
2805
2806 if ((config.type == AIC_274x) || (config.type == AIC_284x))
2807 {2808 if (config.pause & IRQMS)
2809 {2810 printk("aic7xxx: Using Level Sensitive Interrupts\n");
2811 }2812 else2813 {2814 printk("aic7xxx: Using Edge Triggered Interrupts\n");
2815 }2816 }2817
2818 /*2819 * Read the bus type from the SBLKCTL register. Set the FLAGS2820 * register in the sequencer for twin and wide bus cards.2821 */2822 sblkctl = inb(SBLKCTL(base)) & 0x0F; /* mask out upper two bits */2823 switch (sblkctl)
2824 {2825 case 0: /* narrow/normal bus */2826 config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2827 config.bus_type = AIC_SINGLE;
2828 outb(0, HA_FLAGS(base));
2829 break;
2830
2831 case 2: /* Wide bus */2832 config.scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
2833 config.bus_type = AIC_WIDE;
2834 printk("aic7xxx: Enabling wide channel of %s-Wide\n",
2835 board_name[config.type]);
2836 outb(WIDE_BUS, HA_FLAGS(base));
2837 break;
2838
2839 case 8: /* Twin bus */2840 config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2841 #ifdefAIC7XXX_TWIN_SUPPORT2842 config.scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
2843 config.bus_type = AIC_TWIN;
2844 printk("aic7xxx: Enabled channel B of %s-Twin\n",
2845 board_name[config.type]);
2846 outb(TWIN_BUS, HA_FLAGS(base));
2847 #else2848 config.bus_type = AIC_SINGLE;
2849 printk("aic7xxx: Channel B of %s-Twin will be ignored\n",
2850 board_name[config.type]);
2851 outb(0, HA_FLAGS(base));
2852 #endif2853 break;
2854
2855 default:
2856 printk("aic7xxx is an unsupported type 0x%x, please "
2857 "mail deang@ims.com\n", inb(SBLKCTL(base)));
2858 outb(0, HA_FLAGS(base));
2859 return (0);
2860 }2861
2862 /*2863 * Clear the upper two bits. For the 294x cards, clearing the2864 * upper two bits, will take the card out of diagnostic mode2865 * and make the host adatper LED follow bus activity (will not2866 * always be on).2867 */2868 outb(sblkctl, SBLKCTL(base));
2869
2870 /*2871 * The IRQ level in i/o port 4 maps directly onto the real2872 * IRQ number. If it's ok, register it with the kernel.2873 *2874 * NB. the Adaptec documentation says the IRQ number is only2875 * in the lower four bits; the ECU information shows the2876 * high bit being used as well. Which is correct?2877 *2878 * The 294x cards (PCI) get their interrupt from PCI BIOS.2879 */2880 if (((config.type == AIC_274x) || (config.type == AIC_284x))
2881 && (config.irq < 9 || config.irq > 15))
2882 {2883 printk("aic7xxx uses unsupported IRQ level, ignoring\n");
2884 return (0);
2885 }2886
2887 /*2888 * Check the IRQ to see if it is shared by another aic7xxx2889 * controller. If it is and sharing of IRQs is not defined,2890 * then return 0 hosts found. If sharing of IRQs is allowed2891 * or the IRQ is not shared by another host adapter, then2892 * proceed.2893 */2894 #ifndefAIC7XXX_SHARE_IRQS2895 if (aic7xxx_boards[config.irq] != NULL)
2896 {2897 printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
2898 return (0);
2899 }2900 #endif2901
2902 /*2903 * Print out debugging information before re-enabling2904 * the card - a lot of registers on it can't be read2905 * when the sequencer is active.2906 */2907 debug_config(&config);
2908
2909 /*2910 * Before registry, make sure that the offsets of the2911 * struct scatterlist are what the sequencer will expect,2912 * otherwise disable scatter-gather altogether until someone2913 * can fix it. This is important since the sequencer will2914 * DMA elements of the SG array in while executing commands.2915 */2916 if (template->sg_tablesize != SG_NONE)
2917 {2918 structscatterlistsg;
2919
2920 if (SG_STRUCT_CHECK(sg))
2921 {2922 printk("aic7xxx warning: kernel scatter-gather "
2923 "structures changed, disabling it\n");
2924 template->sg_tablesize = SG_NONE;
2925 }2926 }2927
2928 /*2929 * Register each "host" and fill in the returned Scsi_Host2930 * structure as best we can. Some of the parameters aren't2931 * really relevant for bus types beyond ISA, and none of the2932 * high-level SCSI code looks at it anyway. Why are the fields2933 * there? Also save the pointer so that we can find the2934 * information when an IRQ is triggered.2935 */2936 host = scsi_register(template, sizeof(structaic7xxx_host));
2937 host->can_queue = config.maxscb;
2938 #ifdefAIC7XXX_TAGGED_QUEUEING2939 host->cmd_per_lun = 2;
2940 #else2941 host->cmd_per_lun = 1;
2942 #endif2943 host->this_id = config.scsi_id;
2944 host->irq = config.irq;
2945 if (config.bus_type == AIC_WIDE)
2946 {2947 host->max_id = 16;
2948 }2949 if (config.bus_type == AIC_TWIN)
2950 {2951 host->max_channel = 1;
2952 }2953
2954 p = (structaic7xxx_host *) host->hostdata;
2955
2956 /* Initialize the scb array by setting the state to free. */2957 for (i = 0; i < AIC7XXX_MAXSCB; i++)
2958 {2959 p->scb_array[i].state = SCB_FREE;
2960 p->scb_array[i].next = NULL;
2961 p->scb_array[i].cmd = NULL;
2962 }2963
2964 p->isr_count = 0;
2965 p->a_scanned = 0;
2966 p->b_scanned = 0;
2967 p->base = config.base;
2968 p->maxscb = config.maxscb;
2969 p->numscb = 0;
2970 p->extended = config.extended;
2971 p->type = config.type;
2972 p->bus_type = config.bus_type;
2973 p->have_seeprom = have_seeprom;
2974 p->seeprom = sc;
2975 p->free_scb = NULL;
2976 p->next = NULL;
2977
2978 p->unpause = config.unpause;
2979 p->pause = config.pause;
2980
2981 if (aic7xxx_boards[config.irq] == NULL)
2982 {2983 /*2984 * Warning! This must be done before requesting the irq. It is2985 * possible for some boards to raise an interrupt as soon as2986 * they are enabled. So when we request the irq from the Linux2987 * kernel, an interrupt is triggered immediately. Therefore, we2988 * must ensure the board data is correctly set before the request.2989 */2990 aic7xxx_boards[config.irq] = host;
2991
2992 /*2993 * Register IRQ with the kernel.2994 */2995 if (request_irq(config.irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
2996 {2997 printk("aic7xxx couldn't register irq %d, ignoring\n", config.irq);
2998 aic7xxx_boards[config.irq] = NULL;
2999 return (0);
3000 }3001 }3002 else3003 {3004 /*3005 * We have found a host adapter sharing an IRQ of a previously3006 * registered host adapter. Add this host adapter's Scsi_Host3007 * to the beginning of the linked list of hosts at the same IRQ.3008 */3009 p->next = aic7xxx_boards[config.irq];
3010 aic7xxx_boards[config.irq] = host;
3011 }3012
3013 /*3014 * Load the sequencer program, then re-enable the board -3015 * resetting the AIC-7770 disables it, leaving the lights3016 * on with nobody home. On the PCI bus you *may* be home,3017 * but then your mailing address is dynamically assigned3018 * so no one can find you anyway :-)3019 */3020 printk("aic7xxx: Downloading sequencer code..");
3021 aic7xxx_loadseq(base);
3022
3023 /* Set Fast Mode and Enable the board */3024 outb(FASTMODE, SEQCTL(base));
3025
3026 if ((p->type == AIC_274x || p->type == AIC_284x))
3027 {3028 outb(ENABLE, BCTL(base));
3029 }3030
3031 printk("done.\n");
3032
3033 /*3034 * Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels3035 */3036 if (p->bus_type == AIC_TWIN)
3037 {3038 /*3039 * The device is gated to channel B after a chip reset,3040 * so set those values first.3041 */3042 outb(config.scsi_id_b, SCSIID(base));
3043 scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
3044 scsi_conf = scsi_conf | ENSTIMER | ACTNEGEN | STPWEN;
3045 outb(scsi_conf, SXFRCTL1(base));
3046 outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3047 /* Select Channel A */3048 outb(0, SBLKCTL(base));
3049 }3050 outb(config.scsi_id, SCSIID(base));
3051 scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
3052 outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3053 outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3054
3055 /* Look at the information that board initialization or the board3056 * BIOS has left us. In the lower four bits of each target's3057 * scratch space any value other than 0 indicates that we should3058 * initiate synchronous transfers. If it's zero, the user or the3059 * BIOS has decided to disable synchronous negotiation to that3060 * target so we don't activate the needsdtr flag.3061 */3062 p->needsdtr_copy = 0;
3063 p->sdtr_pending = 0;
3064 p->needwdtr_copy = 0;
3065 p->wdtr_pending = 0;
3066 if (p->bus_type == AIC_SINGLE)
3067 {3068 max_targets = 8;
3069 }3070 else3071 {3072 max_targets = 16;
3073 }3074
3075 for (i = 0; i < max_targets; i++)
3076 {3077 if (have_seeprom)
3078 {3079 target_settings = (sc.device_flags[i] & CFXFER) << 4;
3080 if (sc.device_flags[i] & CFSYNCH)
3081 {3082 p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
3083 }3084 if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
3085 {3086 p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3087 }3088 }3089 else3090 {3091 target_settings = inb(HA_TARG_SCRATCH(base) + i);
3092 if (target_settings & 0x0F)
3093 {3094 p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
3095 /*3096 * Default to asynchronous transfers (0 offset)3097 */3098 target_settings = target_settings & 0xF0;
3099 }3100 /*3101 * If we are not wide, forget WDTR. This makes the driver3102 * work on some cards that don't leave these fields cleared3103 * when BIOS is not installed.3104 */3105 if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
3106 {3107 p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3108 target_settings = target_settings & 0x7F;
3109 }3110 }3111 outb(target_settings, (HA_TARG_SCRATCH(base) + i));
3112 }3113
3114 p->needsdtr = p->needsdtr_copy;
3115 p->needwdtr = p->needwdtr_copy;
3116 #if 0
3117 printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
3118 printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
3119 #endif 0
3120
3121 /*3122 * Clear the control byte for every SCB so that the sequencer3123 * doesn't get confused and think that one of them is valid3124 */3125 for (i = 0; i < config.maxscb; i++)
3126 {3127 outb(i, SCBPTR(base));
3128 outb(0, SCBARRAY(base));
3129 }3130
3131 /*3132 * For reconnecting targets, the sequencer code needs to3133 * know how many SCBs it has to search through.3134 */3135 outb(config.maxscb, HA_SCBCOUNT(base));
3136
3137 /*3138 * Clear the active flags - no targets are busy.3139 */3140 outb(0, HA_ACTIVE0(base));
3141 outb(0, HA_ACTIVE1(base));
3142
3143 /* We don't have any waiting selections */3144 outb (SCB_LIST_NULL, WAITING_SCBH(base));
3145 outb (SCB_LIST_NULL, WAITING_SCBT(base));
3146
3147 /*3148 * Reset the SCSI bus. Is this necessary?3149 * There may be problems for a warm boot without resetting3150 * the SCSI bus. Either BIOS settings in scratch RAM3151 * will not get reinitialized, or devices may stay at3152 * previous negotiated settings (SDTR and WDTR) while3153 * the driver will think that no negotiations have been3154 * performed.3155 *3156 * Some devices need a long time to "settle" after a SCSI3157 * bus reset.3158 */3159
3160 if (!aic7xxx_no_reset)
3161 {3162 printk("Resetting the SCSI bus...\n");
3163 if (p->bus_type == AIC_TWIN)
3164 {3165 /*3166 * Select channel B.3167 */3168 outb(2, SBLKCTL(base));
3169 outb(SCSIRSTO, SCSISEQ(base));
3170 udelay(1000);
3171 outb(0, SCSISEQ(base));
3172 /*3173 * Select channel A.3174 */3175 outb(0, SBLKCTL(base));
3176 }3177
3178 outb(SCSIRSTO, SCSISEQ(base));
3179 udelay(1000);
3180 outb(0, SCSISEQ(base));
3181 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3182 }3183
3184 /*3185 * Unpause the sequencer before returning and enable3186 * interrupts - we shouldn't get any until the first3187 * command is sent to us by the high-level SCSI code.3188 */3189 UNPAUSE_SEQUENCER(p);
3190 return (found);
3191 }3192
3193 /*+F*************************************************************************3194 * Function:3195 * aic7xxx_detect3196 *3197 * Description:3198 * Try to detect and register an Adaptec 7770 or 7870 SCSI controller.3199 *-F*************************************************************************/3200 int3201 aic7xxx_detect(Scsi_Host_Template *template)
/* */3202 {3203 aha_typetype = AIC_NONE;
3204 intfound = 0, slot, base;
3205 unsignedcharirq = 0;
3206 inti;
3207
3208 /*3209 * Since we may allow sharing of IRQs, it is imperative3210 * that we "null-out" the aic7xxx_boards array. It is3211 * not guaranteed to be initialized to 0 (NULL). We use3212 * a NULL entry to indicate that no prior hosts have3213 * been found/registered for that IRQ.3214 */3215 for (i = 0; i <= MAXIRQ; i++)
3216 {3217 aic7xxx_boards[i] = NULL;
3218 }3219
3220 /*3221 * Initialize the spurious count to 0.3222 */3223 aic7xxx_spurious_count = 0;
3224
3225 /*3226 * EISA/VL-bus card signature probe.3227 */3228 for (slot = MINSLOT; slot <= MAXSLOT; slot++)
3229 {3230 base = SLOTBASE(slot);
3231
3232 if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
3233 {3234 /*3235 * Some other driver has staked a3236 * claim to this i/o region already.3237 */3238 continue;
3239 }3240
3241 type = aic7xxx_probe(slot, HID0(base));
3242 if (type != AIC_NONE)
3243 {3244 /*3245 * We found a card, allow 1 spurious interrupt.3246 */3247 aic7xxx_spurious_count = 1;
3248
3249 #if 0
3250 printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3251 outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3252 irq = inb(HA_INTDEF(base)) & 0x0F;
3253 #endif3254
3255 /*3256 * We "find" a AIC-7770 if we locate the card3257 * signature and we can set it up and register3258 * it with the kernel without incident.3259 */3260 found += aic7xxx_register(template, type, base, irq);
3261
3262 /*3263 * Disallow spurious interrupts.3264 */3265 aic7xxx_spurious_count = 0;
3266 }3267 }3268
3269 #ifdefCONFIG_PCI3270
3271 #defineDEVREVID 0x08
3272 #defineDEVCONFIG 0x40
3273 #defineDEVSTATUS 0x41
3274 #defineRAMPSM 0x02
3275
3276 /*3277 * PCI-bus probe.3278 */3279 if (pcibios_present())
3280 {3281 interror;
3282 intdone = 0;
3283 unsignedintio_port;
3284 unsignedshortindex = 0;
3285 unsignedcharpci_bus, pci_device_fn;
3286 unsignedchardevrevid, devconfig, devstatus;
3287 charrev_id[] = {'B', 'C', 'D'};
3288
3289 while (!done)
3290 {3291 if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3292 PCI_DEVICE_ID_ADAPTEC_294x,
3293 index, &pci_bus, &pci_device_fn)) ||
3294 (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3295 PCI_DEVICE_ID_ADAPTEC_2940,
3296 index, &pci_bus, &pci_device_fn)))
3297 {3298 type = AIC_7870;
3299 }3300 else3301 {3302 if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3303 PCI_DEVICE_ID_ADAPTEC_7850,
3304 index, &pci_bus, &pci_device_fn))
3305 {3306 type = AIC_7850;
3307 }3308 else3309 {3310 if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3311 PCI_DEVICE_ID_ADAPTEC_7872,
3312 index, &pci_bus, &pci_device_fn))
3313 {3314 type = AIC_7872;
3315 }3316 else3317 {3318 type = AIC_NONE;
3319 done = 1;
3320 }3321 }3322 }3323
3324 if (!done)
3325 {3326 /*3327 * Read esundry information from PCI BIOS.3328 */3329 error = pcibios_read_config_dword(pci_bus, pci_device_fn,
3330 PCI_BASE_ADDRESS_0, &io_port);
3331
3332 if (error)
3333 {3334 panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
3335 }3336
3337 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3338 PCI_INTERRUPT_LINE, &irq);
3339 if (error)
3340 {3341 panic("aic7xxx_detect: error %d reading irq.\n", error);
3342 }3343
3344 /*3345 * Make the base I/O register look like EISA and VL-bus.3346 */3347 base = io_port - 0xC01;
3348
3349 /*3350 * I don't think we need to bother with allowing3351 * spurious interrupts for the 787x/7850, but what3352 * the hey.3353 */3354 aic7xxx_spurious_count = 1;
3355
3356 #if 0
3357 printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3358 #endif3359 outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3360
3361 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3362 DEVREVID, &devrevid);
3363 if (devrevid < 3)
3364 {3365 printk("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
3366 }3367 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3368 DEVCONFIG, &devconfig);
3369 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3370 DEVSTATUS, &devstatus);
3371 printk("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
3372 devconfig, devstatus);
3373 if (devstatus & RAMPSM)
3374 {3375 printk("aic7xxx_detect: detected external SCB RAM, "
3376 "mail deang@ims.com for test patch");
3377 }3378
3379 found += aic7xxx_register(template, type, base, irq);
3380
3381 /*3382 * Disable spurious interrupts.3383 */3384 aic7xxx_spurious_count = 0;
3385
3386 index += 1;
3387 }3388 }3389 }3390 #endifCONFIG_PCI3391
3392 template->name = aic7xxx_info(NULL);
3393 return (found);
3394 }3395
3396
3397 /*+F*************************************************************************3398 * Function:3399 * aic7xxx_buildscb3400 *3401 * Description:3402 * Build a SCB.3403 *-F*************************************************************************/3404 staticvoid3405 aic7xxx_buildscb(structaic7xxx_host *p,
/* */3406 Scsi_Cmnd *cmd,
3407 structaic7xxx_scb *scb)
3408 {3409 void *addr;
3410 unsignedlength;
3411 unsignedshortmask;
3412
3413 /*3414 * Setup the control byte if we need negotiation and have not3415 * already requested it.3416 */3417 #ifdefAIC7XXX_TAGGED_QUEUEING3418 if (cmd->device->tagged_supported)
3419 {3420 if (cmd->device->tagged_queue == 0)
3421 {3422 printk("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
3423 "channel %d\n", cmd->target, cmd->channel);
3424 cmd->device->tagged_queue = 1;
3425 cmd->device->current_tag = 1; /* enable tagging */3426 }3427 cmd->tag = cmd->device->current_tag;
3428 cmd->device->current_tag = cmd->device->current_tag + 1;
3429 scb->control = scb->control | SCB_TE;
3430 }3431 #endif3432 mask = (0x01 << cmd->target);
3433 if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
3434 {3435 p->wdtr_pending = p->wdtr_pending | mask;
3436 scb->control = scb->control | SCB_NEEDWDTR;
3437 #if 0
3438 printk("Sending WDTR request to target %d.\n", cmd->target);
3439 #endif3440 }3441 else3442 {3443 if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
3444 {3445 p->sdtr_pending = p->sdtr_pending | mask;
3446 scb->control = scb->control | SCB_NEEDSDTR;
3447 #if 0
3448 printk("Sending SDTR request to target %d.\n", cmd->target);
3449 #endif3450 }3451 }3452
3453 #if 0
3454 printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
3455 cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
3456 #endif3457 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
3458 ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
3459
3460 /*3461 * The interpretation of request_buffer and request_bufflen3462 * changes depending on whether or not use_sg is zero; a3463 * non-zero use_sg indicates the number of elements in the3464 * scatter-gather array.3465 *3466 * The AIC-7770 can't support transfers of any sort larger3467 * than 2^24 (three-byte count) without backflips. For what3468 * the kernel is doing, this shouldn't occur. I hope.3469 */3470 length = aic7xxx_length(cmd, 0);
3471
3472 if (length > 0xFFFFFF)
3473 {3474 panic("aic7xxx_buildscb: can't transfer > 2^24 - 1 bytes\n");
3475 }3476
3477 /*3478 * XXX - this relies on the host data being stored in a3479 * little-endian format.3480 */3481 addr = cmd->cmnd;
3482 scb->SCSI_cmd_length = cmd->cmd_len;
3483 memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
3484
3485 if (cmd->use_sg)
3486 {3487 #if 0
3488 debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
3489 cmd->use_sg, length);
3490 #endif3491 scb->SG_segment_count = cmd->use_sg;
3492 memcpy(scb->SG_list_pointer, &cmd->request_buffer,
3493 sizeof(scb->SG_list_pointer));
3494 }3495 else3496 {3497 #if 0
3498 debug("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
3499 (unsignedlong) cmd->request_buffer, cmd->request_bufflen);
3500 #endif3501 #ifdefAIC7XXX_USE_SG3502 scb->SG_segment_count = 1;
3503 scb->sg.address = (char *) cmd->request_buffer;
3504 scb->sg.length = cmd->request_bufflen;
3505 addr = &scb->sg;
3506 memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
3507 #else3508 scb->SG_segment_count = 0;
3509 memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
3510 memcpy(scb->data_count, &cmd->request_bufflen, 3);
3511 #endif3512 }3513 }3514
3515 /*+F*************************************************************************3516 * Function:3517 * aic7xxx_queue3518 *3519 * Description:3520 * Queue a SCB to the controller.3521 *-F*************************************************************************/3522 int3523 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
/* */3524 {3525 longflags;
3526 #ifndefAIC7XXX_USE_DMA3527 intold_scbptr;
3528 #endif3529 structaic7xxx_host *p;
3530 structaic7xxx_scb *scb;
3531 unsignedcharcurscb;
3532
3533 p = (structaic7xxx_host *) cmd->host->hostdata;
3534
3535 /* Check to see if channel was scanned. */3536 if (!p->a_scanned && (cmd->channel == 0))
3537 {3538 printk("aic7xxx: Scanning channel A for devices.\n");
3539 p->a_scanned = 1;
3540 }3541 else3542 {3543 if (!p->b_scanned && (cmd->channel == 1))
3544 {3545 printk("aic7xxx: Scanning channel B for devices.\n");
3546 p->b_scanned = 1;
3547 }3548 }3549
3550 #if 0
3551 debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
3552 cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
3553 cmd->lun & 0x07);
3554 #endif3555
3556 /*3557 * This is a critical section, since we don't want the3558 * interrupt routine mucking with the host data or the3559 * card. Since the kernel documentation is vague on3560 * whether or not we are in a cli/sti pair already, save3561 * the flags to be on the safe side.3562 */3563 save_flags(flags);
3564 cli();
3565
3566 /*3567 * Find a free slot in the SCB array to load this command3568 * into. Since can_queue is set to the maximum number of3569 * SCBs for the card, we should always find one.3570 *3571 * First try to find an scb in the free list. If there are3572 * none in the free list, then check the current number of3573 * of scbs and take an unused one from the scb array.3574 */3575 scb = p->free_scb;
3576 if (scb != NULL)
3577 {/* found one in the free list */3578 p->free_scb = scb->next; /* remove and update head of list */3579 /*3580 * Warning! For some unknown reason, the scb at the head3581 * of the free list is not the same address that it should3582 * be. That's why we set the scb pointer taken by the3583 * position in the array. The scb at the head of the list3584 * should match this address, but it doesn't.3585 */3586 scb = &(p->scb_array[scb->position]);
3587 scb->control = 0;
3588 scb->state = SCB_ACTIVE;
3589 }3590 else3591 {3592 if (p->numscb >= p->maxscb)
3593 {3594 panic("aic7xxx_queue: couldn't find a free scb\n");
3595 }3596 else3597 {3598 /*3599 * Initialize the scb within the scb array. The3600 * position within the array is the position on3601 * the board that it will be loaded.3602 */3603 scb = &(p->scb_array[p->numscb]);
3604 memset(scb, 0, sizeof(*scb));
3605
3606 scb->position = p->numscb;
3607 p->numscb++;
3608 scb->state = SCB_ACTIVE;
3609 scb->next_waiting = SCB_LIST_NULL;
3610 memcpy(scb->host_scb, &scb, sizeof(scb));
3611 #ifdefAIC7XXX_USE_DMA3612 scb->control = SCB_NEEDDMA;
3613 #endif3614 PAUSE_SEQUENCER(p);
3615 curscb = inb(SCBPTR(p->base));
3616 outb(scb->position, SCBPTR(p->base));
3617 aic7xxx_putdmascb(p->base, scb);
3618 outb(curscb, SCBPTR(p->base));
3619 UNPAUSE_SEQUENCER(p);
3620 scb->control = 0;
3621 }3622 }3623
3624 scb->cmd = cmd;
3625 aic7xxx_position(cmd) = scb->position;
3626
3627 /*3628 * Construct the SCB beforehand, so the sequencer is3629 * paused a minimal amount of time.3630 */3631 aic7xxx_buildscb(p, cmd, scb);
3632
3633 #if 0
3634 if (scb != &p->scb_array[scb->position])
3635 {3636 printk("aic7xxx_queue: address of scb by position does not match scb address\n");
3637 }3638 printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
3639 scb->position, (unsignedint) scb->cmd,
3640 scb->state, (unsignedint) p->free_scb);
3641 #endif3642 /*3643 * Pause the sequencer so we can play with its registers -3644 * wait for it to acknowledge the pause.3645 *3646 * XXX - should the interrupts be left on while doing this?3647 */3648 PAUSE_SEQUENCER(p);
3649
3650 /*3651 * Save the SCB pointer and put our own pointer in - this3652 * selects one of the four banks of SCB registers. Load3653 * the SCB, then write its pointer into the queue in FIFO3654 * and restore the saved SCB pointer.3655 */3656 #ifdefAIC7XXX_USE_DMA3657 aic7xxx_putscb(p->base, scb);
3658 #else3659 old_scbptr = inb(SCBPTR(p->base));
3660 outb(scb->position, SCBPTR(p->base));
3661
3662 aic7xxx_putscb(p->base, scb);
3663
3664 outb(scb->position, QINFIFO(p->base));
3665 outb(old_scbptr, SCBPTR(p->base));
3666 #endif3667 /*3668 * Make sure the Scsi_Cmnd pointer is saved, the struct it3669 * points to is set up properly, and the parity error flag3670 * is reset, then unpause the sequencer and watch the fun3671 * begin.3672 */3673 cmd->scsi_done = fn;
3674 aic7xxx_error(cmd) = DID_OK;
3675 aic7xxx_status(cmd) = 0;
3676
3677 cmd->result = 0;
3678 memset(&cmd->sense_buffer, 0, sizeof(cmd->sense_buffer));
3679
3680 UNPAUSE_SEQUENCER(p);
3681 restore_flags(flags);
3682 return (0);
3683 }3684
3685 /* return values from aic7xxx_kill */3686 typedefenum{3687 k_ok, /* scb found and message sent */3688 k_busy, /* message already present */3689 k_absent, /* couldn't locate scb */3690 k_disconnect, /* scb found, but disconnected */3691 }k_state;
3692
3693 /*+F*************************************************************************3694 * Function:3695 * aic7xxx_kill3696 *3697 * Description:3698 * This must be called with interrupts disabled - it's going to3699 * be messing around with the host data, and an interrupt being3700 * fielded in the middle could get ugly.3701 *3702 * Since so much of the abort and reset code is shared, this3703 * function performs more magic than it really should. If the3704 * command completes ok, then it will call scsi_done with the3705 * result code passed in. The unpause parameter controls whether3706 * or not the sequencer gets unpaused - the reset function, for3707 * instance, may want to do something more aggressive.3708 *3709 * Note that the command is checked for in our SCB_array first3710 * before the sequencer is paused, so if k_absent is returned,3711 * then the sequencer is NOT paused.3712 *-F*************************************************************************/3713 statick_state3714 aic7xxx_kill(Scsi_Cmnd *cmd, unsignedcharmessage,
/* */3715 unsignedintresult, intunpause)
3716 {3717 structaic7xxx_host *p;
3718 structaic7xxx_scb *scb;
3719 inti, active_scb, found, queued;
3720 unsignedcharscbsave[AIC7XXX_MAXSCB];
3721 unsignedcharflags;
3722 intscb_control;
3723 k_statestatus;
3724
3725 p = (structaic7xxx_host *) cmd->host->hostdata;
3726 scb = &p->scb_array[aic7xxx_position(cmd)];
3727
3728 #if 0
3729 printk("aic7xxx_kill: In the kill function...\n");
3730 #endif3731 PAUSE_SEQUENCER(p);
3732
3733 /*3734 * Case 1: In the QINFIFO3735 *3736 * This is the best case, really. Check to see if the3737 * command is still in the sequencer's input queue. If3738 * so, simply remove it. Reload the queue afterward.3739 */3740 queued = inb(QINCNT(p->base));
3741
3742 for (i = found = 0; i < (queued - found); i++)
3743 {3744 scbsave[i] = inb(QINFIFO(p->base));
3745
3746 if (scbsave[i] == scb->position)
3747 {3748 found = 1;
3749 i--;
3750 }3751 }3752
3753 for (queued = 0; queued < i; queued++)
3754 {3755 outb(scbsave[queued], QINFIFO(p->base));
3756 }3757
3758 if (found)
3759 {3760 status = k_ok;
3761 gotocomplete;
3762 }3763
3764 active_scb = inb(SCBPTR(p->base));
3765 /*3766 * Case 2: Not the active command3767 *3768 * Check the current SCB bank. If it's not the one belonging3769 * to the command we want to kill, select the scb we want to3770 * abort and turn off the disconnected bit. The driver will3771 * then abort the command and notify us of the abort.3772 */3773 if (active_scb != scb->position)
3774 {3775 outb(scb->position, SCBPTR(p->base));
3776 scb_control = inb(SCBARRAY(p->base));
3777 scb_control = scb_control & ~SCB_DIS;
3778 outb(scb_control, SCBARRAY(p->base));
3779 outb(active_scb, SCBPTR(p->base));
3780 status = k_disconnect;
3781 gotocomplete;
3782 }3783
3784 scb_control = inb(SCBARRAY(p->base));
3785 if (scb_control & SCB_DIS)
3786 {3787 scb_control = scb_control & ~SCB_DIS;
3788 outb(scb_control, SCBARRAY(p->base));
3789 status = k_disconnect;
3790 gotocomplete;
3791 }3792
3793 /*3794 * Presumably at this point our target command is active. Check3795 * to see if there's a message already in effect. If not, place3796 * our message in and assert ATN so the target goes into MESSAGE3797 * OUT phase.3798 */3799 flags = inb(HA_FLAGS(p->base));
3800 if (flags & ACTIVE_MSG)
3801 {3802 /*3803 * If there is a message in progress, reset the bus3804 * and have all devices renegotiate.3805 */3806 if (cmd->channel & 0x01)
3807 {3808 p->needsdtr = p->needsdtr_copy & 0xFF00;
3809 p->sdtr_pending = p->sdtr_pending & 0x00FF;
3810 outb(0, HA_ACTIVE1(p->base));
3811 }3812 else3813 {3814 if (p->bus_type == AIC_WIDE)
3815 {3816 p->needsdtr = p->needsdtr_copy;
3817 p->needwdtr = p->needwdtr_copy;
3818 p->sdtr_pending = 0;
3819 p->wdtr_pending = 0;
3820 outb(0, HA_ACTIVE0(p->base));
3821 outb(0, HA_ACTIVE1(p->base));
3822 }3823 else3824 {3825 p->needsdtr = p->needsdtr_copy & 0x00FF;
3826 p->sdtr_pending = p->sdtr_pending & 0xFF00;
3827 outb(0, HA_ACTIVE0(p->base));
3828 }3829 }3830 /* Reset the bus. */3831 outb(SCSIRSTO, SCSISEQ(p->base));
3832 udelay(1000);
3833 outb(0, SCSISEQ(p->base));
3834 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3835
3836 status = k_busy;
3837 gotocomplete;
3838 }3839
3840 outb(flags | ACTIVE_MSG, HA_FLAGS(p->base)); /* active message */3841 outb(1, HA_MSG_LEN(p->base)); /* length = 1 */3842 outb(message, HA_MSG_START(p->base)); /* message body */3843
3844 /*3845 * Assert ATN. Use the value of SCSISIGO saved by the3846 * sequencer code so we don't alter its contents radically3847 * in the middle of something critical.3848 */3849 outb(inb(HA_SIGSTATE(p->base)) | 0x10, SCSISIGO(p->base));
3850
3851 status = k_ok;
3852
3853 /*3854 * The command has been killed. Do the bookkeeping, unpause3855 * the sequencer, and notify the higher-level SCSI code.3856 */3857 complete:
3858 if (unpause)
3859 {3860 UNPAUSE_SEQUENCER(p);
3861 }3862
3863 /*3864 * Mark the scb as free and clear the scbs command pointer.3865 * Add the scb to the head of the free list being careful3866 * to preserve the next pointers.3867 */3868 scb->state = SCB_FREE; /* mark the scb as free */3869 scb->cmd = NULL; /* clear the command pointer */3870 scb->next = p->free_scb; /* preserve next pointer */3871 p->free_scb = scb; /* add at head of free list */3872 cmd->result = cmd->result << 16;
3873 cmd->scsi_done(cmd);
3874 return (status);
3875 }3876
3877 /*+F*************************************************************************3878 * Function:3879 * aic7xxx_abort3880 *3881 * Description:3882 * Abort the current SCSI command(s).3883 *-F*************************************************************************/3884 int3885 aic7xxx_abort(Scsi_Cmnd *cmd)
/* */3886 {3887 intrv;
3888 longflags;
3889
3890 save_flags(flags);
3891 cli();
3892
3893 switch (aic7xxx_kill(cmd, ABORT, DID_ABORT, !0))
3894 {3895 casek_ok: rv = SCSI_ABORT_SUCCESS; break;
3896 casek_busy: rv = SCSI_ABORT_BUSY; break;
3897 casek_absent: rv = SCSI_ABORT_NOT_RUNNING; break;
3898 casek_disconnect: rv = SCSI_ABORT_SNOOZE; break;
3899 default: panic("aic7xxx_abort: internal error\n");
3900 }3901
3902 restore_flags(flags);
3903 return (rv);
3904 }3905
3906 /*+F*************************************************************************3907 * Function:3908 * aic7xxx_reset3909 *3910 * Description:3911 * Resetting the bus always succeeds - is has to, otherwise the3912 * kernel will panic! Try a surgical technique - sending a BUS3913 * DEVICE RESET message - on the offending target before pulling3914 * the SCSI bus reset line.3915 *-F*************************************************************************/3916 int3917 aic7xxx_reset(Scsi_Cmnd *cmd)
/* */3918 {3919 longflags;
3920 structaic7xxx_host *p;
3921
3922 p = (structaic7xxx_host *) cmd->host->hostdata;
3923 save_flags(flags);
3924 cli();
3925
3926 switch (aic7xxx_kill(cmd, BUS_DEVICE_RESET, DID_RESET, 0))
3927 {3928 casek_ok:
3929 /*3930 * The RESET message was sent to the target3931 * with no problems. Flag that target as3932 * needing a SDTR negotiation on the next3933 * connection and restart the sequencer.3934 */3935 p->needsdtr = p->needsdtr & (1 << cmd->target);
3936 UNPAUSE_SEQUENCER(p);
3937 break;
3938
3939 casek_absent:
3940 /*3941 * The sequencer will not be paused if aic7xxx_kill()3942 * couldn't find the command.3943 */3944 PAUSE_SEQUENCER(p);
3945 /* falls through */3946
3947 casek_busy:
3948 cmd->result = DID_RESET << 16; /* return reset code */3949 cmd->scsi_done(cmd);
3950 break;
3951
3952 casek_disconnect:
3953 /*3954 * Do a hard reset of the SCSI bus. According to the3955 * SCSI-2 draft specification, reset has to be asserted3956 * for at least 25us. I'm invoking the kernel delay3957 * function for 30us since I'm not totally trusting of3958 * the busy loop timing.3959 *3960 * XXX - I'm not convinced this works. I tried resetting3961 * the bus before, trying to get the devices on the3962 * bus to revert to asynchronous transfer, and it3963 * never seemed to work.3964 */3965 debug("aic7xxx: attempting to reset scsi bus and card\n");
3966
3967 outb(SCSIRSTO, SCSISEQ(p->base));
3968 udelay(1000);
3969 outb(0, SCSISEQ(p->base));
3970 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3971
3972 UNPAUSE_SEQUENCER(p);
3973
3974 /*3975 * Locate the command and return a "reset" status3976 * for it. This is not completely correct and will3977 * probably return to haunt me later.3978 */3979 cmd->result = DID_RESET << 16; /* return reset code */3980 cmd->scsi_done(cmd);
3981 break;
3982
3983 default:
3984 panic("aic7xxx_reset: internal error\n");
3985 }3986
3987 restore_flags(flags);
3988 return (SCSI_RESET_SUCCESS);
3989 }3990
3991 /*+F*************************************************************************3992 * Function:3993 * aic7xxx_biosparam3994 *3995 * Description:3996 * Return the disk geometry for the given SCSI device.3997 *-F*************************************************************************/3998 int3999 aic7xxx_biosparam(Disk *disk, intdevno, intgeom[])
/* */4000 {4001 intheads, sectors, cylinders;
4002 structaic7xxx_host *p;
4003
4004 p = (structaic7xxx_host *) disk->device->host->hostdata;
4005
4006 /*4007 * XXX - if I could portably find the card's configuration4008 * information, then this could be autodetected instead4009 * of left to a boot-time switch.4010 */4011 heads = 64;
4012 sectors = 32;
4013 cylinders = disk->capacity / (heads * sectors);
4014
4015 if (p->extended && cylinders > 1024)
4016 {4017 heads = 255;
4018 sectors = 63;
4019 cylinders = disk->capacity / (255 * 63);
4020 }4021
4022 geom[0] = heads;
4023 geom[1] = sectors;
4024 geom[2] = cylinders;
4025
4026 return (0);
4027 }4028
4029 #ifdefMODULE4030 /* Eventually this will go into an include file, but this will be later */4031 Scsi_Host_Templatedriver_template = AIC7XXX;
4032
4033 #include "scsi_module.c"
4034 #endif4035
4036 /*4037 * Overrides for Emacs so that we almost follow Linus's tabbing style.4038 * Emacs will notice this stuff at the end of the file and automatically4039 * adjust the settings for this buffer only. This must remain at the end4040 * of the file.4041 * ---------------------------------------------------------------------------4042 * Local variables:4043 * c-indent-level: 24044 * c-brace-imaginary-offset: 04045 * c-brace-offset: -24046 * c-argdecl-indent: 24047 * c-label-offset: -24048 * c-continued-statement-offset: 24049 * c-continued-brace-offset: 04050 * indent-tabs-mode: nil4051 * tab-width: 84052 * End:4053 */