drivers/scsi/aha152x.h

/* */
   1 #ifndef _AHA152X_H
   2 #define _AHA152X_H
   3 
   4 /*
   5  * $Id: aha152x.h,v 1.9 1995/03/18 09:21:04 root Exp root $
   6  */
   7 
   8 #if defined(__KERNEL__)
   9 
  10 #include "../block/blk.h"
  11 #include "scsi.h"
  12 #include <asm/io.h>
  13 
  14 int        aha152x_detect(Scsi_Host_Template *);
  15 int        aha152x_command(Scsi_Cmnd *);
  16 int        aha152x_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  17 int        aha152x_abort(Scsi_Cmnd *);
  18 int        aha152x_reset(Scsi_Cmnd *);
  19 int        aha152x_biosparam(Disk *, int, int*);
  20 
  21 /* number of queueable commands
  22    (unless we support more than 1 cmd_per_lun this should do) */
  23 #define AHA152X_MAXQUEUE        7               
  24 
  25 #define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 1.9 $"
  26 
  27 /* Initial value of Scsi_Host entry */
  28 #define AHA152X       { /* next */              NULL,                       \
  29                         /* usage_count */       NULL,                       \
  30                                                 NULL,                       \
  31                                                 "aha152x",                  \
  32                                                 PROC_SCSI_AHA152X,          \
  33                         /* name */              AHA152X_REVID,              \
  34                         /* detect */            aha152x_detect,             \
  35                         /* release */           NULL,                       \
  36                         /* info */              NULL,                       \
  37                         /* command */           aha152x_command,            \
  38                         /* queuecommand */      aha152x_queue,              \
  39                         /* abort */             aha152x_abort,              \
  40                         /* reset */             aha152x_reset,              \
  41                         /* slave_attach */      /* NULL */  0,              \
  42                         /* bios_param */        aha152x_biosparam,          \
  43                         /* can_queue */         1,                          \
  44                         /* this_id */           7,                          \
  45                         /* sg_tablesize */      SG_ALL,                     \
  46                         /* cmd_per_lun */       1,                          \
  47                         /* present */           0,                          \
  48                         /* unchecked_isa_dma */ 0,                          \
  49                         /* use_clustering */    DISABLE_CLUSTERING }
  50 #endif
  51 
  52 
  53 /* port addresses */
  54 #define SCSISEQ         (port_base+0x00)        /* SCSI sequence control */
  55 #define SXFRCTL0        (port_base+0x01)        /* SCSI transfer control 0 */
  56 #define SXFRCTL1        (port_base+0x02)        /* SCSI transfer control 1 */
  57 #define SCSISIG         (port_base+0x03)        /* SCSI signal in/out */
  58 #define SCSIRATE        (port_base+0x04)        /* SCSI rate control */
  59 #define SELID           (port_base+0x05)        /* selection/reselection ID */
  60 #define SCSIID          SELID                   /* SCSI ID */
  61 #define SCSIDAT         (port_base+0x06)        /* SCSI latched data */
  62 #define SCSIBUS         (port_base+0x07)        /* SCSI data bus */
  63 #define STCNT0          (port_base+0x08)        /* SCSI transfer count 0 */
  64 #define STCNT1          (port_base+0x09)        /* SCSI transfer count 1 */
  65 #define STCNT2          (port_base+0x0a)        /* SCSI transfer count 2 */
  66 #define SSTAT0          (port_base+0x0b)        /* SCSI interrupt status 0 */
  67 #define SSTAT1          (port_base+0x0c)        /* SCSI interrupt status 1 */
  68 #define SSTAT2          (port_base+0x0d)        /* SCSI interrupt status 2 */
  69 #define SCSITEST        (port_base+0x0e)        /* SCSI test control */
  70 #define SSTAT4          (port_base+0x0f)        /* SCSI status 4 */
  71 #define SIMODE0         (port_base+0x10)        /* SCSI interrupt mode 0 */
  72 #define SIMODE1         (port_base+0x11)        /* SCSI interrupt mode 1 */
  73 #define DMACNTRL0       (port_base+0x12)        /* DMA control 0 */
  74 #define DMACNTRL1       (port_base+0x13)        /* DMA control 1 */
  75 #define DMASTAT         (port_base+0x14)        /* DMA status */
  76 #define FIFOSTAT        (port_base+0x15)        /* FIFO status */
  77 #define DATAPORT        (port_base+0x16)        /* DATA port */
  78 #define BRSTCNTRL       (port_base+0x18)        /* burst control */
  79 #define PORTA           (port_base+0x1a)        /* PORT A */
  80 #define PORTB           (port_base+0x1b)        /* PORT B */
  81 #define REV             (port_base+0x1c)        /* revision */
  82 #define STACK           (port_base+0x1d)        /* stack */
  83 #define TEST            (port_base+0x1e)        /* test register */
  84 
  85 
  86 /* bits and bitmasks to ports */
  87 
  88 /* SCSI sequence control */
  89 #define TEMODEO         0x80
  90 #define ENSELO          0x40
  91 #define ENSELI          0x20
  92 #define ENRESELI        0x10
  93 #define ENAUTOATNO      0x08
  94 #define ENAUTOATNI      0x04
  95 #define ENAUTOATNP      0x02
  96 #define SCSIRSTO        0x01
  97 
  98 /* SCSI transfer control 0 */
  99 #define SCSIEN          0x80
 100 #define DMAEN           0x40
 101 #define CH1             0x20
 102 #define CLRSTCNT        0x10
 103 #define SPIOEN          0x08
 104 #define CLRCH1          0x02
 105 
 106 /* SCSI transfer control 1 */
 107 #define BITBUCKET       0x80
 108 #define SWRAPEN         0x40
 109 #define ENSPCHK         0x20
 110 #define STIMESEL        0x18    /* mask */
 111 #define STIMESEL_       3
 112 #define ENSTIMER        0x04
 113 #define BYTEALIGN       0x02
 114 
 115 /* SCSI signal IN */
 116 #define CDI             0x80
 117 #define IOI             0x40
 118 #define MSGI            0x20
 119 #define ATNI            0x10
 120 #define SELI            0x08
 121 #define BSYI            0x04
 122 #define REQI            0x02
 123 #define ACKI            0x01
 124 
 125 /* SCSI Phases */
 126 #define P_MASK          (MSGI|CDI|IOI)
 127 #define P_DATAO         (0)
 128 #define P_DATAI         (IOI)
 129 #define P_CMD           (CDI)
 130 #define P_STATUS        (CDI|IOI)
 131 #define P_MSGO          (MSGI|CDI)
 132 #define P_MSGI          (MSGI|CDI|IOI)
 133 
 134 /* SCSI signal OUT */
 135 #define CDO             0x80
 136 #define IOO             0x40
 137 #define MSGO            0x20
 138 #define ATNO            0x10
 139 #define SELO            0x08
 140 #define BSYO            0x04
 141 #define REQO            0x02
 142 #define ACKO            0x01
 143 
 144 /* SCSI rate control */
 145 #define SXFR            0x70    /* mask */
 146 #define SXFR_           4
 147 #define SOFS            0x0f    /* mask */
 148 
 149 /* SCSI ID */
 150 #define OID             0x70
 151 #define OID_            4
 152 #define TID             0x07
 153 
 154 /* SCSI transfer count */
 155 #define GETSTCNT()   ( (GETPORT(STCNT2)<<16) \
 156                      + (GETPORT(STCNT1)<< 8) \
 157                      + GETPORT(STCNT0) )
 158 
 159 #define SETSTCNT(X)  { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
 160                        SETPORT(STCNT1, ((X) & 0x00FF00) >>  8); \
 161                        SETPORT(STCNT0, ((X) & 0x0000FF) ); }
 162 
 163 /* SCSI interrupt status */
 164 #define TARGET          0x80
 165 #define SELDO           0x40
 166 #define SELDI           0x20
 167 #define SELINGO         0x10
 168 #define SWRAP           0x08
 169 #define SDONE           0x04
 170 #define SPIORDY         0x02
 171 #define DMADONE         0x01
 172 
 173 #define SETSDONE        0x80
 174 #define CLRSELDO        0x40
 175 #define CLRSELDI        0x20
 176 #define CLRSELINGO      0x10
 177 #define CLRSWRAP        0x08
 178 #define CLRSDONE        0x04
 179 #define CLRSPIORDY      0x02
 180 #define CLRDMADONE      0x01
 181 
 182 /* SCSI status 1 */
 183 #define SELTO           0x80
 184 #define ATNTARG         0x40
 185 #define SCSIRSTI        0x20
 186 #define PHASEMIS        0x10
 187 #define BUSFREE         0x08
 188 #define SCSIPERR        0x04
 189 #define PHASECHG        0x02
 190 #define REQINIT         0x01
 191 
 192 #define CLRSELTIMO      0x80
 193 #define CLRATNO         0x40
 194 #define CLRSCSIRSTI     0x20
 195 #define CLRBUSFREE      0x08
 196 #define CLRSCSIPERR     0x04
 197 #define CLRPHASECHG     0x02
 198 #define CLRREQINIT      0x01
 199 
 200 /* SCSI status 2 */
 201 #define SOFFSET         0x20
 202 #define SEMPTY          0x10
 203 #define SFULL           0x08
 204 #define SFCNT           0x07    /* mask */
 205 
 206 /* SCSI status 3 */
 207 #define SCSICNT         0xf0    /* mask */
 208 #define SCSICNT_        4
 209 #define OFFCNT          0x0f    /* mask */
 210 
 211 /* SCSI TEST control */
 212 #define SCTESTU         0x08
 213 #define SCTESTD         0x04
 214 #define STCTEST         0x01
 215 
 216 /* SCSI status 4 */
 217 #define SYNCERR         0x04
 218 #define FWERR           0x02
 219 #define FRERR           0x01
 220 
 221 #define CLRSYNCERR      0x04
 222 #define CLRFWERR        0x02
 223 #define CLRFRERR        0x01
 224 
 225 /* SCSI interrupt mode 0 */
 226 #define ENSELDO         0x40
 227 #define ENSELDI         0x20
 228 #define ENSELINGO       0x10
 229 #define ENSWRAP         0x08
 230 #define ENSDONE         0x04
 231 #define ENSPIORDY       0x02
 232 #define ENDMADONE       0x01
 233 
 234 /* SCSI interrupt mode 1 */
 235 #define ENSELTIMO       0x80
 236 #define ENATNTARG       0x40
 237 #define ENSCSIRST       0x20
 238 #define ENPHASEMIS      0x10
 239 #define ENBUSFREE       0x08
 240 #define ENSCSIPERR      0x04
 241 #define ENPHASECHG      0x02
 242 #define ENREQINIT       0x01
 243 
 244 /* DMA control 0 */
 245 #define ENDMA           0x80
 246 #define _8BIT           0x40
 247 #define DMA             0x20
 248 #define WRITE_READ      0x08
 249 #define INTEN           0x04
 250 #define RSTFIFO         0x02
 251 #define SWINT           0x01
 252 
 253 /* DMA control 1 */
 254 #define PWRDWN          0x80
 255 #define STK             0x07    /* mask */
 256 
 257 /* DMA status */
 258 #define ATDONE          0x80
 259 #define WORDRDY         0x40
 260 #define INTSTAT         0x20
 261 #define DFIFOFULL       0x10
 262 #define DFIFOEMP        0x08
 263 
 264 /* BURST control */
 265 #define BON             0xf0
 266 #define BOFF            0x0f
 267 
 268 /* TEST REGISTER */
 269 #define BOFFTMR         0x40
 270 #define BONTMR          0x20
 271 #define STCNTH          0x10
 272 #define STCNTM          0x08
 273 #define STCNTL          0x04
 274 #define SCSIBLK         0x02
 275 #define DMABLK          0x01
 276 
 277 /* On the AHA-152x board PORTA and PORTB contain
 278    some information about the board's configuration. */
 279 typedef union {
 280   struct {
 281     unsigned reserved:2;        /* reserved */
 282     unsigned tardisc:1;         /* Target disconnect: 0=disabled, 1=enabled */
 283     unsigned syncneg:1;         /* Initial sync neg: 0=disabled, 1=enabled */
 284     unsigned msgclasses:2;      /* Message classes
 285                                    0=#4
 286                                    1=#0, #1, #2, #3, #4
 287                                    2=#0, #3, #4
 288                                    3=#0, #4
 289                                 */
 290     unsigned boot:1;            /* boot: 0=disabled, 1=enabled */
 291     unsigned dma:1;             /* Transfer mode: 0=PIO; 1=DMA */
 292     unsigned id:3;              /* SCSI-id */
 293     unsigned irq:2;             /* IRQ-Channel: 0,3=12, 1=10, 2=11 */
 294     unsigned dmachan:2;         /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */
 295     unsigned parity:1;          /* SCSI-parity: 1=enabled 0=disabled */
 296   } fields;
 297   unsigned short port;
 298 } aha152x_config ;
 299 
 300 #define cf_parity       fields.parity
 301 #define cf_dmachan      fields.dmachan
 302 #define cf_irq          fields.irq
 303 #define cf_id           fields.id
 304 #define cf_dma          fields.dma
 305 #define cf_boot         fields.boot
 306 #define cf_msgclasses   fields.msgclasses
 307 #define cf_syncneg      fields.syncneg
 308 #define cf_tardisc      fields.tardisc
 309 #define cf_port         port
 310 
 311 /* Some macros to manipulate ports and their bits */
 312 
 313 #define SETPORT(PORT, VAL)      \
 314         outb( (VAL), (PORT) )
 315 
 316 #define SETPORTP(PORT, VAL)     \
 317         outb_p( (VAL), (PORT) )
 318 
 319 #define SETPORTW(PORT, VAL)     \
 320         outw( (VAL), (PORT) )
 321 
 322 #define GETPORT(PORT)   \
 323         inb( PORT )
 324 
 325 #define GETPORTW(PORT)  \
 326         inw( PORT )
 327 
 328 #define SETBITS(PORT, BITS)     \
 329         outb( (inb(PORT) | (BITS)), (PORT) )
 330 
 331 #define CLRBITS(PORT, BITS)     \
 332         outb( (inb(PORT) & ~(BITS)), (PORT) )
 333 
 334 #define CLRSETBITS(PORT, CLR, SET)      \
 335         outb( (inb(PORT) & ~(CLR)) | (SET) , (PORT) )
 336 
 337 #define TESTHI(PORT, BITS)      \
 338         ((inb(PORT) & (BITS)) == BITS)
 339 
 340 #define TESTLO(PORT, BITS)      \
 341         ((inb(PORT) & (BITS)) == 0)
 342 
 343 #ifdef DEBUG_AHA152X
 344 enum {
 345         debug_skipports =0x0001,
 346         debug_queue     =0x0002,
 347         debug_intr      =0x0004,
 348         debug_selection =0x0008,
 349         debug_msgo      =0x0010,
 350         debug_msgi      =0x0020,
 351         debug_status    =0x0040,
 352         debug_cmd       =0x0080,
 353         debug_datai     =0x0100,
 354         debug_datao     =0x0200,
 355         debug_abort     =0x0400,
 356         debug_done      =0x0800,
 357         debug_biosparam =0x1000,
 358         debug_phases    =0x2000,
 359         debug_queues    =0x4000,
 360         debug_reset     =0x8000,
 361 };
 362 #endif
 363 
 364 #endif /* _AHA152X_H */
/* */
root/drivers/scsi/aha152x.h

INCLUDED FROM
