include/asm-sparc/psr.h

/* */
This source file includes following definitions.
get_psr
put_psr
get_fsr
get_v9_pstate
put_v9_pstate
get_v9_version
get_v9_tstate
get_v9_pil
put_v9_pil
   1 /* psr.h: This file holds the macros for masking off various parts of
   2           the processor status register on the Sparc. This is valid
   3           for Version 8. On the V9 this is renamed to the PSTATE
   4           register and its members are accessed as fields like
   5           PSTATE.PRIV for the current CPU privilege level.
   6 
   7    Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
   8 */
   9 
  10 #ifndef __LINUX_SPARC_PSR_H
  11 #define __LINUX_SPARC_PSR_H
  12 
  13 #define __LINUX_SPARC_V8  /* duh */
  14 
  15 #ifdef __LINUX_SPARC_V8
  16 
  17 /* The Sparc PSR fields are laid out as the following:
  18 
  19     ------------------------------------------------------------------------
  20     | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
  21 bits| 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
  22     ------------------------------------------------------------------------
  23 
  24    The PSR can only be directly be written/read by the privileged instructions
  25    'rd' and 'wr'. Certain fields are changed as a side effect due to the 'Ticc',
  26    'save', 'restore', and 'rett' instructions. Also the integer condition codes
  27    'icc' are modified by various arithmetic instructions.
  28 
  29    For example:  wr  %o2, or'd_bit_pattern, %psr
  30                  rd  %psr, %o3
  31 
  32 */
  33 
  34 #define PSR_CWP     0x0000001f         /* current window pointer     */
  35 #define PSR_ET      0x00000020         /* enable traps field         */
  36 #define PSR_PS      0x00000040         /* previous privilege level   */
  37 #define PSR_S       0x00000080         /* current privilege level    */
  38 #define PSR_PIL     0x00000f00         /* processor interrupt level  */
  39 #define PSR_EF      0x00001000         /* enable floating point      */
  40 #define PSR_EC      0x00002000         /* enable co-processor        */
  41 #define PSR_ICC     0x00f00000         /* integer condition codes    */
  42 #define PSR_C       0x00100000         /* carry bit                  */
  43 #define PSR_V       0x00200000         /* overflow bit               */
  44 #define PSR_Z       0x00400000         /* zero bit                   */
  45 #define PSR_N       0x00800000         /* negative bit               */
  46 #define PSR_VERS    0x0f000000         /* cpu-version field          */
  47 #define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
  48 
  49 #ifndef __ASSEMBLY__
  50 /* Get the %psr register. */
  51 extern inline unsigned int get_psr(void)
     /*  */
  52 {
  53         unsigned int psr;
  54         __asm__ __volatile__("rd %%psr, %0\n\t" :
  55                              "=r" (psr));
  56         return psr;
  57 }
  58 
  59 extern inline void put_psr(unsigned int new_psr)
     /*  */
  60 {
  61   __asm__("wr %0, 0x0, %%psr\n\t" : :
  62           "r" (new_psr));
  63 }
  64 
  65 /* Get the %fsr register.  Be careful, make sure the floating point
  66  * enable bit is set in the %psr when you execute this or you will
  67  * incur a trap.
  68  */
  69 
  70 extern unsigned int fsr_storage;
  71 
  72 extern inline unsigned int get_fsr(void)
     /*  */
  73 {
  74         unsigned int fsr = 0;
  75 
  76         __asm__ __volatile__("st %%fsr, %1\n\t"
  77                              "ld %1, %0\n\t" :
  78                              "=r" (fsr) :
  79                              "m" (fsr_storage));
  80         return fsr;
  81 }
  82 
  83 #endif /* !(__ASSEMBLY__) */
  84 
  85 #endif /* !(__LINUX_SPARC_V8) */
  86 
  87 #ifdef __LINUX_SPARC_V9
  88 
  89 /* The information available in the %psr on the V8 is spread amongst
  90    a whole bunch of registers on the V9. The main one being PSTATE.
  91 
  92      --------------------------------------------------------
  93      |  CLE  | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
  94 bits |   9   |  8  |  7-6 |  5  |  4  |  3 |   2  |  1 |  0 |
  95      --------------------------------------------------------
  96 
  97    Writes and reads to PSTATE are done via 'wrpr' and 'rdpr' instructions.
  98 
  99    For example:  wrpr %o2, or'd_bit_pattern, %pstate
 100                  rdpr %pstate, %o3
 101 */
 102 
 103 #define PSTATE_AG    0x001   /* Alternate Globals             */
 104 #define PSTATE_IE    0x002   /* Interrupt Enable              */
 105 #define PSTATE_PRIV  0x004   /* Current privilege level       */
 106 #define PSTATE_AM    0x008   /* Address mask (data reads can  */
 107                              /* be chosen to be either big or */
 108                              /* little endian on V9).         */
 109 #define PSTATE_PEF   0x010   /* enable floating point         */
 110 #define PSTATE_RED   0x020   /* RED trap state (set if trap   */
 111                              /* trap_level == max_tl).        */
 112 #define PSTATE_MM    0x0c0   /* Memory model (Total Store     */
 113                              /* Order=0, Partial Store Order  */
 114                              /* =1 or Relaxed Memory Order=2) */
 115 #define PSTATE_TLE   0x100   /* Trap Little Endian            */
 116 #define PSTATE_CLE   0x200   /* Current Little Endian         */
 117 
 118 
 119 extern inline unsigned int get_v9_pstate(void)
     /*  */
 120 {
 121         unsigned int pstate;
 122         __asm__ __volatile__("rdpr %pstate, %0\n\t" :
 123                              "=r" (pstate));
 124         return pstate;
 125 }
 126 
 127 extern inline void put_v9_pstate(unsigned int pstate)
     /*  */
 128 {
 129         __asm__ __volatile__("wrpr %0, 0x0, %pstate\n\t" : :
 130                              "r" (pstate));
 131         return;
 132 }
 133 
 134 /* The Version Register holds vendor information for the chip:
 135 
 136     ---------------------------------------------------------------------------
 137     | manufacturer | implementation | mask | reserved | maxtl | resv | maxwin |
 138 bits|  63-48       |   47-32        | 31-24|   23-16  | 15-8  | 7-5  |  4-0   |
 139     ---------------------------------------------------------------------------
 140 
 141 */
 142 
 143 #define VERS_MAXWIN  0x000000000000001f     /* 'nwindows' on this chip       */
 144 #define VERS_MAXTL   0x00000000000ff000     /* Maximum Trap-level supported  */
 145 #define VERS_MASK    0x0000000ff0000000     /* impl. dep. chip mask revision */
 146 #define VERS_MANUF   0xffff000000000000     /* Manufacturer ID code          */
 147 
 148 extern inline unsigned int get_v9_version(void)
     /*  */
 149 {
 150         unsigned int vers;
 151         __asm__ __volatile__("rdpr %ver, %0\n\t" :
 152                              "=r" (vers));
 153         return vers;
 154 }
 155 
 156 extern inline unsigned int get_v9_tstate(void)
     /*  */
 157 {
 158         unsigned int tstate;
 159         __asm__ __volatile__("rdpr %tstate, %0\n\t" :
 160                              "=r" (pstate));
 161         return tstate;
 162 }
 163 
 164 extern inline unsigned int get_v9_pil(void)
     /*  */
 165 {
 166         unsigned int pil;
 167         __asm__ __volatile__("rdpr %pil, %0\n\t" :
 168                              "=r" (pstate));
 169         return pil;
 170 }
 171 
 172 extern inline void put_v9_pil(unsigned int pil)
     /*  */
 173 {
 174         __asm__ __volatile__("wrpr %0, 0x0, %pil\n\t" : :
 175                              "r" (pil));
 176         return;
 177 }
 178 
 179 
 180 #endif /* !(__LINUX_SPARC_V9) */
 181 
 182 #endif /* !(__LINUX_SPARC_PSR_H) */
/* */
root/include/asm-sparc/psr.h

INCLUDED FROM

DEFINITIONS
