drivers/pci/pci.c

/* */
This source file includes following definitions.
pci_lookup_dev
pci_strbioserr
pci_strclass
pci_strvendor
pci_strdev
burst_bridge
sprint_dev_config
get_pci_list
pci_malloc
scan_bus
pci_init
   1 /*
   2  * drivers/pci/pci.c
   3  *
   4  * PCI services that are built on top of the BIOS32 service.
   5  *
   6  * Copyright 1993, 1994, 1995 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  */
   9 #include <linux/config.h>
  10 #include <linux/ptrace.h>
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/bios32.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 
  17 #include <asm/page.h>
  18 
  19 struct pci_bus pci_root;
  20 struct pci_dev *pci_devices = 0;
  21 
  22 
  23 /*
  24  * The bridge_id field is an offset of an item into the array
  25  * BRIDGE_MAPPING_TYPE. 0xff indicates that the device is not a PCI
  26  * bridge, or that we don't know for the moment how to configure it.
  27  * I'm trying to do my best so that the kernel stays small.  Different
  28  * chipset can have same optimization structure. i486 and pentium
  29  * chipsets from the same manufacturer usually have the same
  30  * structure.
  31  */
  32 #define DEVICE(vid,did,name) \
  33   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
  34 
  35 #define BRIDGE(vid,did,name,bridge) \
  36   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
  37 
  38 /*
  39  * Sorted in ascending order by vendor and device.
  40  * Use binary search for lookup. If you add a device make sure
  41  * it is sequential by both vendor and device id.
  42  */
  43 struct pci_dev_info dev_info[] = {
  44         DEVICE( NCR,            NCR_53C810,     "53c810"),
  45         DEVICE( NCR,            NCR_53C820,     "53c820"),
  46         DEVICE( NCR,            NCR_53C825,     "53c825"),
  47         DEVICE( NCR,            NCR_53C815,     "53c815"),
  48         DEVICE( ATI,            ATI_68800,      "68800AX"),
  49         DEVICE( ATI,            ATI_215CT222,   "215CT222"),
  50         DEVICE( ATI,            ATI_210888CX,   "210888CX"),
  51         DEVICE( ATI,            ATI_210888GX,   "210888GX"),
  52         DEVICE( VLSI,           VLSI_82C592,    "82C592-FC1"),
  53         DEVICE( VLSI,           VLSI_82C593,    "82C593-FC1"),
  54         DEVICE( ADL,            ADL_2301,       "2301"),
  55         DEVICE( NS,             NS_87410,       "87410"),
  56         DEVICE( TSENG,          TSENG_W32P_2,   "ET4000W32P"),
  57         DEVICE( TSENG,          TSENG_W32P_b,   "ET4000W32P rev B"),
  58         DEVICE( TSENG,          TSENG_W32P_c,   "ET4000W32P rev C"),
  59         DEVICE( TSENG,          TSENG_W32P_d,   "ET4000W32P rev D"),
  60         DEVICE( WEITEK,         WEITEK_P9000,   "P9000"),
  61         DEVICE( WEITEK,         WEITEK_P9100,   "P9100"),
  62         DEVICE( DEC,            DEC_BRD,        "DC21050"),
  63         DEVICE( DEC,            DEC_TULIP,      "DC21040"),
  64         DEVICE( DEC,            DEC_TULIP_FAST, "DC21140"),
  65         DEVICE( DEC,            DEC_FDDI,       "DEFPA"),
  66         DEVICE( DEC,            DEC_TULIP_PLUS, "DC21041"),
  67         DEVICE( CIRRUS,         CIRRUS_5430,    "GD 5430"),
  68         DEVICE( CIRRUS,         CIRRUS_5434_4,  "GD 5434"),
  69         DEVICE( CIRRUS,         CIRRUS_5434_8,  "GD 5434"),
  70         DEVICE( CIRRUS,         CIRRUS_6729,    "CL 6729"),
  71         DEVICE( CIRRUS,         CIRRUS_7542,    "CL 7542"),
  72         DEVICE( AMD,            AMD_LANCE,      "79C970"),
  73         DEVICE( AMD,            AMD_SCSI,       "53C974"),
  74         DEVICE( TRIDENT,        TRIDENT_9420,   "TG 9420"),
  75         DEVICE( TRIDENT,        TRIDENT_9440,   "TG 9440"),
  76         DEVICE( AI,             AI_M1435,       "M1435"),
  77         DEVICE( MATROX,         MATROX_MGA_2,   "Atlas PX2085"),
  78         DEVICE( MATROX,         MATROX_MIL     ,"Millenium"),
  79         DEVICE( MATROX,         MATROX_MGA_IMP, "MGA Impression"),
  80         DEVICE( CT,             CT_65545,       "65545"),
  81         DEVICE( FD,             FD_36C70,       "TMC-18C30"),
  82         DEVICE( SI,             SI_503,         "85C503"),
  83         DEVICE( SI,             SI_501,         "85C501"),
  84         DEVICE( SI,             SI_496,         "85C496"),
  85         DEVICE( SI,             SI_601,         "85C601"),
  86         DEVICE( HP,             HP_J2585A,      "J2585A"),
  87 #if 0
  88         DEVICE( SMC,            SMC_37C665,     "FDC 37C665"),  /* 1042 ? */
  89         DEVICE( SMC,            SMC_37C922,     "FDC 37C922"),
  90 #else
  91         DEVICE( PCTECH,         PCTECH_RZ1000,  "RZ1000 (buggy)"), /* 1042 */
  92 #endif
  93         DEVICE( DPT,            DPT,            "SmartCache/Raid"),
  94         DEVICE( OPTI,           OPTI_82C557,    "82C557"),
  95         DEVICE( OPTI,           OPTI_82C558,    "82C558"),
  96         DEVICE( OPTI,           OPTI_82C621,    "82C621"),
  97         DEVICE( OPTI,           OPTI_82C822,    "82C822"),
  98         DEVICE( BUSLOGIC,       BUSLOGIC_946C_2,"946C"),
  99         DEVICE( BUSLOGIC,       BUSLOGIC_946C,  "946C"),
 100         DEVICE( PROMISE,        PROMISE_5300,   "DC5030"),
 101         DEVICE( N9,             N9_I128,        "Imagine 128"),
 102         DEVICE( UMC,            UMC_UM8673F,    "UM8673F"),
 103         BRIDGE( UMC,            UMC_UM8891A,    "UM8891A",              0x01),
 104         DEVICE( UMC,            UMC_UM8886A,    "UM8886A"),
 105         BRIDGE( UMC,            UMC_UM8881F,    "UM8881F",              0x02),
 106         DEVICE( UMC,            UMC_UM8886F,    "UM8886F"),
 107         DEVICE( X,              X_AGX016,       "ITT AGX016"),
 108         DEVICE( QLOGIC,         QLOGIC_ISP1020, "ISP1020"),
 109         DEVICE( QLOGIC,         QLOGIC_ISP1022, "ISP1022"),
 110         DEVICE( LEADTEK,        LEADTEK_805,    "S3 805"),
 111         DEVICE( CONTAQ,         CONTAQ_82C599,  "82C599"),
 112         DEVICE( CMD,            CMD_640,        "640A"),
 113         DEVICE( VISION,         VISION_QD8500,  "QD-8500"),
 114         DEVICE( VISION,         VISION_QD8580,  "QD-8580"),
 115         DEVICE( WINBOND,        WINBOND_83769,  "W83769F"),
 116         DEVICE( 3COM,           3COM_3C590,     "3C590 10bT"),
 117         DEVICE( 3COM,           3COM_3C595TX,   "3C595 100bTX"),
 118         DEVICE( 3COM,           3COM_3C595T4,   "3C595 100bT4"),
 119         DEVICE( 3COM,           3COM_3C595MII,  "3C595 100b-MII"),
 120         DEVICE( AL,             AL_M1445,       "M1445"),
 121         DEVICE( AL,             AL_M1449,       "M1449"),
 122         DEVICE( AL,             AL_M1451,       "M1451"),
 123         DEVICE( AL,             AL_M1461,       "M1461"),
 124         DEVICE( AL,             AL_M4803,       "M4803"),
 125         DEVICE( IMS,            IMS_8849,       "8849"),
 126         DEVICE( VIA,            VIA_82C505,     "VT 82C505"),
 127         DEVICE( VIA,            VIA_82C561,     "VT 82C561"),
 128         DEVICE( VIA,            VIA_82C576,     "VT 82C576 3V"),
 129         DEVICE( VORTEX,         VORTEX_GDT,     "GDT 6000b"),
 130         DEVICE( EF,             EF_ATM,         "155P-MF1"),
 131         DEVICE( IMAGINGTECH,    IMAGINGTECH_ICPCI, "MVC IC-PCI"),
 132         DEVICE( PLX,            PLX_9060,       "PCI9060 i960 bridge"),
 133         DEVICE( MUTECH,         MUTECH_MV1000,  "MV-1000"),
 134         DEVICE( ZEINET,         ZEINET_1221,    "1221"),
 135         DEVICE( CYCLADES,       CYCLADES_Y,     "Cyclome-Y"),
 136         DEVICE( SYMPHONY,       SYMPHONY_101,   "82C101"),
 137         DEVICE( TEKRAM,         TEKRAM_DC290,   "DC-290"),
 138         DEVICE( S3,             S3_811,         "Trio32/Trio64"),
 139         DEVICE( S3,             S3_868, "Vision 868"),
 140         DEVICE( S3,             S3_928,         "Vision 928-P"),
 141         DEVICE( S3,             S3_864_1,       "Vision 864-P"),
 142         DEVICE( S3,             S3_864_2,       "Vision 864-P"),
 143         DEVICE( S3,             S3_964_1,       "Vision 964-P"),
 144         DEVICE( S3,             S3_964_2,       "Vision 964-P"),
 145         DEVICE( S3,             S3_968,         "Vision 968"),
 146         DEVICE( INTEL,          INTEL_82375,    "82375EB"),
 147         BRIDGE( INTEL,          INTEL_82424,    "82424ZX Saturn",       0x00),
 148         DEVICE( INTEL,          INTEL_82378,    "82378IB"),
 149         DEVICE( INTEL,          INTEL_82430,    "82430ZX Aries"),
 150         BRIDGE( INTEL,          INTEL_82434,    "82434LX Mercury/Neptune", 0x00),
 151         DEVICE( INTEL,          INTEL_7116,     "SAA7116"),
 152         DEVICE( INTEL,          INTEL_82865,    "82865"),
 153         DEVICE( INTEL,          INTEL_82437,    "82437 Triton"),
 154         DEVICE( INTEL,          INTEL_82371,    "82371 Triton"),
 155         DEVICE( INTEL,          INTEL_82438,    "82438"),
 156         DEVICE( INTEL,          INTEL_P6,       "Experimental P6 bridge"),
 157         DEVICE( ADAPTEC,        ADAPTEC_7850,   "AIC-7850"),
 158         DEVICE( ADAPTEC,        ADAPTEC_294x,   "294x"),
 159         DEVICE( ADAPTEC,        ADAPTEC_2940,   "2940"),
 160         DEVICE( ATRONICS,       ATRONICS_2015,  "IDE-2015PL"),
 161         DEVICE( HER,            HER_STING,      "Stingray"),
 162         DEVICE( HER,            HER_STINGARK,   "Stingray ARK 2000PV")
 163 };
 164 
 165 
 166 #ifdef CONFIG_PCI_OPTIMIZE
 167 
 168 /*
 169  * An item of this structure has the following meaning:
 170  * for each optimization, the register address, the mask
 171  * and value to write to turn it on.
 172  * There are 5 optimizations for the moment:
 173  * Cache L2 write back best than write through
 174  * Posted Write for CPU to PCI enable
 175  * Posted Write for CPU to MEMORY enable
 176  * Posted Write for PCI to MEMORY enable
 177  * PCI Burst enable
 178  *
 179  * Half of the bios I've meet don't allow you to turn that on, and you
 180  * can gain more than 15% on graphic accesses using those
 181  * optimizations...
 182  */
 183 struct optimization_type {
 184         const char      *type;
 185         const char      *off;
 186         const char      *on;
 187 } bridge_optimization[] = {
 188         {"Cache L2",                    "write trough", "write back"},
 189         {"CPU-PCI posted write",        "off",          "on"},
 190         {"CPU-Memory posted write",     "off",          "on"},
 191         {"PCI-Memory posted write",     "off",          "on"},
 192         {"PCI burst",                   "off",          "on"}
 193 };
 194 
 195 #define NUM_OPTIMIZATIONS \
 196         (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
 197 
 198 struct bridge_mapping_type {
 199         unsigned char   addr;   /* config space address */
 200         unsigned char   mask;
 201         unsigned char   value;
 202 } bridge_mapping[] = {
 203         /*
 204          * Intel Neptune/Mercury/Saturn:
 205          *      If the internal cache is write back,
 206          *      the L2 cache must be write through!
 207          *      I've to check out how to control that
 208          *      for the moment, we won't touch the cache
 209          */
 210         {0x0    ,0x02   ,0x02   },
 211         {0x53   ,0x02   ,0x02   },
 212         {0x53   ,0x01   ,0x01   },
 213         {0x54   ,0x01   ,0x01   },
 214         {0x54   ,0x02   ,0x02   },
 215 
 216         /*
 217          * UMC 8891A Pentium chipset:
 218          *      Why did you think UMC was cheaper ??
 219          */
 220         {0x50   ,0x10   ,0x00   },
 221         {0x51   ,0x40   ,0x40   },
 222         {0x0    ,0x0    ,0x0    },
 223         {0x0    ,0x0    ,0x0    },
 224         {0x0    ,0x0    ,0x0    },
 225 
 226         /*
 227          * UMC UM8881F
 228          *      This is a dummy entry for my tests.
 229          *      I have this chipset and no docs....
 230          */
 231         {0x0    ,0x1    ,0x1    },
 232         {0x0    ,0x2    ,0x0    },
 233         {0x0    ,0x0    ,0x0    },
 234         {0x0    ,0x0    ,0x0    },
 235         {0x0    ,0x0    ,0x0    }
 236 };
 237 
 238 #endif /* CONFIG_PCI_OPTIMIZE */
 239 
 240 
 241 /*
 242  * device_info[] is sorted so we can use binary search
 243  */
 244 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
     /*  */
 245 {
 246         int min = 0,
 247             max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
 248 
 249         for ( ; ; )
 250         {
 251             int i = (min + max) >> 1;
 252             long order;
 253 
 254             order = dev_info[i].vendor - (long) vendor;
 255             if (!order)
 256                 order = dev_info[i].device - (long) dev;
 257         
 258             if (order < 0)
 259             {
 260                     min = i + 1;
 261                     if ( min > max )
 262                        return 0;
 263                     continue;
 264             }
 265 
 266             if (order > 0)
 267             {
 268                     max = i - 1;
 269                     if ( min > max )
 270                        return 0;
 271                     continue;
 272             }
 273 
 274             return & dev_info[ i ];
 275         }
 276 }
 277 
 278 
 279 const char *pci_strbioserr (int error)
     /*  */
 280 {
 281         switch (error) {
 282               case PCIBIOS_SUCCESSFUL:          return "SUCCESSFUL";
 283               case PCIBIOS_FUNC_NOT_SUPPORTED:  return "FUNC_NOT_SUPPORTED";
 284               case PCIBIOS_BAD_VENDOR_ID:       return "SUCCESSFUL";
 285               case PCIBIOS_DEVICE_NOT_FOUND:    return "DEVICE_NOT_FOUND";
 286               case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
 287               case PCIBIOS_SET_FAILED:          return "SET_FAILED";
 288               case PCIBIOS_BUFFER_TOO_SMALL:    return "BUFFER_TOO_SMALL";
 289               default:                          return "Unknown error status";
 290         }
 291 }
 292 
 293 
 294 const char *pci_strclass (unsigned int class)
     /*  */
 295 {
 296         switch (class >> 8) {
 297               case PCI_CLASS_NOT_DEFINED:               return "Non-VGA device";
 298               case PCI_CLASS_NOT_DEFINED_VGA:           return "VGA compatible device";
 299 
 300               case PCI_CLASS_STORAGE_SCSI:              return "SCSI storage controller";
 301               case PCI_CLASS_STORAGE_IDE:               return "IDE interface";
 302               case PCI_CLASS_STORAGE_FLOPPY:            return "Floppy disk controller";
 303               case PCI_CLASS_STORAGE_IPI:               return "IPI bus controller";
 304               case PCI_CLASS_STORAGE_RAID:              return "RAID bus controller";
 305               case PCI_CLASS_STORAGE_OTHER:             return "Unknown mass storage controller";
 306 
 307               case PCI_CLASS_NETWORK_ETHERNET:          return "Ethernet controller";
 308               case PCI_CLASS_NETWORK_TOKEN_RING:        return "Token ring network controller";
 309               case PCI_CLASS_NETWORK_FDDI:              return "FDDI network controller";
 310               case PCI_CLASS_NETWORK_ATM:               return "ATM network controller";
 311               case PCI_CLASS_NETWORK_OTHER:             return "Network controller";
 312 
 313               case PCI_CLASS_DISPLAY_VGA:               return "VGA compatible controller";
 314               case PCI_CLASS_DISPLAY_XGA:               return "XGA compatible controller";
 315               case PCI_CLASS_DISPLAY_OTHER:             return "Display controller";
 316 
 317               case PCI_CLASS_MULTIMEDIA_VIDEO:          return "Multimedia video controller";
 318               case PCI_CLASS_MULTIMEDIA_AUDIO:          return "Multimedia audio controller";
 319               case PCI_CLASS_MULTIMEDIA_OTHER:          return "Multimedia controller";
 320 
 321               case PCI_CLASS_MEMORY_RAM:                return "RAM memory";
 322               case PCI_CLASS_MEMORY_FLASH:              return "FLASH memory";
 323               case PCI_CLASS_MEMORY_OTHER:              return "Memory";
 324 
 325               case PCI_CLASS_BRIDGE_HOST:               return "Host bridge";
 326               case PCI_CLASS_BRIDGE_ISA:                return "ISA bridge";
 327               case PCI_CLASS_BRIDGE_EISA:               return "EISA bridge";
 328               case PCI_CLASS_BRIDGE_MC:                 return "MicroChannel bridge";
 329               case PCI_CLASS_BRIDGE_PCI:                return "PCI bridge";
 330               case PCI_CLASS_BRIDGE_PCMCIA:             return "PCMCIA bridge";
 331               case PCI_CLASS_BRIDGE_NUBUS:              return "NuBus bridge";
 332               case PCI_CLASS_BRIDGE_CARDBUS:            return "CardBus bridge";
 333               case PCI_CLASS_BRIDGE_OTHER:              return "Bridge";
 334 
 335               case PCI_CLASS_COMMUNICATION_SERIAL:      return "Serial controller";
 336               case PCI_CLASS_COMMUNICATION_PARALLEL:    return "Parallel controller";
 337               case PCI_CLASS_COMMUNICATION_OTHER:       return "Communication controller";
 338 
 339               case PCI_CLASS_SYSTEM_PIC:                return "PIC";
 340               case PCI_CLASS_SYSTEM_DMA:                return "DMA controller";
 341               case PCI_CLASS_SYSTEM_TIMER:              return "Timer";
 342               case PCI_CLASS_SYSTEM_RTC:                return "RTC";
 343               case PCI_CLASS_SYSTEM_OTHER:              return "System peripheral";
 344 
 345               case PCI_CLASS_INPUT_KEYBOARD:            return "Keyboard controller";
 346               case PCI_CLASS_INPUT_PEN:                 return "Digitizer Pen";
 347               case PCI_CLASS_INPUT_MOUSE:               return "Mouse controller";
 348               case PCI_CLASS_INPUT_OTHER:               return "Input device controller";
 349 
 350               case PCI_CLASS_DOCKING_GENERIC:           return "Generic Docking Station";
 351               case PCI_CLASS_DOCKING_OTHER:             return "Docking Station";
 352 
 353               case PCI_CLASS_PROCESSOR_386:             return "386";
 354               case PCI_CLASS_PROCESSOR_486:             return "486";
 355               case PCI_CLASS_PROCESSOR_PENTIUM:         return "Pentium";
 356               case PCI_CLASS_PROCESSOR_ALPHA:           return "Alpha";
 357               case PCI_CLASS_PROCESSOR_POWERPC:         return "Power PC";
 358               case PCI_CLASS_PROCESSOR_CO:              return "Co-processor";
 359 
 360               case PCI_CLASS_SERIAL_FIREWIRE:           return "FireWire (IEEE 1394)";
 361               case PCI_CLASS_SERIAL_ACCESS:             return "ACCESS Bus";
 362               case PCI_CLASS_SERIAL_SSA:                return "SSA";
 363               case PCI_CLASS_SERIAL_FIBER:              return "Fiber Channel";
 364 
 365               default:                                  return "Unknown class";
 366         }
 367 }
 368 
 369 
 370 const char *pci_strvendor(unsigned int vendor)
     /*  */
 371 {
 372         switch (vendor) {
 373               case PCI_VENDOR_ID_NCR:           return "NCR";
 374               case PCI_VENDOR_ID_ADAPTEC:       return "Adaptec";
 375               case PCI_VENDOR_ID_DPT:           return "DPT";
 376               case PCI_VENDOR_ID_S3:            return "S3 Inc.";
 377               case PCI_VENDOR_ID_OPTI:          return "OPTI";
 378               case PCI_VENDOR_ID_UMC:           return "UMC";
 379               case PCI_VENDOR_ID_DEC:           return "DEC";
 380               case PCI_VENDOR_ID_MATROX:        return "Matrox";
 381               case PCI_VENDOR_ID_INTEL:         return "Intel";
 382 #if 0
 383               case PCI_VENDOR_ID_SMC:           return "SMC";
 384 #else
 385               case PCI_VENDOR_ID_PCTECH:        return "PCTECH";
 386 #endif
 387               case PCI_VENDOR_ID_ATI:           return "ATI";
 388               case PCI_VENDOR_ID_WEITEK:        return "Weitek";
 389               case PCI_VENDOR_ID_CIRRUS:        return "Cirrus Logic";
 390               case PCI_VENDOR_ID_BUSLOGIC:      return "Bus Logic";
 391               case PCI_VENDOR_ID_N9:            return "Number Nine";
 392               case PCI_VENDOR_ID_AI:            return "Acer Incorporated";
 393               case PCI_VENDOR_ID_AL:            return "Acer Labs";
 394               case PCI_VENDOR_ID_TSENG:         return "Tseng'Lab";
 395               case PCI_VENDOR_ID_CMD:           return "CMD";
 396               case PCI_VENDOR_ID_VISION:        return "Vision";
 397               case PCI_VENDOR_ID_AMD:           return "AMD";
 398               case PCI_VENDOR_ID_VLSI:          return "VLSI";
 399               case PCI_VENDOR_ID_ADL:           return "Advance Logic";
 400               case PCI_VENDOR_ID_SYMPHONY:      return "Symphony";
 401               case PCI_VENDOR_ID_TRIDENT:       return "Trident";
 402               case PCI_VENDOR_ID_CONTAQ:        return "Contaq";
 403               case PCI_VENDOR_ID_NS:            return "NS";
 404               case PCI_VENDOR_ID_VIA:           return "VIA Technologies";
 405               case PCI_VENDOR_ID_SI:            return "Silicon Integrated Systems";
 406               case PCI_VENDOR_ID_LEADTEK:       return "Leadtek Research";
 407               case PCI_VENDOR_ID_IMS:           return "IMS";
 408               case PCI_VENDOR_ID_ZEINET:        return "ZeiNet";
 409               case PCI_VENDOR_ID_EF:            return "Efficient Networks";
 410               case PCI_VENDOR_ID_HER:           return "Hercules";
 411               case PCI_VENDOR_ID_ATRONICS:      return "Atronics";
 412               case PCI_VENDOR_ID_CT:            return "Chips & Technologies";
 413               case PCI_VENDOR_ID_FD:            return "Future Domain";
 414               case PCI_VENDOR_ID_WINBOND:       return "Winbond";
 415               case PCI_VENDOR_ID_3COM:          return "3Com";
 416               case PCI_VENDOR_ID_PROMISE:       return "Promise Technology";
 417               case PCI_VENDOR_ID_QLOGIC:        return "Q Logic";
 418               case PCI_VENDOR_ID_X:             return "X TECHNOLOGY";
 419               case PCI_VENDOR_ID_ACC:           return "ACC MICROELECTRONICS";
 420               case PCI_VENDOR_ID_VORTEX:        return "VORTEX";
 421               case PCI_VENDOR_ID_HP:            return "Hewlett Packard";
 422               case PCI_VENDOR_ID_IMAGINGTECH:   return "Imaging Technology";
 423               case PCI_VENDOR_ID_CYCLADES:      return "Cyclades";
 424               case PCI_VENDOR_ID_OLICOM:        return "Olicom";
 425               default:                          return "Unknown vendor";
 426         }
 427 }
 428 
 429 
 430 const char *pci_strdev(unsigned int vendor, unsigned int device)
     /*  */
 431 {
 432         struct pci_dev_info *info;
 433 
 434         info =  pci_lookup_dev(vendor, device);
 435         return info ? info->name : "Unknown device";
 436 }
 437 
 438 
 439 
 440 /*
 441  * Turn on/off PCI bridge optimization. This should allow benchmarking.
 442  */
 443 static void burst_bridge(unsigned char bus, unsigned char devfn,
     /*  */
 444                          unsigned char pos, int turn_on)
 445 {
 446 #ifdef CONFIG_PCI_OPTIMIZE
 447         struct bridge_mapping_type *bmap;
 448         unsigned char val;
 449         int i;
 450 
 451         pos *= NUM_OPTIMIZATIONS;
 452         printk("PCI bridge optimization.\n");
 453         for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
 454                 printk("    %s: ", bridge_optimization[i].type);
 455                 bmap = &bridge_mapping[pos + i];
 456                 if (!bmap->addr) {
 457                         printk("Not supported.");
 458                 } else {
 459                         pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
 460                         if ((val & bmap->mask) == bmap->value) {
 461                                 printk("%s.", bridge_optimization[i].on);
 462                                 if (!turn_on) {
 463                                         pcibios_write_config_byte(bus, devfn,
 464                                                                   bmap->addr,
 465                                                                   (val | bmap->mask)
 466                                                                   - bmap->value);
 467                                         printk("Changed!  Now %s.", bridge_optimization[i].off);
 468                                 }
 469                         } else {
 470                                 printk("%s.", bridge_optimization[i].off);
 471                                 if (turn_on) {
 472                                         pcibios_write_config_byte(bus, devfn,
 473                                                                   bmap->addr,
 474                                                                   (val & (0xff - bmap->mask))
 475                                                                   + bmap->value);
 476                                         printk("Changed!  Now %s.", bridge_optimization[i].on);
 477                                 }
 478                         }
 479                 }
 480                 printk("\n");
 481         }
 482 #endif /* CONFIG_PCI_OPTIMIZE */
 483 }
 484 
 485 
 486 /*
 487  * Convert some of the configuration space registers of the device at
 488  * address (bus,devfn) into a string (possibly several lines each).
 489  * The configuration string is stored starting at buf[len].  If the
 490  * string would exceed the size of the buffer (SIZE), 0 is returned.
 491  */
 492 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
     /*  */
 493 {
 494         unsigned long base;
 495         unsigned int l, class_rev, bus, devfn;
 496         unsigned short vendor, device, status;
 497         unsigned char bist, latency, min_gnt, max_lat;
 498         int reg, len = 0;
 499         const char *str;
 500 
 501         bus   = dev->bus->number;
 502         devfn = dev->devfn;
 503 
 504         pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
 505         pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
 506         pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
 507         pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
 508         pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
 509         pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
 510         pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
 511         pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
 512         if (len + 80 > size) {
 513                 return -1;
 514         }
 515         len += sprintf(buf + len, "  Bus %2d, device %3d, function %2d:\n",
 516                        bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
 517 
 518         if (len + 80 > size) {
 519                 return -1;
 520         }
 521         len += sprintf(buf + len, "    %s: %s %s (rev %d).\n      ",
 522                        pci_strclass(class_rev >> 8), pci_strvendor(vendor),
 523                        pci_strdev(vendor, device), class_rev & 0xff);
 524 
 525         if (!pci_lookup_dev(vendor, device)) {
 526                 len += sprintf(buf + len,
 527                                "Vendor id=%x. Device id=%x.\n      ",
 528                                vendor, device);
 529         }
 530 
 531         str = 0;        /* to keep gcc shut... */
 532         switch (status & PCI_STATUS_DEVSEL_MASK) {
 533               case PCI_STATUS_DEVSEL_FAST:   str = "Fast devsel.  "; break;
 534               case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel.  "; break;
 535               case PCI_STATUS_DEVSEL_SLOW:   str = "Slow devsel.  "; break;
 536         }
 537         if (len + strlen(str) > size) {
 538                 return -1;
 539         }
 540         len += sprintf(buf + len, str);
 541 
 542         if (status & PCI_STATUS_FAST_BACK) {
 543 #               define fast_b2b_capable "Fast back-to-back capable.  "
 544                 if (len + strlen(fast_b2b_capable) > size) {
 545                         return -1;
 546                 }
 547                 len += sprintf(buf + len, fast_b2b_capable);
 548 #               undef fast_b2b_capable
 549         }
 550 
 551         if (bist & PCI_BIST_CAPABLE) {
 552 #               define BIST_capable     "BIST capable.  "
 553                 if (len + strlen(BIST_capable) > size) {
 554                         return -1;
 555                 }
 556                 len += sprintf(buf + len, BIST_capable);
 557 #               undef BIST_capable
 558         }
 559 
 560         if (dev->irq) {
 561                 if (len + 40 > size) {
 562                         return -1;
 563                 }
 564                 len += sprintf(buf + len, "IRQ %d.  ", dev->irq);
 565         }
 566 
 567         if (dev->master) {
 568                 if (len + 80 > size) {
 569                         return -1;
 570                 }
 571                 len += sprintf(buf + len, "Master Capable.  ");
 572                 if (latency)
 573                   len += sprintf(buf + len, "Latency=%d.  ", latency);
 574                 else
 575                   len += sprintf(buf + len, "No bursts.  ");
 576                 if (min_gnt)
 577                   len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
 578                 if (max_lat)
 579                   len += sprintf(buf + len, "Max Lat=%d.", max_lat);
 580         }
 581 
 582         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 583                 if (len + 40 > size) {
 584                         return -1;
 585                 }
 586                 pcibios_read_config_dword(bus, devfn, reg, &l);
 587                 base = l;
 588                 if (!base) {
 589                         continue;
 590                 }
 591 
 592                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 593                         len += sprintf(buf + len,
 594                                        "\n      I/O at 0x%lx.",
 595                                        base & PCI_BASE_ADDRESS_IO_MASK);
 596                 } else {
 597                         const char *pref, *type = "unknown";
 598 
 599                         if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 600                                 pref = "P";
 601                         } else {
 602                                 pref = "Non-p";
 603                         }
 604                         switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
 605                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 606                                 type = "32 bit"; break;
 607                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 608                                 type = "20 bit"; break;
 609                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 610                                 type = "64 bit";
 611                                 /* read top 32 bit address of base addr: */
 612                                 reg += 4;
 613                                 pcibios_read_config_dword(bus, devfn, reg, &l);
 614                                 base |= ((u64) l) << 32;
 615                                 break;
 616                         }
 617                         len += sprintf(buf + len,
 618                                        "\n      %srefetchable %s memory at "
 619                                        "0x%lx.", pref, type,
 620                                        base & PCI_BASE_ADDRESS_MEM_MASK);
 621                 }
 622         }
 623 
 624         len += sprintf(buf + len, "\n");
 625         return len;
 626 }
 627 
 628 
 629 /*
 630  * Return list of PCI devices as a character string for /proc/pci.
 631  * BUF is a buffer that is PAGE_SIZE bytes long.
 632  */
 633 int get_pci_list(char *buf)
     /*  */
 634 {
 635         int nprinted, len, size;
 636         struct pci_dev *dev;
 637 #       define MSG "\nwarning: page-size limit reached!\n"
 638 
 639         /* reserve same for truncation warning message: */
 640         size  = PAGE_SIZE - (strlen(MSG) + 1);
 641         len   = sprintf(buf, "PCI devices found:\n");
 642 
 643         for (dev = pci_devices; dev; dev = dev->next) {
 644                 nprinted = sprint_dev_config(dev, buf + len, size - len);
 645                 if (nprinted < 0) {
 646                         return len + sprintf(buf + len, MSG);
 647                 }
 648                 len += nprinted;
 649         }
 650         return len;
 651 }
 652 
 653 
 654 /*
 655  * pci_malloc() returns initialized memory of size SIZE.  Can be
 656  * used only while pci_init() is active.
 657  */
 658 static void *pci_malloc(long size, unsigned long *mem_startp)
     /*  */
 659 {
 660         void *mem;
 661 
 662 #ifdef DEBUG
 663         printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
 664 #endif
 665         mem = (void*) *mem_startp;
 666         *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
 667         memset(mem, 0, size);
 668         return mem;
 669 }
 670 
 671 
 672 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
     /*  */
 673 {
 674         unsigned int devfn, l, max;
 675         unsigned char cmd, tmp, hdr_type = 0;
 676         struct pci_dev_info *info;
 677         struct pci_dev *dev;
 678         struct pci_bus *child;
 679 
 680 #ifdef DEBUG
 681         printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
 682 #endif
 683 
 684         max = bus->secondary;
 685         for (devfn = 0; devfn < 0xff; ++devfn) {
 686                 if (PCI_FUNC(devfn) == 0) {
 687                         pcibios_read_config_byte(bus->number, devfn,
 688                                                  PCI_HEADER_TYPE, &hdr_type);
 689                 } else if (!(hdr_type & 0x80)) {
 690                         /* not a multi-function device */
 691                         continue;
 692                 }
 693 
 694                 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
 695                                           &l);
 696                 /* some broken boards return 0 if a slot is empty: */
 697                 if (l == 0xffffffff || l == 0x00000000) {
 698                         hdr_type = 0;
 699                         continue;
 700                 }
 701 
 702                 dev = pci_malloc(sizeof(*dev), mem_startp);
 703                 dev->bus = bus;
 704                 /*
 705                  * Put it into the simple chain of devices on this
 706                  * bus.  It is used to find devices once everything is
 707                  * set up.
 708                  */
 709                 dev->next = pci_devices;
 710                 pci_devices = dev;
 711 
 712                 dev->devfn  = devfn;
 713                 dev->vendor = l & 0xffff;
 714                 dev->device = (l >> 16) & 0xffff;
 715 
 716                 /*
 717                  * Check to see if we now about this device and report
 718                  * a message at boot time.  This is the only way to
 719                  * learn about new hardware...
 720                  */
 721                 info = pci_lookup_dev(dev->vendor, dev->device);
 722                 if (!info) {
 723                         printk("Warning : Unknown PCI device (%x:%x).  Please read include/linux/pci.h \n",
 724                                 dev->vendor, dev->device);
 725                 } else {
 726                         /* Some BIOS' are lazy. Let's do their job: */
 727                         if (info->bridge_type != 0xff) {
 728                                 burst_bridge(bus->number, devfn,
 729                                              info->bridge_type, 1);
 730                         }
 731                 }
 732 
 733                 /* non-destructively determine if device can be a master: */
 734                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 735                                          &cmd);
 736                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 737                                           cmd | PCI_COMMAND_MASTER);
 738                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 739                                          &tmp);
 740                 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
 741                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 742                                           cmd);
 743 
 744                 /* read irq level (may be changed during pcibios_fixup()): */
 745                 pcibios_read_config_byte(bus->number, devfn,
 746                                          PCI_INTERRUPT_LINE, &dev->irq);
 747 
 748                 /* check to see if this device is a PCI-PCI bridge: */
 749                 pcibios_read_config_dword(bus->number, devfn,
 750                                           PCI_CLASS_REVISION, &l);
 751                 l = l >> 8;                     /* upper 3 bytes */
 752                 dev->class = l;
 753                 /*
 754                  * Now insert it into the list of devices held
 755                  * by the parent bus.
 756                  */
 757                 dev->sibling = bus->devices;
 758                 bus->devices = dev;
 759 
 760                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
 761                         unsigned int buses;
 762                         unsigned short cr;
 763 
 764                         /*
 765                          * Insert it into the tree of buses.
 766                          */
 767                         child = pci_malloc(sizeof(*child), mem_startp);
 768                         child->next   = bus->children;
 769                         bus->children = child;
 770                         child->self = dev;
 771                         child->parent = bus;
 772 
 773                         /*
 774                          * Set up the primary, secondary and subordinate
 775                          * bus numbers.
 776                          */
 777                         child->number = child->secondary = ++max;
 778                         child->primary = bus->secondary;
 779                         child->subordinate = 0xff;
 780                         /*
 781                          * Clear all status bits and turn off memory,
 782                          * I/O and master enables.
 783                          */
 784                         pcibios_read_config_word(bus->number, devfn,
 785                                                   PCI_COMMAND, &cr);
 786                         pcibios_write_config_word(bus->number, devfn,
 787                                                   PCI_COMMAND, 0x0000);
 788                         pcibios_write_config_word(bus->number, devfn,
 789                                                   PCI_STATUS, 0xffff);
 790                         /*
 791                          * Configure the bus numbers for this bridge:
 792                          */
 793                         pcibios_read_config_dword(bus->number, devfn, 0x18,
 794                                                   &buses);
 795                         buses &= 0xff000000;
 796                         buses |= (((unsigned int)(child->primary)     <<  0) |
 797                                   ((unsigned int)(child->secondary)   <<  8) |
 798                                   ((unsigned int)(child->subordinate) << 16));
 799                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 800                                                    buses);
 801                         /*
 802                          * Now we can scan all subordinate buses:
 803                          */
 804                         max = scan_bus(child, mem_startp);
 805                         /*
 806                          * Set the subordinate bus number to its real
 807                          * value:
 808                          */
 809                         child->subordinate = max;
 810                         buses = (buses & 0xff00ffff)
 811                           | ((unsigned int)(child->subordinate) << 16);
 812                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 813                                                    buses);
 814                         pcibios_write_config_word(bus->number, devfn,
 815                                                   PCI_COMMAND, cr);
 816                 }
 817         }
 818         /*
 819          * We've scanned the bus and so we know all about what's on
 820          * the other side of any bridges that may be on this bus plus
 821          * any devices.
 822          *
 823          * Return how far we've got finding sub-buses.
 824          */
 825         return max;
 826 }
 827 
 828 
 829 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
     /*  */
 830 {
 831         mem_start = pcibios_init(mem_start, mem_end);
 832 
 833         if (!pcibios_present()) {
 834                 printk("pci_init: no BIOS32 detected\n");
 835                 return mem_start;
 836         }
 837 
 838         printk("Probing PCI hardware.\n");
 839 
 840         memset(&pci_root, 0, sizeof(pci_root));
 841         pci_root.subordinate = scan_bus(&pci_root, &mem_start);
 842 
 843         /* give BIOS a chance to apply platform specific fixes: */
 844         mem_start = pcibios_fixup(mem_start, mem_end);
 845 
 846 #ifdef DEBUG
 847         {
 848                 int len = get_pci_list((char*)mem_start);
 849                 if (len) {
 850                         ((char *) mem_start)[len] = '\0';
 851                         printk("%s\n", (char *) mem_start);
 852                 }
 853         }
 854 #endif
 855         return mem_start;
 856 }
/* */
root/drivers/pci/pci.c

DEFINITIONS
