include/asm-i386/smp.h

/* */
This source file includes following definitions.
apic_write
apic_read
smp_processor_id
   1 #ifndef __ASM_SMP_H
   2 #define __ASM_SMP_H
   3 
   4 #ifndef ASSEMBLY
   5 
   6 #include <asm/i82489.h>
   7 
   8 /*
   9  *      Support definitions for SMP machines following the intel multiprocessing
  10  *      specification
  11  */
  12 
  13 /*
  14  *      This tag identifies where the SMP configuration
  15  *      information is. 
  16  */
  17  
  18 #define SMP_MAGIC_IDENT ('_'<<24)|('P'<<16)|('M'<<8)|'_'
  19 
  20 struct intel_mp_floating
  21 {
  22         char mpf_signature[4];          /* "_MP_"                       */
  23         unsigned long mpf_physptr;      /* Configuration table address  */
  24         unsigned char mpf_length;       /* Our length (paragraphs)      */
  25         unsigned char mpf_specification;/* Specification version        */
  26         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
  27         unsigned char mpf_feature1;     /* Standard or configuration ?  */
  28         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
  29         unsigned char mpf_feature3;     /* Unused (0)                   */
  30         unsigned char mpf_feature4;     /* Unused (0)                   */
  31         unsigned char mpf_feature5;     /* Unused (0)                   */
  32 };
  33 
  34 struct mp_config_table
  35 {
  36         char mpc_signature[4];
  37 #define MPC_SIGNATURE "PCMP"
  38         unsigned short mpc_length;      /* Size of table */
  39         char  mpc_spec;                 /* 0x01 */
  40         char  mpc_checksum;
  41         char  mpc_oem[8];
  42         char  mpc_productid[12];
  43         unsigned long mpc_oemptr;       /* 0 if not present */
  44         unsigned short mpc_oemsize;     /* 0 if not present */
  45         unsigned short mpc_oemcount;
  46         unsigned long mpc_lapic;        /* APIC address */
  47         unsigned long reserved;
  48 };
  49 
  50 /* Followed by entries */
  51 
  52 #define MP_PROCESSOR    0
  53 #define MP_BUS          1
  54 #define MP_IOAPIC       2
  55 #define MP_INTSRC       3
  56 #define MP_LINTSRC      4
  57 
  58 struct mpc_config_processor
  59 {
  60         unsigned char mpc_type;
  61         unsigned char mpc_apicid;       /* Local APIC number */
  62         unsigned char mpc_apicver;      /* Its versions */
  63         unsigned char mpc_cpuflag;
  64 #define CPU_ENABLED             1       /* Processor is available */
  65 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  66         unsigned long mpc_cpufeature;           
  67 #define CPU_STEPPING_MASK 0x0F
  68 #define CPU_MODEL_MASK  0xF0
  69 #define CPU_FAMILY_MASK 0xF00
  70         unsigned long mpc_featureflag;  /* CPUID feature value */
  71         unsigned long mpc_reserved[2];
  72 };
  73 
  74 struct mpc_config_bus
  75 {
  76         unsigned char mpc_type;
  77         unsigned char mpc_busid;
  78         unsigned char mpc_bustype[6] __attribute((packed));
  79 };
  80 
  81 #define BUSTYPE_EISA    "EISA"
  82 #define BUSTYPE_ISA     "ISA"
  83 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  84 #define BUSTYPE_MCA     "MCA"
  85 #define BUSTYPE_VL      "VL"            /* Local bus */
  86 #define BUSTYPE_PCI     "PCI"
  87 #define BUSTYPE_PCMCIA  "PCMCIA"
  88 
  89 /* We don't understand the others */
  90 
  91 struct mpc_config_ioapic
  92 {
  93         unsigned char mpc_type;
  94         unsigned char mpc_apicid;
  95         unsigned char mpc_apicver;
  96         unsigned char mpc_flags;
  97 #define MPC_APIC_USABLE         0x01
  98         unsigned long mpc_apicaddr;
  99 };
 100 
 101 struct mpc_config_intsrc
 102 {
 103         unsigned char mpc_type;
 104         unsigned char mpc_irqtype;
 105         unsigned short mpc_irqflag;
 106         unsigned char mpc_srcbus;
 107         unsigned char mpc_srcbusirq;
 108         unsigned char mpc_dstapic;
 109         unsigned char mpc_dstirq;
 110 };
 111 
 112 #define MP_INT_VECTORED         0
 113 #define MP_INT_NMI              1
 114 #define MP_INT_SMI              2
 115 #define MP_INT_EXTINT           3
 116 
 117 #define MP_IRQDIR_DEFAULT       0
 118 #define MP_IRQDIR_HIGH          1
 119 #define MP_IRQDIR_LOW           3
 120 
 121 
 122 struct mpc_config_intlocal
 123 {
 124         unsigned char mpc_type;
 125         unsigned char mpc_irqtype;
 126         unsigned short mpc_irqflag;
 127         unsigned char mpc_srcbusid;
 128         unsigned char mpc_srcbusirq;
 129         unsigned char mpc_destapic;     
 130 #define MP_APIC_ALL     0xFF
 131         unsigned char mpc_destapiclint;
 132 };
 133 
 134 
 135 /*
 136  *      Default configurations
 137  *
 138  *      1       2 CPU ISA 82489DX
 139  *      2       2 CPU EISA 82489DX no IRQ 8 or timer chaining
 140  *      3       2 CPU EISA 82489DX
 141  *      4       2 CPU MCA 82489DX
 142  *      5       2 CPU ISA+PCI
 143  *      6       2 CPU EISA+PCI
 144  *      7       2 CPU MCA+PCI
 145  */
 146 
 147 /*
 148  *      Per process x86 parameters
 149  */
 150  
 151 struct cpuinfo_x86
 152 {
 153         char hard_math;
 154         char x86;
 155         char x86_model;
 156         char x86_mask;
 157         char x86_vendor_id[16];
 158         int  x86_capability;
 159         int  fdiv_bug;
 160         char wp_works_ok;
 161         char hlt_works_ok;
 162         unsigned long udelay_val;
 163 };
 164 
 165 
 166 extern struct cpuinfo_x86 cpu_data[32];
 167 
 168 /*
 169  *      Private routines/data
 170  */
 171  
 172 extern void smp_scan_config(unsigned long, unsigned long);
 173 extern unsigned long smp_alloc_memory(unsigned long mem_base);
 174 extern unsigned char *apic_reg;
 175 extern unsigned char *kernel_stacks[32];
 176 extern unsigned char boot_cpu_id;
 177 extern unsigned long cpu_present_map;
 178 extern void smp_invalidate(void);
 179 extern volatile unsigned long kernel_flag, kernel_counter;
 180 extern volatile unsigned char active_kernel_processor;
 181 extern void smp_message_irq(int cpl, struct pt_regs *regs);
 182 extern void smp_reschedule_irq(int cpl, struct pt_regs *regs);
 183 extern unsigned long ipi_count;
 184 extern void smp_invalidate_rcv(void);           /* Process an NMI */
 185 extern volatile unsigned long kernel_counter;
 186 extern volatile unsigned long syscall_count;
 187 
 188 /*
 189  *      General functions that each host system must provide.
 190  */
 191  
 192 extern void smp_callin(void);
 193 extern void smp_boot_cpus(void);
 194 extern void smp_store_cpu_info(int id);         /* Store per cpu info (like the initial udelay numbers */
 195 
 196 /*
 197  *      APIC handlers: Note according to the Intel specification update
 198  *      you should put reads between APIC writes.
 199  *      Intel Pentium processor specification update [11AP, pg 64]
 200  *              "Back to Back Assertions of HOLD May Cause Lost APIC Write Cycle"
 201  */
 202 
 203 extern __inline void apic_write(unsigned long reg, unsigned long v)
     /*  */
 204 {
 205         *((unsigned long *)(apic_reg+reg))=v;
 206 }
 207 
 208 extern __inline unsigned long apic_read(unsigned long reg)
     /*  */
 209 {
 210         return *((unsigned long *)(apic_reg+reg));
 211 }
 212 
 213 /*
 214  *      This function is needed by all SMP systems. It must _always_ be valid from the initial
 215  *      startup. This may require magic on some systems (in the i86 case we dig out the boot 
 216  *      cpu id from the config and set up a fake apic_reg pointer so that before we activate
 217  *      the apic we get the right answer). Hopefully other processors are more sensible 8)
 218  */
 219  
 220 extern __inline int smp_processor_id(void)
     /*  */
 221 {
 222         return GET_APIC_ID(apic_read(APIC_ID));
 223 }
 224 
 225 #endif /* !ASSEMBLY */
 226 
 227 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 228 
 229 #endif
/* */
root/include/asm-i386/smp.h

INCLUDED FROM

DEFINITIONS
