root/include/asm-mips/stackframe.h

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INCLUDED FROM

   1 /*
   2  *  include/asm-mips/stackframe.h
   3  *
   4  *  Copyright (C) 1994, 1995 Waldorf Electronics
   5  *  written by Ralf Baechle
   6  */
   7 
   8 #ifndef __ASM_MIPS_STACKFRAME_H
   9 #define __ASM_MIPS_STACKFRAME_H
  10 
  11 /*
  12  * Stack layout for all exceptions:
  13  *
  14  * ptrace needs to have all regs on the stack.
  15  * if the order here is changed, it needs to be 
  16  * updated in asm/mips/fork.c:copy_process, asm/mips/signal.c:do_signal,
  17  * asm-mips/ptrace.c, include/asm-mips/ptrace.h
  18  * and asm-mips/ptrace
  19  */
  20 
  21 /*
  22  * Offsets into the Interrupt stackframe.
  23  * The first 20 bytes are reserved for the usual MIPS calling sequence
  24  */
  25 #define FR_REG1         20
  26 #define FR_REG2         ((FR_REG1) + 4)
  27 #define FR_REG3         ((FR_REG2) + 4)
  28 #define FR_REG4         ((FR_REG3) + 4)
  29 #define FR_REG5         ((FR_REG4) + 4)
  30 #define FR_REG6         ((FR_REG5) + 4)
  31 #define FR_REG7         ((FR_REG6) + 4)
  32 #define FR_REG8         ((FR_REG7) + 4)
  33 #define FR_REG9         ((FR_REG8) + 4)
  34 #define FR_REG10        ((FR_REG9) + 4)
  35 #define FR_REG11        ((FR_REG10) + 4)
  36 #define FR_REG12        ((FR_REG11) + 4)
  37 #define FR_REG13        ((FR_REG12) + 4)
  38 #define FR_REG14        ((FR_REG13) + 4)
  39 #define FR_REG15        ((FR_REG14) + 4)
  40 #define FR_REG16        ((FR_REG15) + 4)
  41 #define FR_REG17        ((FR_REG16) + 4)
  42 #define FR_REG18        ((FR_REG17) + 4)
  43 #define FR_REG19        ((FR_REG18) + 4)
  44 #define FR_REG20        ((FR_REG19) + 4)
  45 #define FR_REG21        ((FR_REG20) + 4)
  46 #define FR_REG22        ((FR_REG21) + 4)
  47 #define FR_REG23        ((FR_REG22) + 4)
  48 #define FR_REG24        ((FR_REG23) + 4)
  49 #define FR_REG25        ((FR_REG24) + 4)
  50 
  51 /*
  52  * $26 (k0) and $27 (k1) not saved
  53  */
  54 #define FR_REG28        ((FR_REG25) + 4)
  55 #define FR_REG29        ((FR_REG28) + 4)
  56 #define FR_REG30        ((FR_REG29) + 4)
  57 #define FR_REG31        ((FR_REG30) + 4)
  58 
  59 /*
  60  * Saved special registers
  61  */
  62 #define FR_LO           ((FR_REG31) + 4)
  63 #define FR_HI           ((FR_LO) + 4)
  64 
  65 /*
  66  * Saved cp0 registers follow
  67  */
  68 #define FR_STATUS       ((FR_HI) + 4)
  69 #define FR_EPC          ((FR_STATUS) + 4)
  70 #define FR_CAUSE        ((FR_EPC) + 4)
  71 
  72 /*
  73  * Some goodies...
  74  */
  75 #define FR_INTERRUPT    ((FR_CAUSE) + 4)
  76 #define FR_ORIG_REG2    ((FR_INTERRUPT) + 4)
  77 
  78 /*
  79  * Size of stack frame
  80  */
  81 #define FR_SIZE         ((FR_ORIG_REG2) + 4)
  82 
  83 #define SAVE_ALL                                \
  84                 mfc0    k0,CP0_STATUS;          \
  85                 andi    k0,0x18;                /* extract KSU bits */ \
  86                 beqz    k0,1f;                  \
  87                 move    k1,sp;                  \
  88                 /*                              \
  89                  * Called from user mode, new stack \
  90                  */                             \
  91                 lui     k1,%hi(_kernelsp);      \
  92                 lw      k1,%lo(_kernelsp)(k1);  \
  93 1:              move    k0,sp;                  \
  94                 subu    sp,k1,FR_SIZE;          \
  95                 sw      k0,FR_REG29(sp);        \
  96                 sw      $2,FR_REG2(sp);         \
  97                 sw      $2,FR_ORIG_REG2(sp);    \
  98                 mfc0    v0,CP0_STATUS;          \
  99                 sw      v0,FR_STATUS(sp);       \
 100                 mfc0    v0,CP0_CAUSE;           \
 101                 sw      v0,FR_CAUSE(sp);        \
 102                 mfc0    v0,CP0_EPC;             \
 103                 sw      v0,FR_EPC(sp);          \
 104                 mfhi    v0;                     \
 105                 sw      v0,FR_HI(sp);           \
 106                 mflo    v0;                     \
 107                 sw      v0,FR_LO(sp);           \
 108                 sw      $1,FR_REG1(sp);         \
 109                 sw      $3,FR_REG3(sp);         \
 110                 sw      $4,FR_REG4(sp);         \
 111                 sw      $5,FR_REG5(sp);         \
 112                 sw      $6,FR_REG6(sp);         \
 113                 sw      $7,FR_REG7(sp);         \
 114                 sw      $8,FR_REG8(sp);         \
 115                 sw      $9,FR_REG9(sp);         \
 116                 sw      $10,FR_REG10(sp);       \
 117                 sw      $11,FR_REG11(sp);       \
 118                 sw      $12,FR_REG12(sp);       \
 119                 sw      $13,FR_REG13(sp);       \
 120                 sw      $14,FR_REG14(sp);       \
 121                 sw      $15,FR_REG15(sp);       \
 122                 sw      $16,FR_REG16(sp);       \
 123                 sw      $17,FR_REG17(sp);       \
 124                 sw      $18,FR_REG18(sp);       \
 125                 sw      $19,FR_REG19(sp);       \
 126                 sw      $20,FR_REG20(sp);       \
 127                 sw      $21,FR_REG21(sp);       \
 128                 sw      $22,FR_REG22(sp);       \
 129                 sw      $23,FR_REG23(sp);       \
 130                 sw      $24,FR_REG24(sp);       \
 131                 sw      $25,FR_REG25(sp);       \
 132                 sw      $28,FR_REG28(sp);       \
 133                 sw      $30,FR_REG30(sp);       \
 134                 sw      $31,FR_REG31(sp)
 135 
 136 #define RESTORE_ALL                             \
 137                 lw      v1,FR_EPC(sp);          \
 138                 lw      v0,FR_HI(sp);           \
 139                 mtc0    v1,CP0_EPC;             \
 140                 lw      v1,FR_LO(sp);           \
 141                 mthi    v0;                     \
 142                 lw      v0,FR_STATUS(sp);       \
 143                 mtlo    v1;                     \
 144                 mtc0    v0,CP0_STATUS;          \
 145                 lw      $31,FR_REG31(sp);       \
 146                 lw      $30,FR_REG30(sp);       \
 147                 lw      $28,FR_REG28(sp);       \
 148                 lw      $25,FR_REG25(sp);       \
 149                 lw      $24,FR_REG24(sp);       \
 150                 lw      $23,FR_REG23(sp);       \
 151                 lw      $22,FR_REG22(sp);       \
 152                 lw      $21,FR_REG21(sp);       \
 153                 lw      $20,FR_REG20(sp);       \
 154                 lw      $19,FR_REG19(sp);       \
 155                 lw      $18,FR_REG18(sp);       \
 156                 lw      $17,FR_REG17(sp);       \
 157                 lw      $16,FR_REG16(sp);       \
 158                 lw      $15,FR_REG15(sp);       \
 159                 lw      $14,FR_REG14(sp);       \
 160                 lw      $13,FR_REG13(sp);       \
 161                 lw      $12,FR_REG12(sp);       \
 162                 lw      $11,FR_REG11(sp);       \
 163                 lw      $10,FR_REG10(sp);       \
 164                 lw      $9,FR_REG9(sp);         \
 165                 lw      $8,FR_REG8(sp);         \
 166                 lw      $7,FR_REG7(sp);         \
 167                 lw      $6,FR_REG6(sp);         \
 168                 lw      $5,FR_REG5(sp);         \
 169                 lw      $4,FR_REG4(sp);         \
 170                 lw      $3,FR_REG3(sp);         \
 171                 lw      $2,FR_REG2(sp);         \
 172                 lw      $1,FR_REG1(sp);         \
 173                 lw      sp,FR_REG29(sp); /* Deallocate stack */ \
 174                 eret
 175 
 176 /*
 177  * Move to kernel mode and disable interrupts
 178  */
 179 #define CLI                                     \
 180                 mfc0    k0,CP0_STATUS;          \
 181                 ori     k0,k0,0x1f;             \
 182                 xori    k0,k0,0x1f;             \
 183                 mtc0    k0,CP0_STATUS
 184 
 185 /*
 186  * Move to kernel mode and enable interrupts
 187  */
 188 #define STI                                     \
 189                 mfc0    k0,CP0_STATUS;          \
 190                 ori     k0,k0,0x1f;             \
 191                 xori    k0,k0,0x1e;             \
 192                 mtc0    k0,CP0_STATUS
 193 
 194 #endif /* __ASM_MIPS_STACKFRAME_H */
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