This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129 static const char *version = "ewrk3.c:v0.32 1/16/95 davies@wanton.lkg.dec.com\n";
130
131 #ifdef MODULE
132 #include <linux/module.h>
133 #include <linux/version.h>
134 #endif
135
136 #include <stdarg.h>
137 #include <linux/kernel.h>
138 #include <linux/sched.h>
139 #include <linux/string.h>
140 #include <linux/ptrace.h>
141 #include <linux/errno.h>
142 #include <linux/ioport.h>
143 #include <linux/malloc.h>
144 #include <linux/interrupt.h>
145 #include <asm/bitops.h>
146 #include <asm/io.h>
147 #include <asm/dma.h>
148 #include <asm/segment.h>
149
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/skbuff.h>
153
154 #include <linux/time.h>
155 #include <linux/types.h>
156 #include <linux/unistd.h>
157
158 #include "ewrk3.h"
159
160 #ifdef EWRK3_DEBUG
161 static int ewrk3_debug = EWRK3_DEBUG;
162 #else
163 static int ewrk3_debug = 1;
164 #endif
165
166 #ifndef PROBE_LENGTH
167 #define PROBE_LENGTH 32
168 #endif
169
170 #ifndef PROBE_SEQUENCE
171 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
172 #endif
173
174 #ifndef EWRK3_SIGNATURE
175 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
176 #define EWRK3_NAME_LENGTH 8
177 #endif
178
179 #ifndef EWRK3_RAM_BASE_ADDRESSES
180 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
181 #endif
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197 #define EWRK3_IO_BASE 0x100
198 #define EWRK3_IOP_INC 0x20
199 #define EWRK3_TOTAL_SIZE 0x20
200 #define EWRK3_IO_SEARCH 0x007dff7f
201 static long mem_chkd = EWRK3_IO_SEARCH;
202
203
204 #ifndef MAX_NUM_EWRK3S
205 #define MAX_NUM_EWRK3S 21
206 #endif
207
208 #ifndef EWRK3_EISA_IO_PORTS
209 #define EWRK3_EISA_IO_PORTS 0x0c00
210 #endif
211
212 #ifndef MAX_EISA_SLOTS
213 #define MAX_EISA_SLOTS 8
214 #define EISA_SLOT_INC 0x1000
215 #endif
216
217 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
218 #define CRC_POLYNOMIAL_LE 0xedb88320UL
219
220
221
222
223 #define IO_ONLY 0x00
224 #define SHMEM_2K 0x800
225 #define SHMEM_32K 0x8000
226 #define SHMEM_64K 0x10000
227
228
229
230
231 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
232
233 #define ENABLE_IRQs \
234 icr |= irq_mask;\
235 outb(icr, EWRK3_ICR)
236
237 #define DISABLE_IRQs \
238 icr = inb(EWRK3_ICR);\
239 icr &= ~irq_mask;\
240 outb(icr, EWRK3_ICR)
241
242
243
244
245 #define START_EWRK3 \
246 csr = inb(EWRK3_CSR);\
247 csr &= ~(TXD|RXD);\
248 outb(csr, EWRK3_CSR)
249
250 #define STOP_EWRK3 \
251 csr = (TXD|RXD);\
252 outb(csr, EWRK3_CSR)
253
254
255
256
257 #define EWRK3_PKT_STAT_SZ 16
258 #define EWRK3_PKT_BIN_SZ 128
259
260
261 struct ewrk3_private {
262 long shmem_base;
263 long shmem_length;
264 struct enet_statistics stats;
265 struct {
266 unsigned long bins[EWRK3_PKT_STAT_SZ];
267 unsigned long unicast;
268 unsigned long multicast;
269 unsigned long broadcast;
270 unsigned long excessive_collisions;
271 unsigned long tx_underruns;
272 unsigned long excessive_underruns;
273 } pktStats;
274 short mPage;
275 unsigned char lemac;
276 unsigned char hard_strapped;
277 unsigned char lock;
278 unsigned char txc;
279 };
280
281
282
283
284 #define FORCE_2K_MODE \
285 shmem_length = SHMEM_2K;\
286 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
287
288
289
290
291 static int ewrk3_open(struct device *dev);
292 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
293 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
294 static int ewrk3_close(struct device *dev);
295 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
296 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
297 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
298
299
300
301
302 static int ewrk3_hw_init(struct device *dev, short iobase);
303 static void ewrk3_init(struct device *dev);
304 static int ewrk3_rx(struct device *dev);
305 static int ewrk3_tx(struct device *dev);
306
307 static void EthwrkSignature(char * name, char *eeprom_image);
308 static int DevicePresent(short iobase);
309 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
310
311 static int Read_EEPROM(short iobase, unsigned char eaddr);
312 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
313 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
314
315 #ifndef MODULE
316 static struct device *isa_probe(struct device *dev);
317 static struct device *eisa_probe(struct device *dev);
318 static struct device *alloc_device(struct device *dev, int iobase);
319
320 static int num_ewrk3s = 0, num_eth = 0;
321 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
322
323 #else
324 int init_module(void);
325 void cleanup_module(void);
326
327 #endif
328
329 static int autoprobed = 0;
330
331
332
333
334 #define INIT_EWRK3 {\
335 int i;\
336 outb(EEPROM_INIT, EWRK3_IOPR);\
337 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
338 }
339
340
341
342
343 int ewrk3_probe(struct device *dev)
344 {
345 int base_addr = dev->base_addr;
346 int status = -ENODEV;
347 #ifndef MODULE
348 struct device *eth0;
349 #endif
350
351 if (base_addr > 0x0ff) {
352 if (!autoprobed) {
353 if (!check_region(base_addr, EWRK3_TOTAL_SIZE)) {
354 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
355 if (DevicePresent(base_addr) == 0) {
356
357 request_region(base_addr, EWRK3_IOP_INC, "ewrk3");
358 status = ewrk3_hw_init(dev, base_addr);
359 } else {
360 printk("ewrk3_probe(): No device found\n");
361 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
362 }
363 }
364 } else {
365 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
366 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
367 }
368 } else {
369 status = ewrk3_hw_init(dev, base_addr);
370 }
371 } else if (base_addr > 0) {
372 status = -ENXIO;
373
374 #ifdef MODULE
375 } else {
376 printk("Autoprobing is not supported when loading a module based driver.\n");
377 status = -EIO;
378 #else
379 } else if (!autoprobed) {
380
381 eth0=isa_probe(dev);
382 eth0=eisa_probe(eth0);
383 if (dev->priv) status=0;
384 autoprobed = 1;
385 } else {
386 status = -ENXIO;
387 #endif
388
389 }
390
391 if (status) dev->base_addr = base_addr;
392
393 return status;
394 }
395
396 static int
397 ewrk3_hw_init(struct device *dev, short iobase)
398 {
399 struct ewrk3_private *lp;
400 int i, status=0;
401 unsigned long mem_start, shmem_length;
402 char name[EWRK3_NAME_LENGTH + 1];
403 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
404 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
405
406
407
408
409
410 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
411 INIT_EWRK3;
412
413 nicsr = inb(EWRK3_CSR);
414
415
416
417
418 DISABLE_IRQs;
419
420 if (nicsr == TXD|RXD) {
421
422
423
424
425 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
426 union {
427 short val;
428 char c[2];
429 } tmp;
430
431 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
432 eeprom_image[i] = tmp.c[0];
433 eeprom_image[i+1] = tmp.c[1];
434
435 chksum += eeprom_image[i] + eeprom_image[i+1];
436 }
437
438 if (chksum != 0) {
439 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
440 status = -ENXIO;
441 } else {
442
443
444
445 EthwrkSignature(name, eeprom_image);
446
447 if (*name != '\0') {
448 dev->base_addr = iobase;
449
450 if (iobase > 0x400) {
451 outb(eisa_cr, EISA_CR);
452 }
453
454 lemac = eeprom_image[EEPROM_CHIPVER];
455 cmr = inb(EWRK3_CMR);
456
457 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
458 ((lemac == LeMAC2) && !(cmr & HS))) {
459 printk("%s: %s at %#3x", dev->name, name, iobase);
460 hard_strapped = 1;
461 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
462
463 printk("%s: %s at %#3x (EISA slot %d)",
464 dev->name, name, iobase, ((iobase>>12)&0x0f));
465 } else {
466 printk("%s: %s at %#3x", dev->name, name, iobase);
467 }
468
469 if (!status) {
470 printk(", h/w address ");
471 if (lemac == LeMAC2) {
472 for (i = 0;i < ETH_ALEN - 1;i++) {
473 printk("%2.2x:", dev->dev_addr[i] =
474 eeprom_image[EEPROM_PADDR0 + i]);
475 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
476 }
477 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
478 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
479 } else {
480 DevicePresent(iobase);
481 for (i = 0; i < ETH_ALEN - 1; i++) {
482 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
483 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
484 }
485 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
486 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
487 }
488
489 if (aprom_crc(dev, eeprom_image, lemac)) {
490 printk(" which has an EEPROM CRC error.\n");
491 status = -ENXIO;
492 } else {
493 if (lemac == LeMAC2) {
494 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
495 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
496 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
497 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
498 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
499 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
500 }
501 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
502 outb(cmr, EWRK3_CMR);
503
504 cr = inb(EWRK3_CR);
505 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
506 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
507 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
508 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
509 outb(cr, EWRK3_CR);
510
511
512
513
514
515 mem_start = inb(EWRK3_MBR);
516 shmem_length = 0;
517 if (mem_start != 0) {
518 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
519 mem_start *= SHMEM_64K;
520 shmem_length = SHMEM_64K;
521 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
522 mem_start *= SHMEM_32K;
523 shmem_length = SHMEM_32K;
524 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
525 mem_start = mem_start * SHMEM_2K + 0x80000;
526 shmem_length = SHMEM_2K;
527 } else {
528 status = -ENXIO;
529 }
530 }
531
532
533
534
535
536
537
538 if (!status) {
539 if (hard_strapped) {
540 printk(" is hard strapped.\n");
541 } else if (mem_start) {
542 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
543 printk(" at 0x%.5lx", mem_start);
544 } else {
545 printk(" is in I/O only mode");
546 }
547
548
549 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
550 GFP_KERNEL);
551 if (dev->priv == NULL)
552 return -ENOMEM;
553 lp = (struct ewrk3_private *)dev->priv;
554 memset(dev->priv, 0, sizeof(struct ewrk3_private));
555 lp->shmem_base = mem_start;
556 lp->shmem_length = shmem_length;
557 lp->lemac = lemac;
558 lp->hard_strapped = hard_strapped;
559
560 lp->mPage = 64;
561 if (cmr & DRAM) lp->mPage <<= 1 ;
562
563 if (!hard_strapped) {
564
565
566
567 icr |= IE;
568 outb(icr, EWRK3_ICR);
569
570
571 dev->dma = 0;
572
573
574
575 if (dev->irq < 2) {
576 #ifndef MODULE
577 unsigned char irqnum;
578
579 autoirq_setup(0);
580
581
582
583
584 icr |=TNEM;
585 outb(1,EWRK3_TDQ);
586 outb(icr, EWRK3_ICR);
587
588 irqnum = irq[((icr & IRQ_SEL) >> 4)];
589
590 dev->irq = autoirq_report(1);
591 if ((dev->irq) && (irqnum == dev->irq)) {
592 printk(" and uses IRQ%d.\n", dev->irq);
593 } else {
594 if (!dev->irq) {
595 printk(" and failed to detect IRQ line.\n");
596 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
597 printk(" and an illegal IRQ line detected.\n");
598 } else {
599 printk(", but incorrect IRQ line detected.\n");
600 }
601 status = -ENXIO;
602 }
603
604 DISABLE_IRQs;
605
606 #endif
607 } else {
608 printk(" and requires IRQ%d.\n", dev->irq);
609 }
610 }
611 } else {
612 status = -ENXIO;
613 }
614 }
615 }
616 } else {
617 status = -ENXIO;
618 }
619 }
620
621 if (!status) {
622 if (ewrk3_debug > 0) {
623 printk(version);
624 }
625
626
627 dev->open = &ewrk3_open;
628 dev->hard_start_xmit = &ewrk3_queue_pkt;
629 dev->stop = &ewrk3_close;
630 dev->get_stats = &ewrk3_get_stats;
631 #ifdef HAVE_MULTICAST
632 dev->set_multicast_list = &set_multicast_list;
633 #endif
634 dev->do_ioctl = &ewrk3_ioctl;
635
636 dev->mem_start = 0;
637
638
639 ether_setup(dev);
640 }
641 } else {
642 status = -ENXIO;
643 }
644
645 return status;
646 }
647
648
649 static int
650 ewrk3_open(struct device *dev)
651 {
652 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
653 int i, iobase = dev->base_addr;
654 int status = 0;
655 unsigned char icr, csr;
656
657
658
659
660 STOP_EWRK3;
661
662 if (!lp->hard_strapped) {
663 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
664 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
665 status = -EAGAIN;
666 } else {
667
668 irq2dev_map[dev->irq] = dev;
669
670
671
672
673 ewrk3_init(dev);
674
675 if (ewrk3_debug > 1){
676 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
677 printk("\tphysical address: ");
678 for (i=0;i<6;i++){
679 printk("%2.2x:",(short)dev->dev_addr[i]);
680 }
681 printk("\n");
682 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
683 if (lp->shmem_length == 0) {
684 printk("\tno shared memory, I/O only mode\n");
685 } else {
686 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
687 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
688 }
689 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
690 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
691 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
692 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
693 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
694 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
695 }
696
697 dev->tbusy = 0;
698 dev->start = 1;
699 dev->interrupt = UNMASK_INTERRUPTS;
700
701
702
703
704 icr = inb(EWRK3_ICR);
705 ENABLE_IRQs;
706
707 }
708 } else {
709 dev->start = 0;
710 dev->tbusy = 1;
711 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
712 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
713 }
714
715 #ifdef MODULE
716 MOD_INC_USE_COUNT;
717 #endif
718
719
720 return status;
721 }
722
723
724
725
726 static void
727 ewrk3_init(struct device *dev)
728 {
729 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
730 char csr, page;
731 short iobase = dev->base_addr;
732
733
734
735
736 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
737
738
739
740
741 while (inb(EWRK3_TQ));
742 while (inb(EWRK3_TDQ));
743 while (inb(EWRK3_RQ));
744 while (inb(EWRK3_FMQ));
745
746
747
748
749 for (page=1;page<lp->mPage;page++) {
750 outb(page, EWRK3_FMQ);
751 }
752
753 lp->lock = 0;
754
755 START_EWRK3;
756 }
757
758
759
760
761 static int
762 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
763 {
764 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
765 int iobase = dev->base_addr;
766 int status = 0;
767 unsigned char icr, csr;
768
769
770 if (dev->tbusy || lp->lock) {
771 int tickssofar = jiffies - dev->trans_start;
772 if (tickssofar < 10) {
773 status = -1;
774 } else if (!lp->hard_strapped) {
775 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
776 dev->name, inb(EWRK3_CSR));
777
778
779
780
781 DISABLE_IRQs;
782
783
784
785
786 STOP_EWRK3;
787
788 ewrk3_init(dev);
789
790
791
792
793 ENABLE_IRQs;
794
795 dev->tbusy=0;
796 dev->trans_start = jiffies;
797 }
798 } else if (skb == NULL) {
799 dev_tint(dev);
800 } else if (skb->len > 0) {
801
802
803
804
805
806 if (set_bit(0, (void*)&dev->tbusy) != 0)
807 printk("%s: Transmitter access conflict.\n", dev->name);
808
809 DISABLE_IRQs;
810
811
812
813
814 if (inb(EWRK3_FMQC) > 0) {
815 unsigned char *buf;
816 unsigned char page;
817
818 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
819 buf = NULL;
820
821
822
823
824 while (set_bit(0, (void *)&lp->lock) != 0);
825 if (lp->shmem_length == IO_ONLY) {
826 outb(page, EWRK3_IOPR);
827 } else if (lp->shmem_length == SHMEM_2K) {
828 buf = (char *) lp->shmem_base;
829 outb(page, EWRK3_MPR);
830 } else if (lp->shmem_length == SHMEM_32K) {
831 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
832 outb((page >> 4), EWRK3_MPR);
833 } else if (lp->shmem_length == SHMEM_64K) {
834 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
835 outb((page >> 5), EWRK3_MPR);
836 } else {
837 status = -1;
838 printk("%s: Oops - your private data area is hosed!\n",dev->name);
839 }
840
841 if (!status) {
842
843
844
845
846
847
848 if (lp->shmem_length == IO_ONLY) {
849 int i;
850 unsigned char *p = skb->data;
851
852 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
853 outb((char)(skb->len & 0xff), EWRK3_DATA);
854 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
855 outb((char)0x04, EWRK3_DATA);
856 for (i=0; i<skb->len; i++) {
857 outb(*p++, EWRK3_DATA);
858 }
859 outb(page, EWRK3_TQ);
860 } else {
861 *buf++ = (char)(QMODE | PAD | IFC);
862 *buf++ = (char)(skb->len & 0xff);
863 if (lp->txc) {
864 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
865 *buf++ = 0x04;
866 *(buf + skb->len) = 0x00;
867 memcpy(buf, skb->data, PRELOAD);
868 outb(page, EWRK3_TQ);
869 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
870 *(buf + skb->len) = 0xff;
871 } else {
872 *buf++ = (char)((skb->len >> 8) & 0xff);
873 *buf++ = 0x04;
874 memcpy(buf, skb->data, skb->len);
875 outb(page, EWRK3_TQ);
876 }
877 }
878
879 dev->trans_start = jiffies;
880
881 dev_kfree_skb (skb, FREE_WRITE);
882
883 } else {
884 outb(page, EWRK3_FMQ);
885 }
886 lp->lock = 0;
887 } else {
888 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
889 (unsigned char) page);
890 }
891 } else {
892 printk("ewrk3_queue_pkt(): No free resources...\n");
893 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
894 }
895
896
897 if (inb(EWRK3_FMQC) > 0) {
898 dev->tbusy = 0;
899 }
900
901 ENABLE_IRQs;
902 }
903
904 return status;
905 }
906
907
908
909
910 static void
911 ewrk3_interrupt(int irq, struct pt_regs * regs)
912 {
913 struct device *dev = (struct device *)(irq2dev_map[irq]);
914 struct ewrk3_private *lp;
915 int iobase;
916 unsigned char icr, cr, csr;
917
918 if (dev == NULL) {
919 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
920 } else {
921 lp = (struct ewrk3_private *)dev->priv;
922 iobase = dev->base_addr;
923
924 if (dev->interrupt)
925 printk("%s: Re-entering the interrupt handler.\n", dev->name);
926
927 dev->interrupt = MASK_INTERRUPTS;
928
929
930 csr = inb(EWRK3_CSR);
931
932
933
934
935 DISABLE_IRQs;
936
937 cr = inb(EWRK3_CR);
938 cr |= LED;
939 outb(cr, EWRK3_CR);
940
941 if (csr & RNE)
942 ewrk3_rx(dev);
943
944 if (csr & TNE)
945 ewrk3_tx(dev);
946
947
948
949
950
951
952
953 if (inb(EWRK3_FMQC)) {
954 irq_mask |= TXDM|RXDM;
955 csr &= ~(TXD|RXD);
956 outb(csr, EWRK3_CSR);
957 dev->tbusy = 0;
958 mark_bh(NET_BH);
959 } else {
960 irq_mask &= ~(TXDM|RXDM);
961 }
962
963
964 cr &= ~LED;
965 outb(cr, EWRK3_CR);
966
967 dev->interrupt = UNMASK_INTERRUPTS;
968
969 ENABLE_IRQs;
970 }
971
972 return;
973 }
974
975 static int
976 ewrk3_rx(struct device *dev)
977 {
978 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
979 int i, iobase = dev->base_addr;
980 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
981 int status = 0;
982
983 while (inb(EWRK3_RQC) && !status) {
984 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
985 buf = NULL;
986
987
988
989
990
991 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
992 if (lp->shmem_length == IO_ONLY) {
993 tmpPage = inb(EWRK3_IOPR);
994 } else {
995 tmpPage = inb(EWRK3_MPR);
996 }
997 }
998
999
1000
1001
1002 if (lp->shmem_length == IO_ONLY) {
1003 outb(page, EWRK3_IOPR);
1004 } else if (lp->shmem_length == SHMEM_2K) {
1005 buf = (char *) lp->shmem_base;
1006 outb(page, EWRK3_MPR);
1007 } else if (lp->shmem_length == SHMEM_32K) {
1008 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1009 outb((page >> 4), EWRK3_MPR);
1010 } else if (lp->shmem_length == SHMEM_64K) {
1011 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1012 outb((page >> 5), EWRK3_MPR);
1013 } else {
1014 status = -1;
1015 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1016 }
1017
1018 if (!status) {
1019 char rx_status;
1020 int pkt_len;
1021
1022 if (lp->shmem_length == IO_ONLY) {
1023 rx_status = inb(EWRK3_DATA);
1024 pkt_len = inb(EWRK3_DATA);
1025 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1026 } else {
1027 rx_status = (char)(*buf++);
1028 pkt_len = (short)(*buf+((*(buf+1))<<8));
1029 buf+=3;
1030 }
1031
1032 if (!(rx_status & ROK)) {
1033 lp->stats.rx_errors++;
1034 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1035 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1036 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1037 } else {
1038 struct sk_buff *skb;
1039
1040 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1041 unsigned char *p;
1042 skb->dev = dev;
1043 skb_reserve(skb,2);
1044 p = skb_put(skb,pkt_len);
1045
1046 if (lp->shmem_length == IO_ONLY) {
1047 *p = inb(EWRK3_DATA);
1048 for (i=0; i<pkt_len; i++) {
1049 *p++ = inb(EWRK3_DATA);
1050 }
1051 } else {
1052 memcpy(p, buf, pkt_len);
1053 }
1054
1055
1056
1057
1058
1059
1060 skb->protocol=eth_type_trans(skb,dev);
1061 netif_rx(skb);
1062
1063
1064
1065
1066 lp->stats.rx_packets++;
1067 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1068 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1069 lp->pktStats.bins[i]++;
1070 i = EWRK3_PKT_STAT_SZ;
1071 }
1072 }
1073 buf = skb->data;
1074 if (buf[0] & 0x01) {
1075 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1076 lp->pktStats.broadcast++;
1077 } else {
1078 lp->pktStats.multicast++;
1079 }
1080 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1081 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1082 lp->pktStats.unicast++;
1083 }
1084
1085 lp->pktStats.bins[0]++;
1086 if (lp->pktStats.bins[0] == 0) {
1087 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1088 }
1089 } else {
1090 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1091 lp->stats.rx_dropped++;
1092 break;
1093 }
1094 }
1095 }
1096
1097
1098
1099 outb(page, EWRK3_FMQ);
1100
1101 if (tmpLock) {
1102 if (lp->shmem_length == IO_ONLY) {
1103 outb(tmpPage, EWRK3_IOPR);
1104 } else {
1105 outb(tmpPage, EWRK3_MPR);
1106 }
1107 }
1108 lp->lock = 0;
1109 } else {
1110 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1111 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1112 }
1113 }
1114 return status;
1115 }
1116
1117
1118
1119
1120 static int
1121 ewrk3_tx(struct device *dev)
1122 {
1123 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1124 int iobase = dev->base_addr;
1125 unsigned char tx_status;
1126
1127 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1128 if (tx_status & VSTS) {
1129 if (tx_status & MAC_TXE) {
1130 lp->stats.tx_errors++;
1131 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1132 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1133 if (tx_status & MAC_CTU) {
1134 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1135 lp->pktStats.tx_underruns++;
1136 } else {
1137 lp->pktStats.excessive_underruns++;
1138 }
1139 } else if (tx_status & MAC_COLL) {
1140 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1141 lp->stats.collisions++;
1142 } else {
1143 lp->pktStats.excessive_collisions++;
1144 }
1145 }
1146 } else {
1147 lp->stats.tx_packets++;
1148 }
1149 }
1150 }
1151
1152 return 0;
1153 }
1154
1155 static int
1156 ewrk3_close(struct device *dev)
1157 {
1158 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1159 int iobase = dev->base_addr;
1160 unsigned char icr, csr;
1161
1162 dev->start = 0;
1163 dev->tbusy = 1;
1164
1165 if (ewrk3_debug > 1) {
1166 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1167 dev->name, inb(EWRK3_CSR));
1168 }
1169
1170
1171
1172
1173 DISABLE_IRQs;
1174
1175 STOP_EWRK3;
1176
1177
1178
1179
1180
1181
1182
1183 while (inb(EWRK3_TQ));
1184 while (inb(EWRK3_TDQ));
1185 while (inb(EWRK3_RQ));
1186
1187 if (!lp->hard_strapped) {
1188 free_irq(dev->irq);
1189
1190 irq2dev_map[dev->irq] = 0;
1191 }
1192
1193 #ifdef MODULE
1194 MOD_DEC_USE_COUNT;
1195 #endif
1196
1197 return 0;
1198 }
1199
1200 static struct enet_statistics *
1201 ewrk3_get_stats(struct device *dev)
1202 {
1203 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1204
1205
1206
1207 return &lp->stats;
1208 }
1209
1210
1211
1212
1213
1214
1215
1216
1217 static void
1218 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1219 {
1220 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1221 int iobase = dev->base_addr;
1222 char *multicast_table;
1223 unsigned char csr;
1224
1225 csr = inb(EWRK3_CSR);
1226
1227 if (lp->shmem_length == IO_ONLY) {
1228 multicast_table = (char *) PAGE0_HTE;
1229 } else {
1230 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1231 }
1232
1233 if (num_addrs >= 0) {
1234 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1235 csr &= ~PME;
1236 csr |= MCE;
1237 outb(csr, EWRK3_CSR);
1238 } else {
1239 csr |= PME;
1240 csr &= ~MCE;
1241 outb(csr, EWRK3_CSR);
1242 }
1243 }
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1254 {
1255 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1256 int i, iobase = dev->base_addr;
1257 char j, bit, byte;
1258 short *p = (short *) multicast_table;
1259 u_short hashcode;
1260 u_long crc, poly = CRC_POLYNOMIAL_LE;
1261
1262 while (set_bit(0, (void *)&lp->lock) != 0);
1263
1264 if (lp->shmem_length == IO_ONLY) {
1265 outb(0, EWRK3_IOPR);
1266 outw((short)((long)multicast_table), EWRK3_PIR1);
1267 } else {
1268 outb(0, EWRK3_MPR);
1269 }
1270
1271 if (num_addrs == HASH_TABLE_LEN) {
1272 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1273 if (lp->shmem_length == IO_ONLY) {
1274 outb(0xff, EWRK3_DATA);
1275 } else {
1276 *p++ = 0xffff;
1277 i++;
1278 }
1279 }
1280 } else {
1281
1282 if (lp->shmem_length == IO_ONLY) {
1283 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1284 outb(0x00, EWRK3_DATA);
1285 }
1286 outb(0x80, EWRK3_DATA); i++;
1287 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1288 outb(0x00, EWRK3_DATA);
1289 }
1290 } else {
1291 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1292 *(multicast_table + (HASH_TABLE_LEN >> 4) - 1) = 0x80;
1293 }
1294
1295
1296 for (i=0;i<num_addrs;i++) {
1297 if ((*addrs & 0x01) == 1) {
1298 crc = 0xffffffff;
1299 for (byte=0;byte<ETH_ALEN;byte++) {
1300
1301 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1302 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1303 }
1304 }
1305 hashcode = crc & ((1 << 9) - 1);
1306
1307 byte = hashcode >> 3;
1308 bit = 1 << (hashcode & 0x07);
1309
1310 if (lp->shmem_length == IO_ONLY) {
1311 unsigned char tmp;
1312
1313 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1314 tmp = inb(EWRK3_DATA);
1315 tmp |= bit;
1316 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1317 outb(tmp, EWRK3_DATA);
1318 } else {
1319 multicast_table[byte] |= bit;
1320 }
1321 } else {
1322 addrs += ETH_ALEN;
1323 }
1324 }
1325 }
1326
1327 lp->lock = 0;
1328
1329 return;
1330 }
1331
1332 #ifndef MODULE
1333
1334
1335
1336 static struct device *isa_probe(struct device *dev)
1337 {
1338 int i, iobase, status;
1339 unsigned long int tmp = mem_chkd;
1340
1341 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1342 i < 24;
1343 iobase += EWRK3_IOP_INC, i++) {
1344 if (tmp & 0x01) {
1345
1346 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1347 if (DevicePresent(iobase) == 0) {
1348
1349
1350
1351
1352 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1353 if (num_ewrk3s > 0) {
1354 dev = alloc_device(dev, iobase);
1355 } else {
1356 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1357 num_ewrk3s++;
1358 }
1359 }
1360 num_eth++;
1361 } else {
1362 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1363 }
1364 } else {
1365 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1366 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1367 }
1368 }
1369 tmp >>= 1;
1370 }
1371
1372 return dev;
1373 }
1374
1375
1376
1377
1378
1379 static struct device *eisa_probe(struct device *dev)
1380 {
1381 int i, iobase = EWRK3_EISA_IO_PORTS;
1382 int status;
1383
1384 iobase+=EISA_SLOT_INC;
1385 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1386
1387
1388 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1389 if (DevicePresent(iobase) == 0) {
1390
1391
1392
1393
1394 mem_chkd |= (0x01 << (i + 24));
1395 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1396 if (num_ewrk3s > 0) {
1397 dev = alloc_device(dev, iobase);
1398 } else {
1399 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1400 num_ewrk3s++;
1401 }
1402 }
1403 num_eth++;
1404 }
1405 }
1406 }
1407 return dev;
1408 }
1409
1410
1411
1412
1413
1414 static struct device *alloc_device(struct device *dev, int iobase)
1415 {
1416
1417
1418
1419 while (dev->next != NULL) {
1420 if (dev->next->base_addr == 0xffe0) break;
1421 dev = dev->next;
1422 num_eth++;
1423 }
1424
1425
1426
1427
1428
1429 if (dev->next == NULL) {
1430 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1431 GFP_KERNEL);
1432 if (dev->next == NULL) {
1433 printk("eth%d: Device not initialised, insufficient memory\n",
1434 num_eth);
1435 }
1436 }
1437
1438
1439
1440
1441
1442
1443 if ((dev->next != NULL) &&
1444 (num_eth > 0) && (num_eth < 9999)) {
1445 dev = dev->next;
1446 dev->name = (char *)(dev + sizeof(struct device));
1447 sprintf(dev->name,"eth%d", num_eth);
1448 dev->base_addr = iobase;
1449 dev->next = NULL;
1450 dev->init = &ewrk3_probe;
1451 num_ewrk3s++;
1452 }
1453
1454 return dev;
1455 }
1456 #endif
1457
1458
1459
1460
1461 static int Read_EEPROM(short iobase, unsigned char eaddr)
1462 {
1463 int i;
1464
1465 outb((eaddr & 0x3f), EWRK3_PIR1);
1466 outb(EEPROM_RD, EWRK3_IOPR);
1467 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1468
1469 return inw(EWRK3_EPROM1);
1470 }
1471
1472
1473
1474
1475 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1476 {
1477 int i;
1478
1479 outb(EEPROM_WR_EN, EWRK3_IOPR);
1480 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1481 outw(data, EWRK3_EPROM1);
1482 outb((eaddr & 0x3f), EWRK3_PIR1);
1483 outb(EEPROM_WR, EWRK3_IOPR);
1484 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1485 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1486 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1487
1488 return 0;
1489 }
1490
1491
1492
1493
1494 static void EthwrkSignature(char *name, char *eeprom_image)
1495 {
1496 unsigned long i,j,k;
1497 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1498
1499 strcpy(name, "");
1500 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1501 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1502 if (signatures[i][k] == eeprom_image[j]) {
1503 k++;
1504 } else {
1505 k=0;
1506 }
1507 }
1508 if (k == strlen(signatures[i])) {
1509 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1510 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1511 name[EWRK3_NAME_LENGTH] = '\0';
1512 }
1513 }
1514 }
1515
1516 return;
1517 }
1518
1519
1520
1521
1522
1523
1524 static int DevicePresent(short iobase)
1525 {
1526 static short fp=1,sigLength=0;
1527 static char devSig[] = PROBE_SEQUENCE;
1528 char data;
1529 int i, j, status = 0;
1530 static char asc2hex(char value);
1531
1532
1533
1534
1535 if (fp) {
1536 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1537 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1538 devSig[i]<<=4;
1539 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1540 devSig[j]=devSig[i]+devSig[i+1];
1541 } else {
1542 status= -1;
1543 }
1544 } else {
1545 status= -1;
1546 }
1547 }
1548 sigLength=j;
1549 fp = 0;
1550 }
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560 if (!status) {
1561 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1562 data = inb(EWRK3_APROM);
1563 if (devSig[j] == data) {
1564 j++;
1565 } else {
1566 j=0;
1567 }
1568 }
1569
1570 if (j!=sigLength) {
1571 status = -ENODEV;
1572 }
1573 }
1574
1575 return status;
1576 }
1577
1578 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1579 {
1580 long k;
1581 unsigned short j,chksum;
1582 unsigned char crc, lfsr, sd, status = 0;
1583 int iobase = dev->base_addr;
1584
1585 if (chipType == LeMAC2) {
1586 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1587 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1588 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1589 crc = (crc >> 1) + lfsr;
1590 }
1591 }
1592 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1593 } else {
1594 for (k=0,j=0;j<3;j++) {
1595 k <<= 1 ;
1596 if (k > 0xffff) k-=0xffff;
1597 k += inw(EWRK3_PAR0 + (j<<1));
1598 if (k > 0xffff) k-=0xffff;
1599 }
1600 if (k == 0xffff) k=0;
1601 chksum = inb(EWRK3_APROM);
1602 chksum |= (inb(EWRK3_APROM)<<8);
1603 if (k != chksum) status = -1;
1604 }
1605
1606 return status;
1607 }
1608
1609
1610
1611
1612
1613 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1614 {
1615 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1616 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1617 int i, j, iobase = dev->base_addr, status = 0;
1618 unsigned char csr;
1619 union {
1620 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1621 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1622 } tmp;
1623 int err;
1624
1625 switch(ioc->cmd) {
1626 case EWRK3_GET_HWADDR:
1627 for (i=0; i<ETH_ALEN; i++) {
1628 tmp.addr[i] = dev->dev_addr[i];
1629 }
1630 ioc->len = ETH_ALEN;
1631
1632 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ETH_ALEN);
1633 if (err) return err;
1634 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1635
1636 break;
1637 case EWRK3_SET_HWADDR:
1638 if (suser()) {
1639 csr = inb(EWRK3_CSR);
1640 csr |= (TXD|RXD);
1641 outb(csr, EWRK3_CSR);
1642
1643 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
1644 if (err) return err;
1645 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1646 for (i=0; i<ETH_ALEN; i++) {
1647 dev->dev_addr[i] = tmp.addr[i];
1648 outb(tmp.addr[i], EWRK3_PAR0 + i);
1649 }
1650
1651 csr &= ~(TXD|RXD);
1652 outb(csr, EWRK3_CSR);
1653 } else {
1654 status = -EPERM;
1655 }
1656
1657 break;
1658 case EWRK3_SET_PROM:
1659 if (suser()) {
1660 csr = inb(EWRK3_CSR);
1661 csr |= PME;
1662 csr &= ~MCE;
1663 outb(csr, EWRK3_CSR);
1664 } else {
1665 status = -EPERM;
1666 }
1667
1668 break;
1669 case EWRK3_CLR_PROM:
1670 if (suser()) {
1671 csr = inb(EWRK3_CSR);
1672 csr &= ~PME;
1673 outb(csr, EWRK3_CSR);
1674 } else {
1675 status = -EPERM;
1676 }
1677
1678 break;
1679 case EWRK3_SAY_BOO:
1680 printk("%s: Boo!\n", dev->name);
1681
1682 break;
1683 case EWRK3_GET_MCA:
1684 err = verify_area(VERIFY_WRITE, (void *)ioc->data, HASH_TABLE_LEN >> 3);
1685 if (err) return err;
1686
1687 while (set_bit(0, (void *)&lp->lock) != 0);
1688 if (lp->shmem_length == IO_ONLY) {
1689 outb(0, EWRK3_IOPR);
1690 outw(PAGE0_HTE, EWRK3_PIR1);
1691 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1692 tmp.addr[i] = inb(EWRK3_DATA);
1693 }
1694 } else {
1695 outb(0, EWRK3_MPR);
1696 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1697 }
1698 ioc->len = (HASH_TABLE_LEN >> 3);
1699 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1700 lp->lock = 0;
1701
1702 break;
1703 case EWRK3_SET_MCA:
1704 if (suser()) {
1705 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN * ioc->len);
1706 if (err) return err;
1707
1708 if (ioc->len != HASH_TABLE_LEN) {
1709 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1710 }
1711 set_multicast_list(dev, ioc->len, tmp.addr);
1712 } else {
1713 status = -EPERM;
1714 }
1715
1716 break;
1717 case EWRK3_CLR_MCA:
1718 if (suser()) {
1719 set_multicast_list(dev, 0, NULL);
1720 } else {
1721 status = -EPERM;
1722 }
1723
1724 break;
1725 case EWRK3_MCA_EN:
1726 if (suser()) {
1727 csr = inb(EWRK3_CSR);
1728 csr |= MCE;
1729 csr &= ~PME;
1730 outb(csr, EWRK3_CSR);
1731 } else {
1732 status = -EPERM;
1733 }
1734
1735 break;
1736 case EWRK3_GET_STATS:
1737 err = verify_area(VERIFY_WRITE, (void *)ioc->data, sizeof(lp->pktStats));
1738 if (err) return err;
1739
1740 cli();
1741 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1742 ioc->len = EWRK3_PKT_STAT_SZ;
1743 sti();
1744
1745 break;
1746 case EWRK3_CLR_STATS:
1747 if (suser()) {
1748 cli();
1749 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1750 sti();
1751 } else {
1752 status = -EPERM;
1753 }
1754
1755 break;
1756 case EWRK3_GET_CSR:
1757 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1758 if (err) return err;
1759
1760 tmp.addr[0] = inb(EWRK3_CSR);
1761 memcpy_tofs(ioc->data, tmp.addr, 1);
1762
1763 break;
1764 case EWRK3_SET_CSR:
1765 err = verify_area(VERIFY_READ, (void *)ioc->data, 1);
1766 if (err) return err;
1767
1768 if (suser()) {
1769 memcpy_fromfs(tmp.addr, ioc->data, 1);
1770 outb(tmp.addr[0], EWRK3_CSR);
1771 } else {
1772 status = -EPERM;
1773 }
1774
1775 break;
1776 case EWRK3_GET_EEPROM:
1777 if (suser()) {
1778 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
1779 if (err) return err;
1780
1781 for (i=0; i<(EEPROM_MAX>>1); i++) {
1782 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1783 }
1784 i = EEPROM_MAX;
1785 tmp.addr[i++] = inb(EWRK3_CMR);
1786 for (j=0;j<ETH_ALEN;j++) {
1787 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1788 }
1789 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1790 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1791 } else {
1792 status = -EPERM;
1793 }
1794
1795 break;
1796 case EWRK3_SET_EEPROM:
1797 if (suser()) {
1798 err = verify_area(VERIFY_READ, (void *)ioc->data, EEPROM_MAX);
1799 if (err) return err;
1800
1801 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1802 for (i=0; i<(EEPROM_MAX>>1); i++) {
1803 Write_EEPROM(tmp.val[i], iobase, i);
1804 }
1805 } else {
1806 status = -EPERM;
1807 }
1808
1809 break;
1810 case EWRK3_GET_CMR:
1811 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1812 if (err) return err;
1813
1814 tmp.addr[0] = inb(EWRK3_CMR);
1815 memcpy_tofs(ioc->data, tmp.addr, 1);
1816
1817 break;
1818 case EWRK3_SET_TX_CUT_THRU:
1819 if (suser()) {
1820 lp->txc = 1;
1821 } else {
1822 status = -EPERM;
1823 }
1824
1825 break;
1826 case EWRK3_CLR_TX_CUT_THRU:
1827 if (suser()) {
1828 lp->txc = 0;
1829 } else {
1830 status = -EPERM;
1831 }
1832
1833 break;
1834 default:
1835 status = -EOPNOTSUPP;
1836 }
1837
1838 return status;
1839 }
1840
1841 static char asc2hex(char value)
1842 {
1843 value -= 0x30;
1844 if (value >= 0) {
1845 if (value > 9) {
1846 value &= 0x1f;
1847 value -= 0x07;
1848 if ((value < 0x0a) || (value > 0x0f)) {
1849 value = -1;
1850 }
1851 }
1852 } else {
1853 value = -1;
1854 }
1855 return value;
1856 }
1857
1858 #ifdef MODULE
1859 char kernel_version[] = UTS_RELEASE;
1860 static char devicename[9] = { 0, };
1861 static struct device thisEthwrk = {
1862 devicename,
1863 0, 0, 0, 0,
1864 0x300, 5,
1865 0, 0, 0, NULL, ewrk3_probe };
1866
1867 int io=0x300;
1868 int irq=5;
1869
1870 int
1871 init_module(void)
1872 {
1873 thisEthwrk.base_addr=io;
1874 thisEthwrk.irq=irq;
1875 if (register_netdev(&thisEthwrk) != 0)
1876 return -EIO;
1877 return 0;
1878 }
1879
1880 void
1881 cleanup_module(void)
1882 {
1883 if (MOD_IN_USE) {
1884 printk("%s: device busy, remove delayed\n",thisEthwrk.name);
1885 } else {
1886 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1887 unregister_netdev(&thisEthwrk);
1888 free(thisEthwrk.priv);
1889 thisEthwrk.priv = NULL;
1890 }
1891 }
1892 #endif
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904