This source file includes following definitions.
- xchg_u32
- xchg_u64
- xchg_ptr
1 #ifndef __ALPHA_SYSTEM_H
2 #define __ALPHA_SYSTEM_H
3
4
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7
8
9
10
11
12
13
14
15
16 #define BOOT_PCB 0x20000000
17 #define BOOT_ADDR 0x20000000
18 #define BOOT_SIZE (16*1024)
19
20 #define KERNEL_START 0xfffffc0000300000
21 #define SWAPPER_PGD 0xfffffc0000300000
22 #define INIT_STACK 0xfffffc0000302000
23 #define EMPTY_PGT 0xfffffc0000304000
24 #define EMPTY_PGE 0xfffffc0000308000
25 #define ZERO_PGE 0xfffffc000030A000
26
27 #define START_ADDR 0xfffffc0000310000
28 #define START_SIZE (2*1024*1024)
29
30
31
32
33 #define PAL_halt 0
34 #define PAL_cflush 1
35 #define PAL_draina 2
36 #define PAL_cobratt 9
37 #define PAL_bpt 128
38 #define PAL_bugchk 129
39 #define PAL_chmk 131
40 #define PAL_callsys 131
41 #define PAL_imb 134
42 #define PAL_rduniq 158
43 #define PAL_wruniq 159
44 #define PAL_gentrap 170
45 #define PAL_nphalt 190
46
47
48
49
50 #define PAL_swppal 10
51 #define PAL_mfpr_vptb 41
52
53
54
55
56 #define PAL_rdmces 16
57 #define PAL_wrmces 17
58 #define PAL_wrfen 43
59 #define PAL_wrvptptr 45
60 #define PAL_jtopal 46
61 #define PAL_swpctx 48
62 #define PAL_wrval 49
63 #define PAL_rdval 50
64 #define PAL_tbi 51
65 #define PAL_wrent 52
66 #define PAL_swpipl 53
67 #define PAL_rdps 54
68 #define PAL_wrkgp 55
69 #define PAL_wrusp 56
70 #define PAL_wrperfmon 57
71 #define PAL_rdusp 58
72 #define PAL_whami 60
73 #define PAL_rtsys 61
74 #define PAL_rti 63
75
76 #ifndef __ASSEMBLY__
77
78 extern void wrent(void *, unsigned long);
79 extern void wrkgp(unsigned long);
80 extern void wrusp(unsigned long);
81 extern unsigned long rdusp(void);
82
83 #define halt() __asm__ __volatile__(".long 0");
84
85 extern void alpha_switch_to(unsigned long pctxp);
86
87 #define switch_to(p) do { \
88 current = p; \
89 alpha_switch_to((unsigned long) &(p)->tss - 0xfffffc0000000000); \
90 } while (0)
91
92 #define mb() \
93 __asm__ __volatile__("mb": : :"memory")
94
95 #define draina() \
96 __asm__ __volatile__ ("call_pal %0" : : "i" (PAL_draina) : "memory")
97
98 #define getipl() \
99 ({ unsigned long __old_ipl; \
100 __asm__ __volatile__( \
101 "call_pal 54\n\t" \
102 "bis $0,$0,%0" \
103 : "=r" (__old_ipl) \
104 : : "$0", "$1", "$16", "$22", "$23", "$24", "$25"); \
105 __old_ipl; })
106
107 #define setipl(__new_ipl) \
108 __asm__ __volatile__( \
109 "bis %0,%0,$16\n\t" \
110 "call_pal 53" \
111 : : "r" (__new_ipl) \
112 : "$0", "$1", "$16", "$22", "$23", "$24", "$25")
113
114 #define swpipl(__new_ipl) \
115 ({ unsigned long __old_ipl; \
116 __asm__ __volatile__( \
117 "bis %1,%1,$16\n\t" \
118 "call_pal 53\n\t" \
119 "bis $0,$0,%0" \
120 : "=r" (__old_ipl) \
121 : "r" (__new_ipl) \
122 : "$0", "$1", "$16", "$22", "$23", "$24", "$25"); \
123 __old_ipl; })
124
125 #define cli() setipl(7)
126 #define sti() setipl(0)
127 #define save_flags(flags) do { flags = getipl(); } while (0)
128 #define restore_flags(flags) setipl(flags)
129
130 extern inline unsigned long xchg_u32(int * m, unsigned long val)
131 {
132 unsigned long dummy, dummy2;
133
134 __asm__ __volatile__(
135 "\n1:\t"
136 "ldl_l %0,%1\n\t"
137 "bis %2,%2,%3\n\t"
138 "stl_c %3,%1\n\t"
139 "beq %3,1b\n"
140 : "=r" (val), "=m" (*m), "=r" (dummy), "=r" (dummy2)
141 : "1" (*m), "2" (val));
142 return val;
143 }
144
145 extern inline unsigned long xchg_u64(long * m, unsigned long val)
146 {
147 unsigned long dummy, dummy2;
148
149 __asm__ __volatile__(
150 "\n1:\t"
151 "ldq_l %0,%1\n\t"
152 "bis %2,%2,%3\n\t"
153 "stq_c %3,%1\n\t"
154 "beq %3,1b\n"
155 : "=r" (val), "=m" (*m), "=r" (dummy), "=r" (dummy2)
156 : "1" (*m), "2" (val));
157 return val;
158 }
159
160 extern inline void * xchg_ptr(void *m, void *val)
161 {
162 return (void *) xchg_u64((long *) m, (unsigned long) val);
163 }
164
165 #endif
166
167 #endif