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*/
1 /*
2 Copyright 1994 Digital Equipment Corporation.
3
4 This software may be used and distributed according to the terms of the
5 GNU Public License, incorporated herein by reference.
6
7 The author may be reached as davies@wanton.lkg.dec.com or Digital
8 Equipment Corporation, 550 King Street, Littleton MA 01460.
9
10 =========================================================================
11 */
12
13 /*
14 ** DC21040 CSR<1..15> Register Address Map
15 */
16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
26 #define DE4X5_BROM iobase+(0x048 << lp->bus) /* Boot ROM Register */
27 #define DE4X5_SROM iobase+(0x048 << lp->bus) /* Serial ROM Register */
28 #define DE4X5_DDR iobase+(0x050 << lp->bus) /* Data Diagnostic Register */
29 #define DE4X5_FDR iobase+(0x058 << lp->bus) /* Full Duplex Register */
30 #define DE4X5_GPT iobase+(0x058 << lp->bus) /* General Purpose Timer Reg.*/
31 #define DE4X5_GEP iobase+(0x060 << lp->bus) /* General Purpose Register */
32 #define DE4X5_SISR iobase+(0x060 << lp->bus) /* SIA Status Register */
33 #define DE4X5_SICR iobase+(0x068 << lp->bus) /* SIA Connectivity Register */
34 #define DE4X5_STRR iobase+(0x070 << lp->bus) /* SIA TX/RX Register */
35 #define DE4X5_SIGR iobase+(0x078 << lp->bus) /* SIA General Register */
36
37 /*
38 ** EISA Register Address Map
39 */
40 #define EISA_ID iobase+0x0c80 /* EISA ID Registers */
41 #define EISA_ID0 iobase+0x0c80 /* EISA ID Register 0 */
42 #define EISA_ID1 iobase+0x0c81 /* EISA ID Register 1 */
43 #define EISA_ID2 iobase+0x0c82 /* EISA ID Register 2 */
44 #define EISA_ID3 iobase+0x0c83 /* EISA ID Register 3 */
45 #define EISA_CR iobase+0x0c84 /* EISA Control Register */
46 #define EISA_REG0 iobase+0x0c88 /* EISA Configuration Register 0 */
47 #define EISA_REG1 iobase+0x0c89 /* EISA Configuration Register 1 */
48 #define EISA_REG2 iobase+0x0c8a /* EISA Configuration Register 2 */
49 #define EISA_REG3 iobase+0x0c8f /* EISA Configuration Register 3 */
50 #define EISA_APROM iobase+0x0c90 /* Ethernet Address PROM */
51
52 /*
53 ** PCI/EISA Configuration Registers Address Map
54 */
55 #define PCI_CFID iobase+0x0008 /* PCI Configuration ID Register */
56 #define PCI_CFCS iobase+0x000c /* PCI Command/Status Register */
57 #define PCI_CFRV iobase+0x0018 /* PCI Revision Register */
58 #define PCI_CFLT iobase+0x001c /* PCI Latency Timer Register */
59 #define PCI_CBIO iobase+0x0028 /* PCI Base I/O Register */
60 #define PCI_CBMA iobase+0x002c /* PCI Base Memory Address Register */
61 #define PCI_CBER iobase+0x0030 /* PCI Expansion ROM Base Address Reg. */
62 #define PCI_CFIT iobase+0x003c /* PCI Configuration Interrupt Register */
63 #define PCI_CFDA iobase+0x0040 /* PCI Driver Area Register */
64
65 /*
66 ** EISA Configuration Register 0 bit definitions
67 */
68 #define ER0_BSW 0x80 /* EISA Bus Slave Width, 1: 32 bits */
69 #define ER0_BMW 0x40 /* EISA Bus Master Width, 1: 32 bits */
70 #define ER0_EPT 0x20 /* EISA PREEMPT Time, 0: 23 BCLKs */
71 #define ER0_ISTS 0x10 /* Interrupt Status (X) */
72 #define ER0_LI 0x08 /* Latch Interrupts */
73 #define ER0_INTL 0x06 /* INTerrupt Level */
74 #define ER0_INTT 0x01 /* INTerrupt Type, 0: Level, 1: Edge */
75
76 /*
77 ** EISA Configuration Register 1 bit definitions
78 */
79 #define ER1_IAM 0xe0 /* ISA Address Mode */
80 #define ER1_IAE 0x10 /* ISA Addressing Enable */
81 #define ER1_UPIN 0x0f /* User Pins */
82
83 /*
84 ** EISA Configuration Register 2 bit definitions
85 */
86 #define ER2_BRS 0xc0 /* Boot ROM Size */
87 #define ER2_BRA 0x3c /* Boot ROM Address <16:13> */
88
89 /*
90 ** EISA Configuration Register 3 bit definitions
91 */
92 #define ER3_BWE 0x40 /* Burst Write Enable */
93 #define ER3_BRE 0x04 /* Burst Read Enable */
94 #define ER3_LSR 0x02 /* Local Software Reset */
95
96 /*
97 ** PCI Configuration ID Register (PCI_CFID)
98 */
99 #define CFID_DID 0xff00 /* Device ID */
100 #define CFID_VID 0x00ff /* Vendor ID */
101 #define DC21040_DID 0x0002 /* Unique Device ID # */
102 #define DC21040_VID 0x1011 /* DC21040 Manufacturer */
103 #define DC21041_DID 0x0014 /* Unique Device ID # */
104 #define DC21041_VID 0x1011 /* DC21041 Manufacturer */
105 #define DC21140_DID 0x0009 /* Unique Device ID # */
106 #define DC21140_VID 0x1011 /* DC21140 Manufacturer */
107
108 /*
109 ** Chipset defines
110 */
111 #define DC21040 DC21040_DID
112 #define DC21041 DC21041_DID
113 #define DC21140 DC21140_DID
114
115 #define is_DC21040 ((vendor == DC21040_VID) && (device == DC21040_DID))
116 #define is_DC21041 ((vendor == DC21041_VID) && (device == DC21041_DID))
117 #define is_DC21140 ((vendor == DC21140_VID) && (device == DC21140_DID))
118
119 /*
120 ** PCI Configuration Command/Status Register (PCI_CFCS)
121 */
122 #define CFCS_DPE 0x80000000 /* Detected Parity Error (S) */
123 #define CFCS_SSE 0x40000000 /* Signal System Error (S) */
124 #define CFCS_RMA 0x20000000 /* Receive Master Abort (S) */
125 #define CFCS_RTA 0x10000000 /* Receive Target Abort (S) */
126 #define CFCS_DST 0x06000000 /* DEVSEL Timing (S) */
127 #define CFCS_DPR 0x01000000 /* Data Parity Report (S) */
128 #define CFCS_FBB 0x00800000 /* Fast Back-To-Back (S) */
129 #define CFCS_SLE 0x00000100 /* System Error Enable (C) */
130 #define CFCS_PER 0x00000040 /* Parity Error Response (C) */
131 #define CFCS_MO 0x00000004 /* Master Operation (C) */
132 #define CFCS_MSA 0x00000002 /* Memory Space Access (C) */
133 #define CFCS_IOSA 0x00000001 /* I/O Space Access (C) */
134
135 /*
136 ** PCI Configuration Revision Register (PCI_CFRV)
137 */
138 #define CFRV_BC 0xff000000 /* Base Class */
139 #define CFRV_SC 0x00ff0000 /* Subclass */
140 #define CFRV_SN 0x000000f0 /* Step Number */
141 #define CFRV_RN 0x0000000f /* Revision Number */
142 #define BASE_CLASS 0x02000000 /* Indicates Network Controller */
143 #define SUB_CLASS 0x00000000 /* Indicates Ethernet Controller */
144 #define STEP_NUMBER 0x00000020 /* Increments for future chips */
145 #define REV_NUMBER 0x00000003 /* 0x00, 0x01, 0x02, 0x03: Rev in Step */
146 #define CFRV_MASK 0xffff0000 /* Register mask */
147
148 /*
149 ** PCI Configuration Latency Timer Register (PCI_CFLT)
150 */
151 #define CFLT_BC 0x0000ff00 /* Latency Timer bits */
152
153 /*
154 ** PCI Configuration Base I/O Address Register (PCI_CBIO)
155 */
156 #define CBIO_MASK 0x0000ff80 /* Base I/O Address Mask */
157 #define CBIO_IOSI 0x00000001 /* I/O Space Indicator (RO, value is 1) */
158
159 /*
160 ** PCI Configuration Expansion ROM Base Address Register (PCI_CBER)
161 */
162 #define CBER_MASK 0xfffffc00 /* Expansion ROM Base Address Mask */
163 #define CBER_ROME 0x00000001 /* ROM Enable */
164
165 /*
166 ** PCI Configuration Driver Area Register (PCI_CFDA)
167 */
168 #define CFDA_PSM 0x80000000 /* Power Saving Mode */
169
170 /*
171 ** DC21040 Bus Mode Register (DE4X5_BMR)
172 */
173 #define BMR_DBO 0x00100000 /* Descriptor Byte Ordering (Endian) */
174 #define BMR_TAP 0x000e0000 /* Transmit Automatic Polling */
175 #define BMR_DAS 0x00010000 /* Diagnostic Address Space */
176 #define BMR_CAL 0x0000c000 /* Cache Alignment */
177 #define BMR_PBL 0x00003f00 /* Programmable Burst Length */
178 #define BMR_BLE 0x00000080 /* Big/Little Endian */
179 #define BMR_DSL 0x0000007c /* Descriptor Skip Length */
180 #define BMR_BAR 0x00000002 /* Bus ARbitration */
181 #define BMR_SWR 0x00000001 /* Software Reset */
182
183 #define TAP_NOPOLL 0x00000000 /* No automatic polling */
184 #define TAP_200US 0x00020000 /* TX automatic polling every 200us */
185 #define TAP_800US 0x00040000 /* TX automatic polling every 800us */
186 #define TAP_1_6MS 0x00060000 /* TX automatic polling every 1.6ms */
187 #define TAP_12_8US 0x00080000 /* TX automatic polling every 12.8us */
188 #define TAP_25_6US 0x000a0000 /* TX automatic polling every 25.6us */
189 #define TAP_51_2US 0x000c0000 /* TX automatic polling every 51.2us */
190 #define TAP_102_4US 0x000e0000 /* TX automatic polling every 102.4us */
191
192 #define CAL_NOUSE 0x00000000 /* Not used */
193 #define CAL_8LONG 0x00004000 /* 8-longword alignment */
194 #define CAL_16LONG 0x00008000 /* 16-longword alignment */
195 #define CAL_32LONG 0x0000c000 /* 32-longword alignment */
196
197 #define PBL_0 0x00000000 /* DMA burst length = amount in RX FIFO */
198 #define PBL_1 0x00000100 /* 1 longword DMA burst length */
199 #define PBL_2 0x00000200 /* 2 longwords DMA burst length */
200 #define PBL_4 0x00000400 /* 4 longwords DMA burst length */
201 #define PBL_8 0x00000800 /* 8 longwords DMA burst length */
202 #define PBL_16 0x00001000 /* 16 longwords DMA burst length */
203 #define PBL_32 0x00002000 /* 32 longwords DMA burst length */
204
205 #define DSL_0 0x00000000 /* 0 longword / descriptor */
206 #define DSL_1 0x00000004 /* 1 longword / descriptor */
207 #define DSL_2 0x00000008 /* 2 longwords / descriptor */
208 #define DSL_4 0x00000010 /* 4 longwords / descriptor */
209 #define DSL_8 0x00000020 /* 8 longwords / descriptor */
210 #define DSL_16 0x00000040 /* 16 longwords / descriptor */
211 #define DSL_32 0x00000080 /* 32 longwords / descriptor */
212
213 /*
214 ** DC21040 Transmit Poll Demand Register (DE4X5_TPD)
215 */
216 #define TPD 0x00000001 /* Transmit Poll Demand */
217
218 /*
219 ** DC21040 Receive Poll Demand Register (DE4X5_RPD)
220 */
221 #define RPD 0x00000001 /* Receive Poll Demand */
222
223 /*
224 ** DC21040 Receive Ring Base Address Register (DE4X5_RRBA)
225 */
226 #define RRBA 0xfffffffc /* RX Descriptor List Start Address */
227
228 /*
229 ** DC21040 Transmit Ring Base Address Register (DE4X5_TRBA)
230 */
231 #define TRBA 0xfffffffc /* TX Descriptor List Start Address */
232
233 /*
234 ** DC21040 Status Register (DE4X5_STS)
235 */
236 #define STS_BE 0x03800000 /* Bus Error Bits */
237 #define STS_TS 0x00700000 /* Transmit Process State */
238 #define STS_RS 0x000e0000 /* Receive Process State */
239 #define STS_NIS 0x00010000 /* Normal Interrupt Summary */
240 #define STS_AIS 0x00008000 /* Abnormal Interrupt Summary */
241 #define STS_ER 0x00004000 /* Early Receive */
242 #define STS_SE 0x00002000 /* System Error */
243 #define STS_LNF 0x00001000 /* Link Fail */
244 #define STS_FD 0x00000800 /* Full-Duplex Short Frame Received */
245 #define STS_TM 0x00000800 /* Timer Expired (DC21041) */
246 #define STS_AT 0x00000400 /* AUI/TP Pin */
247 #define STS_RWT 0x00000200 /* Receive Watchdog Time-Out */
248 #define STS_RPS 0x00000100 /* Receive Process Stopped */
249 #define STS_RU 0x00000080 /* Receive Buffer Unavailable */
250 #define STS_RI 0x00000040 /* Receive Interrupt */
251 #define STS_UNF 0x00000020 /* Transmit Underflow */
252 #define STS_LNP 0x00000010 /* Link Pass */
253 #define STS_TJT 0x00000008 /* Transmit Jabber Time-Out */
254 #define STS_TU 0x00000004 /* Transmit Buffer Unavailable */
255 #define STS_TPS 0x00000002 /* Transmit Process Stopped */
256 #define STS_TI 0x00000001 /* Transmit Interrupt */
257
258 #define EB_PAR 0x00000000 /* Parity Error */
259 #define EB_MA 0x00800000 /* Master Abort */
260 #define EB_TA 0x01000000 /* Target Abort */
261 #define EB_RES0 0x01800000 /* Reserved */
262 #define EB_RES1 0x02000000 /* Reserved */
263
264 #define TS_STOP 0x00000000 /* Stopped */
265 #define TS_FTD 0x00100000 /* Fetch Transmit Descriptor */
266 #define TS_WEOT 0x00200000 /* Wait for End Of Transmission */
267 #define TS_QDAT 0x00300000 /* Queue skb data into TX FIFO */
268 #define TS_RES 0x00400000 /* Reserved */
269 #define TS_SPKT 0x00500000 /* Setup Packet */
270 #define TS_SUSP 0x00600000 /* Suspended */
271 #define TS_CLTD 0x00700000 /* Close Transmit Descriptor */
272
273 #define RS_STOP 0x00000000 /* Stopped */
274 #define RS_FRD 0x00020000 /* Fetch Receive Descriptor */
275 #define RS_CEOR 0x00040000 /* Check for End of Receive Packet */
276 #define RS_WFRP 0x00060000 /* Wait for Receive Packet */
277 #define RS_SUSP 0x00080000 /* Suspended */
278 #define RS_CLRD 0x000a0000 /* Close Receive Descriptor */
279 #define RS_FLUSH 0x000c0000 /* Flush RX FIFO */
280 #define RS_QRFS 0x000e0000 /* Queue RX FIFO into RX Skb */
281
282 #define INT_CANCEL 0x0001ffff /* For zeroing all interrupt sources */
283
284 /*
285 ** DC21040 Operation Mode Register (DE4X5_OMR)
286 */
287 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
288 #define OMR_SCR 0x01000000 /* Scrambler Mode */
289 #define OMR_PCS 0x00800000 /* PCS Function */
290 #define OMR_TTM 0x00400000 /* Transmit Threshold Mode */
291 #define OMR_SF 0x00200000 /* Store and Forward */
292 #define OMR_HBD 0x00080000 /* HeartBeat Disable */
293 #define OMR_PS 0x00040000 /* Port Select */
294 #define OMR_CA 0x00020000 /* Capture Effect Enable */
295 #define OMR_BP 0x00010000 /* Back Pressure */
296 #define OMR_TR 0x0000c000 /* Threshold Control Bits */
297 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
298 #define OMR_FC 0x00001000 /* Force Collision Mode */
299 #define OMR_OM 0x00000c00 /* Operating Mode */
300 #define OMR_FD 0x00000200 /* Full Duplex Mode */
301 #define OMR_FKD 0x00000100 /* Flaky Oscillator Disable */
302 #define OMR_PM 0x00000080 /* Pass All Multicast */
303 #define OMR_PR 0x00000040 /* Promiscuous Mode */
304 #define OMR_SB 0x00000020 /* Start/Stop Backoff Counter */
305 #define OMR_IF 0x00000010 /* Inverse Filtering */
306 #define OMR_PB 0x00000008 /* Pass Bad Frames */
307 #define OMR_HO 0x00000004 /* Hash Only Filtering Mode */
308 #define OMR_SR 0x00000002 /* Start/Stop Receive */
309 #define OMR_HP 0x00000001 /* Hash/Perfect Receive Filtering Mode */
310
311 #define TR_72 0x00000000 /* Threshold set to 72 bytes */
312 #define TR_96 0x00004000 /* Threshold set to 96 bytes */
313 #define TR_128 0x00008000 /* Threshold set to 128 bytes */
314 #define TR_160 0x0000c000 /* Threshold set to 160 bytes */
315
316 /*
317 ** DC21040 Interrupt Mask Register (DE4X5_IMR)
318 */
319 #define IMR_NIM 0x00010000 /* Normal Interrupt Summary Mask */
320 #define IMR_AIM 0x00008000 /* Abnormal Interrupt Summary Mask */
321 #define IMR_ERM 0x00004000 /* Early Receive Mask */
322 #define IMR_SEM 0x00002000 /* System Error Mask */
323 #define IMR_LFM 0x00001000 /* Link Fail Mask */
324 #define IMR_FDM 0x00000800 /* Full-Duplex (Short Frame) Mask */
325 #define IMR_TMM 0x00000800 /* Timer Expired Mask (DC21041) */
326 #define IMR_ATM 0x00000400 /* AUI/TP Switch Mask */
327 #define IMR_RWM 0x00000200 /* Receive Watchdog Time-Out Mask */
328 #define IMR_RSM 0x00000100 /* Receive Stopped Mask */
329 #define IMR_RUM 0x00000080 /* Receive Buffer Unavailable Mask */
330 #define IMR_RIM 0x00000040 /* Receive Interrupt Mask */
331 #define IMR_UNM 0x00000020 /* Underflow Interrupt Mask */
332 #define IMR_LPM 0x00000010 /* Link Pass */
333 #define IMR_TJM 0x00000008 /* Transmit Time-Out Jabber Mask */
334 #define IMR_TUM 0x00000004 /* Transmit Buffer Unavailable Mask */
335 #define IMR_TSM 0x00000002 /* Transmission Stopped Mask */
336 #define IMR_TIM 0x00000001 /* Transmit Interrupt Mask */
337
338 /*
339 ** DC21040 Missed Frame Counter (DE4X5_MFC)
340 */
341 #define MFC_OVFL 0x00010000 /* Counter Overflow Bit */
342 #define MFC_CNTR 0x0000ffff /* Counter Bits */
343
344 /*
345 ** DC21040 Ethernet Address PROM (DE4X5_APROM)
346 */
347 #define APROM_DN 0x80000000 /* Data Not Valid */
348 #define APROM_DT 0x000000ff /* Address Byte */
349
350 /*
351 ** DC21041 Boot/Ethernet Address ROM (DE4X5_BROM)
352 */
353 #define BROM_MODE 0x00008000 /* MODE_1: 0, MODE_0: 1 (read only) */
354 #define BROM_RD 0x00004000 /* Read from Boot ROM */
355 #define BROM_WR 0x00002000 /* Write to Boot ROM */
356 #define BROM_BR 0x00001000 /* Select Boot ROM when set */
357 #define BROM_SR 0x00000800 /* Select Serial ROM when set */
358 #define BROM_REG 0x00000400 /* External Register Select */
359 #define BROM_DT 0x000000ff /* Data Byte */
360
361 /*
362 ** DC21041 Serial/Ethernet Address ROM (DE4X5_SROM)
363 */
364 #define SROM_MODE 0x00008000 /* MODE_1: 0, MODE_0: 1 (read only) */
365 #define SROM_RD 0x00004000 /* Read from Boot ROM */
366 #define SROM_WR 0x00002000 /* Write to Boot ROM */
367 #define SROM_BR 0x00001000 /* Select Boot ROM when set */
368 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
369 #define SROM_REG 0x00000400 /* External Register Select */
370 #define SROM_DT 0x000000ff /* Data Byte */
371
372 #define DT_OUT 0x00000008 /* Serial Data Out */
373 #define DT_IN 0x00000004 /* Serial Data In */
374 #define DT_CLK 0x00000002 /* Serial ROM Clock */
375 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
376
377 /*
378 ** DC21040 Full Duplex Register (DE4X5_FDR)
379 */
380 #define FDR_FDACV 0x0000ffff /* Full Duplex Auto Configuration Value */
381
382 /*
383 ** DC21041 General Purpose Timer Register (DE4X5_GPT)
384 */
385 #define GPT_CON 0x00010000 /* One shot: 0, Continuous: 1 */
386 #define GPT_VAL 0x0000ffff /* Timer Value */
387
388 /*
389 ** DC21140 General Purpose Register (DE4X5_GEP) (hardware dependent bits)
390 */
391 /* Valid ONLY for DE500 hardware */
392 #define GEP_LNP 0x00000080 /* Link Pass (input) */
393 #define GEP_SLNK 0x00000040 /* SYM LINK (input) */
394 #define GEP_SDET 0x00000020 /* Signal Detect (input) */
395 #define GEP_FDXD 0x00000008 /* Full Duplex Disable (output) */
396 #define GEP_PHYL 0x00000004 /* PHY Loopback (output) */
397 #define GEP_FLED 0x00000002 /* Force Activity LED on (output) */
398 #define GEP_MODE 0x00000001 /* 0: 10Mb/s, 1: 100Mb/s */
399 #define GEP_INIT 0x0000010f /* Setup inputs (0) and outputs (1) */
400
401
402 /*
403 ** DC21040 SIA Status Register (DE4X5_SISR)
404 */
405 #define SISR_LPC 0xffff0000 /* Link Partner's Code Word */
406 #define SISR_LPN 0x00008000 /* Link Partner Negotiable */
407 #define SISR_ANS 0x00007000 /* Auto Negotiation Arbitration State */
408 #define SISR_NSN 0x00000800 /* Non Stable NLPs Detected */
409 #define SISR_ANR_FDS 0x00000400 /* Auto Negotiate Restart/Full Duplex Sel.*/
410 #define SISR_NRA 0x00000200 /* Non Selected Port Receive Activity */
411 #define SISR_SRA 0x00000100 /* Selected Port Receive Activity */
412 #define SISR_DAO 0x00000080 /* PLL All One */
413 #define SISR_DAZ 0x00000040 /* PLL All Zero */
414 #define SISR_DSP 0x00000020 /* PLL Self-Test Pass */
415 #define SISR_DSD 0x00000010 /* PLL Self-Test Done */
416 #define SISR_APS 0x00000008 /* Auto Polarity State */
417 #define SISR_LKF 0x00000004 /* Link Fail Status */
418 #define SISR_NCR 0x00000002 /* Network Connection Error */
419 #define SISR_PAUI 0x00000001 /* AUI_TP Indication */
420 #define SIA_RESET 0x00000000 /* SIA Reset */
421
422 #define ANS_NDIS 0x00000000 /* Nway disable */
423 #define ANS_TDIS 0x00001000 /* Transmit Disable */
424 #define ANS_ADET 0x00002000 /* Ability Detect */
425 #define ANS_ACK 0x00003000 /* Acknowledge */
426 #define ANS_CACK 0x00004000 /* Complete Acknowledge */
427 #define ANS_NWOK 0x00005000 /* Nway OK - FLP Link Good */
428 #define ANS_LCHK 0x00006000 /* Link Check */
429
430 /*
431 ** DC21040 SIA Connectivity Register (DE4X5_SICR)
432 */
433 #define SICR_SDM 0xffff0000 /* SIA Diagnostics Mode */
434 #define SICR_OE57 0x00008000 /* Output Enable 5 6 7 */
435 #define SICR_OE24 0x00004000 /* Output Enable 2 4 */
436 #define SICR_OE13 0x00002000 /* Output Enable 1 3 */
437 #define SICR_IE 0x00001000 /* Input Enable */
438 #define SICR_EXT 0x00000000 /* SIA MUX Select External SIA Mode */
439 #define SICR_D_SIA 0x00000400 /* SIA MUX Select Diagnostics - SIA Sigs */
440 #define SICR_DPLL 0x00000800 /* SIA MUX Select Diagnostics - DPLL Sigs*/
441 #define SICR_APLL 0x00000a00 /* SIA MUX Select Diagnostics - DPLL Sigs*/
442 #define SICR_D_RxM 0x00000c00 /* SIA MUX Select Diagnostics - RxM Sigs */
443 #define SICR_M_RxM 0x00000d00 /* SIA MUX Select Diagnostics - RxM Sigs */
444 #define SICR_LNKT 0x00000e00 /* SIA MUX Select Diagnostics - Link Test*/
445 #define SICR_SEL 0x00000f00 /* SIA MUX Select AUI or TP with LEDs */
446 #define SICR_ASE 0x00000080 /* APLL Start Enable*/
447 #define SICR_SIM 0x00000040 /* Serial Interface Input Multiplexer */
448 #define SICR_ENI 0x00000020 /* Encoder Input Multiplexer */
449 #define SICR_EDP 0x00000010 /* SIA PLL External Input Enable */
450 #define SICR_AUI 0x00000008 /* 10Base-T or AUI */
451 #define SICR_CAC 0x00000004 /* CSR Auto Configuration */
452 #define SICR_PS 0x00000002 /* Pin AUI/TP Selection */
453 #define SICR_SRL 0x00000001 /* SIA Reset */
454 #define SICR_RESET 0xffff0000 /* Reset value for SICR */
455
456 /*
457 ** DC21040 SIA Transmit and Receive Register (DE4X5_STRR)
458 */
459 #define STRR_TAS 0x00008000 /* 10Base-T/AUI Autosensing Enable */
460 #define STRR_SPP 0x00004000 /* Set Polarity Plus */
461 #define STRR_APE 0x00002000 /* Auto Polarity Enable */
462 #define STRR_LTE 0x00001000 /* Link Test Enable */
463 #define STRR_SQE 0x00000800 /* Signal Quality Enable */
464 #define STRR_CLD 0x00000400 /* Collision Detect Enable */
465 #define STRR_CSQ 0x00000200 /* Collision Squelch Enable */
466 #define STRR_RSQ 0x00000100 /* Receive Squelch Enable */
467 #define STRR_ANE 0x00000080 /* Auto Negotiate Enable */
468 #define STRR_HDE 0x00000040 /* Half Duplex Enable */
469 #define STRR_CPEN 0x00000030 /* Compensation Enable */
470 #define STRR_LSE 0x00000008 /* Link Pulse Send Enable */
471 #define STRR_DREN 0x00000004 /* Driver Enable */
472 #define STRR_LBK 0x00000002 /* Loopback Enable */
473 #define STRR_ECEN 0x00000001 /* Encoder Enable */
474 #define STRR_RESET 0xffffffff /* Reset value for STRR */
475
476 /*
477 ** DC21040 SIA General Register (DE4X5_SIGR)
478 */
479 #define SIGR_LV2 0x00008000 /* General Purpose LED2 value */
480 #define SIGR_LE2 0x00004000 /* General Purpose LED2 enable */
481 #define SIGR_FRL 0x00002000 /* Force Receiver Low */
482 #define SIGR_DPST 0x00001000 /* PLL Self Test Start */
483 #define SIGR_LSD 0x00000800 /* LED Stretch Disable */
484 #define SIGR_FLF 0x00000400 /* Force Link Fail */
485 #define SIGR_FUSQ 0x00000200 /* Force Unsquelch */
486 #define SIGR_TSCK 0x00000100 /* Test Clock */
487 #define SIGR_LV1 0x00000080 /* General Purpose LED1 value */
488 #define SIGR_LE1 0x00000040 /* General Purpose LED1 enable */
489 #define SIGR_RWR 0x00000020 /* Receive Watchdog Release */
490 #define SIGR_RWD 0x00000010 /* Receive Watchdog Disable */
491 #define SIGR_ABM 0x00000008 /* BNC: 0, AUI:1 */
492 #define SIGR_JCK 0x00000004 /* Jabber Clock */
493 #define SIGR_HUJ 0x00000002 /* Host Unjab */
494 #define SIGR_JBD 0x00000001 /* Jabber Disable */
495 #define SIGR_RESET 0xffff0000 /* Reset value for SIGR */
496
497 /*
498 ** Receive Descriptor Bit Summary
499 */
500 #define R_OWN 0x80000000 /* Own Bit */
501 #define RD_FL 0x7fff0000 /* Frame Length */
502 #define RD_ES 0x00008000 /* Error Summary */
503 #define RD_LE 0x00004000 /* Length Error */
504 #define RD_DT 0x00003000 /* Data Type */
505 #define RD_RF 0x00000800 /* Runt Frame */
506 #define RD_MF 0x00000400 /* Multicast Frame */
507 #define RD_FS 0x00000200 /* First Descriptor */
508 #define RD_LS 0x00000100 /* Last Descriptor */
509 #define RD_TL 0x00000080 /* Frame Too Long */
510 #define RD_CS 0x00000040 /* Collision Seen */
511 #define RD_FT 0x00000020 /* Frame Type */
512 #define RD_RJ 0x00000010 /* Receive Watchdog */
513 #define RD_DB 0x00000004 /* Dribbling Bit */
514 #define RD_CE 0x00000002 /* CRC Error */
515 #define RD_OF 0x00000001 /* Overflow */
516
517 #define RD_RER 0x02000000 /* Receive End Of Ring */
518 #define RD_RCH 0x01000000 /* Second Address Chained */
519 #define RD_RBS2 0x003ff800 /* Buffer 2 Size */
520 #define RD_RBS1 0x000007ff /* Buffer 1 Size */
521
522 /*
523 ** Transmit Descriptor Bit Summary
524 */
525 #define T_OWN 0x80000000 /* Own Bit */
526 #define TD_ES 0x00008000 /* Error Summary */
527 #define TD_TO 0x00004000 /* Transmit Jabber Time-Out */
528 #define TD_LO 0x00000800 /* Loss Of Carrier */
529 #define TD_NC 0x00000400 /* No Carrier */
530 #define TD_LC 0x00000200 /* Late Collision */
531 #define TD_EC 0x00000100 /* Excessive Collisions */
532 #define TD_HF 0x00000080 /* Heartbeat Fail */
533 #define TD_CC 0x00000078 /* Collision Counter */
534 #define TD_LF 0x00000004 /* Link Fail */
535 #define TD_UF 0x00000002 /* Underflow Error */
536 #define TD_DE 0x00000001 /* Deferred */
537
538 #define TD_IC 0x80000000 /* Interrupt On Completion */
539 #define TD_LS 0x40000000 /* Last Segment */
540 #define TD_FS 0x20000000 /* First Segment */
541 #define TD_FT1 0x10000000 /* Filtering Type */
542 #define TD_SET 0x08000000 /* Setup Packet */
543 #define TD_AC 0x04000000 /* Add CRC Disable */
544 #define TD_TER 0x02000000 /* Transmit End Of Ring */
545 #define TD_TCH 0x01000000 /* Second Address Chained */
546 #define TD_DPD 0x00800000 /* Disabled Padding */
547 #define TD_FT0 0x00400000 /* Filtering Type */
548 #define TD_RBS2 0x003ff800 /* Buffer 2 Size */
549 #define TD_RBS1 0x000007ff /* Buffer 1 Size */
550
551 #define PERFECT_F 0x00000000
552 #define HASH_F TD_FT0
553 #define INVERSE_F TD_FT1
554 #define HASH_O_F TD_FT1| TD_F0
555
556 /*
557 ** Media / mode state machine definitions
558 */
559 #define NC 0x0000 /* No Connection */
560 #define TP 0x0001 /* 10Base-T */
561 #define TP_NW 0x0002 /* 10Base-T with Nway */
562 #define BNC 0x0004 /* Thinwire */
563 #define AUI 0x0008 /* Thickwire */
564 #define BNC_AUI 0x0010 /* BNC/AUI on DC21040 indistinguishable */
565 #define ANS 0x0020 /* Intermediate AutoNegotiation State */
566
567 #define _10Mb 0x0040 /* 10Mb/s Ethernet */
568 #define _100Mb 0x0080 /* 100Mb/s Ethernet */
569 #define SYM_WAIT 0x0100 /* Wait for SYM_LINK */
570 #define INIT 0x0200 /* Initial state */
571
572 #define AUTO 0x4000 /* Auto sense the media or speed */
573
574 /*
575 ** Miscellaneous
576 */
577 #define PCI 0
578 #define EISA 1
579
580 #define HASH_TABLE_LEN 512 /* Bits */
581 #define HASH_BITS 0x01ff /* 9 LS bits */
582
583 #define SETUP_FRAME_LEN 192 /* Bytes */
584 #define IMPERF_PA_OFFSET 156 /* Bytes */
585
586 #define POLL_DEMAND 1
587
588 #define LOST_MEDIA_THRESHOLD 3
589
590 #define MASK_INTERRUPTS 1
591 #define UNMASK_INTERRUPTS 0
592
593 #define DE4X5_STRLEN 8
594
595 /*
596 ** Address Filtering Modes
597 */
598 #define PERFECT 0 /* 16 perfect physical addresses */
599 #define HASH_PERF 1 /* 1 perfect, 512 multicast addresses */
600 #define PERFECT_REJ 2 /* Reject 16 perfect physical addresses */
601 #define ALL_HASH 3 /* Hashes all physical & multicast addrs */
602
603 #define ALL 0 /* Clear out all the setup frame */
604 #define PHYS_ADDR_ONLY 1 /* Update the physical address only */
605
606 /*
607 ** Booleans
608 */
609 #define NO 0
610 #define FALSE 0
611
612 #define YES !0
613 #define TRUE !0
614
615 /*
616 ** Include the IOCTL stuff
617 */
618 #include <linux/sockios.h>
619
620 #define DE4X5IOCTL SIOCDEVPRIVATE
621
622 struct de4x5_ioctl {
623 unsigned short cmd; /* Command to run */
624 unsigned short len; /* Length of the data buffer */
625 unsigned char *data; /* Pointer to the data buffer */
626 };
627
628 /*
629 ** Recognised commands for the driver
630 */
631 #define DE4X5_GET_HWADDR 0x01 /* Get the hardware address */
632 #define DE4X5_SET_HWADDR 0x02 /* Get the hardware address */
633 #define DE4X5_SET_PROM 0x03 /* Set Promiscuous Mode */
634 #define DE4X5_CLR_PROM 0x04 /* Clear Promiscuous Mode */
635 #define DE4X5_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */
636 #define DE4X5_GET_MCA 0x06 /* Get a multicast address */
637 #define DE4X5_SET_MCA 0x07 /* Set a multicast address */
638 #define DE4X5_CLR_MCA 0x08 /* Clear a multicast address */
639 #define DE4X5_MCA_EN 0x09 /* Enable a multicast address group */
640 #define DE4X5_GET_STATS 0x0a /* Get the driver statistics */
641 #define DE4X5_CLR_STATS 0x0b /* Zero out the driver statistics */
642 #define DE4X5_GET_OMR 0x0c /* Get the OMR Register contents */
643 #define DE4X5_SET_OMR 0x0d /* Set the OMR Register contents */
644 #define DE4X5_GET_REG 0x0e /* Get the DE4X5 Registers */
645
646
647
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![[bottom]](../icons/n_bottom.png){kind=icon}
*/