drivers/scsi/aic7xxx.c

/* */
This source file includes following definitions.
debug
debug_config
aic7xxx_setup
aic7xxx_loadseq
aic7xxx_delay
rcs_version
aic7xxx_info
aic7xxx_putscb
aic7xxx_putdmascb
aic7xxx_getscb
aic7xxx_length
aic7xxx_scsirate
aic7xxx_isr
aic7xxx_probe
read_seeprom
detect_maxscb
aic7xxx_register
aic7xxx_detect
aic7xxx_buildscb
aic7xxx_queue
aic7xxx_kill
aic7xxx_abort
aic7xxx_reset
aic7xxx_biosparam
   1 /*+M*************************************************************************
   2  * Adaptec 274x/284x/294x device driver for Linux.
   3  *
   4  * Copyright (c) 1994 John Aycock
   5  *   The University of Calgary Department of Computer Science.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F
  22  * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA
  23  * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide,
  24  * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux,
  25  * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file
  26  * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual,
  27  * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the
  28  * ANSI SCSI-2 specification (draft 10c), ...
  29  *
  30  * ----------------------------------------------------------------
  31  *  Modified to include support for wide and twin bus adapters,
  32  *  DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes,
  33  *  and other rework of the code.
  34  *
  35  *  Parts of this driver are based on the FreeBSD driver by Justin
  36  *  T. Gibbs.
  37  *
  38  *  A Boot time option was also added for not resetting the scsi bus.
  39  *
  40  *    Form:  aic7xxx=extended,no_reset
  41  *
  42  *    -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95
  43  *
  44  *  $Id: aic7xxx.c,v 2.0 1995/08/02 05:28:42 deang Exp $
  45  *-M*************************************************************************/
  46 
  47 #ifdef MODULE
  48 #include <linux/module.h>
  49 #endif
  50 
  51 #include <stdarg.h>
  52 #include <asm/io.h>
  53 #include <linux/string.h>
  54 #include <linux/errno.h>
  55 #include <linux/kernel.h>
  56 #include <linux/ioport.h>
  57 #include <linux/bios32.h>
  58 #include <linux/delay.h>
  59 #include <linux/sched.h>
  60 #include <linux/pci.h>
  61 #include <linux/proc_fs.h>
  62 #include "../block/blk.h"
  63 #include "sd.h"
  64 #include "scsi.h"
  65 #include "hosts.h"
  66 #include "aic7xxx.h"
  67 #include<linux/stat.h>
  68 
  69 struct proc_dir_entry proc_scsi_aic7xxx = {
  70     PROC_SCSI_AIC7XXX, 7, "aic7xxx",
  71     S_IFDIR | S_IRUGO | S_IXUGO, 2
  72 };
  73 
  74 #define AIC7XXX_C_VERSION  "$Revision: 2.0 $"
  75 
  76 #define NUMBER(arr)     (sizeof(arr) / sizeof(arr[0]))
  77 #define MIN(a,b)        ((a < b) ? a : b)
  78 #ifndef TRUE
  79 #  define TRUE 1
  80 #endif
  81 #ifndef FALSE
  82 #  define FALSE 0
  83 #endif
  84 
  85 /*
  86  * Defines for PCI bus support, testing twin bus support, DMAing of
  87  * SCBs, and tagged queueing.
  88  *
  89  *   o PCI bus support - this has been implemented and working since
  90  *     the December 1, 1994 release of this driver. If you don't have
  91  *     a PCI bus and do not wish to configure your kernel with PCI
  92  *     support, then make sure this define is set to the cprrect
  93  *     define for PCI support (CONFIG_PCI) and configure your kernel
  94  *     without PCI support (make config).
  95  *
  96  *   o Twin bus support - this has been tested and does work.
  97  *
  98  *   o DMAing of SCBs - thanks to Kai Makisara, this now works
  99  *
 100  *   o Tagged queueing - this driver is capable of tagged queueing
 101  *     but I am unsure as to how well the higher level driver implements
 102  *     tagged queueing. Therefore, the maximum commands per lun is
 103  *     set to 2. If you want to implement tagged queueing, ensure
 104  *     this define is not commented out.
 105  *
 106  *   o Sharing IRQs - allowed for sharing of IRQs. This will allow
 107  *     for multiple aic7xxx host adapters sharing the same IRQ, but
 108  *     not for sharing IRQs with other devices. The higher level
 109  *     PCI code and interrupt handling needs to be modified to
 110  *     support this.
 111  *
 112  *  Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95
 113  */
 114 
 115 /* Uncomment this for testing twin bus support. */
 116 #define AIC7XXX_TWIN_SUPPORT
 117 
 118 /* Uncomment this for DMAing of SCBs. */
 119 #define AIC7XXX_USE_DMA
 120 
 121 /* Uncomment this for tagged queueing. */
 122 /* #define AIC7XXX_TAGGED_QUEUEING */
 123 
 124 /* Uncomment this for allowing sharing of IRQs. */
 125 #define AIC7XXX_SHARE_IRQS
 126 
 127 /* Set this to the delay in seconds after SCSI bus reset. */
 128 #define AIC7XXX_RESET_DELAY 15
 129 
 130 /*
 131  * Uncomment this to always use scatter/gather lists.
 132  * *NOTE: The sequencer must be changed also!
 133  */
 134 #define AIC7XXX_USE_SG
 135 
 136 /*
 137  * Controller type and options
 138  */
 139 typedef enum {
 140   AIC_NONE,
 141   AIC_274x,    /* EISA aic7770 */
 142   AIC_284x,    /* VLB  aic7770 */
 143   AIC_7870,    /* PCI  aic7870 */
 144   AIC_7850,    /* PCI  aic7850 */
 145   AIC_7872     /* PCI  aic7870 on 394x */
 146 } aha_type;
 147 
 148 typedef enum {
 149   AIC_SINGLE,  /* Single Channel */
 150   AIC_TWIN,    /* Twin Channel */
 151   AIC_WIDE     /* Wide Channel */
 152 } aha_bus_type;
 153 
 154 typedef enum {
 155   AIC_UNKNOWN,
 156   AIC_ENABLED,
 157   AIC_DISABLED
 158 } aha_status_type;
 159 
 160 /*
 161  * There should be a specific return value for this in scsi.h, but
 162  * it seems that most drivers ignore it.
 163  */
 164 #define DID_UNDERFLOW   DID_ERROR
 165 
 166 /*
 167  *  What we want to do is have the higher level scsi driver requeue
 168  *  the command to us. There is no specific driver status for this
 169  *  condition, but the higher level scsi driver will requeue the
 170  *  command on a DID_BUS_BUSY error.
 171  */
 172 #define DID_RETRY_COMMAND DID_BUS_BUSY
 173 
 174 /*
 175  * EISA/VL-bus stuff
 176  */
 177 #define MINSLOT         1
 178 #define MAXSLOT         15
 179 #define SLOTBASE(x)     ((x) << 12)
 180 #define MAXIRQ          15
 181 
 182 /*
 183  * Standard EISA Host ID regs  (Offset from slot base)
 184  */
 185 #define HID0(x)         ((x) + 0xC80)   /* 0,1: msb of ID2, 2-7: ID1      */
 186 #define HID1(x)         ((x) + 0xC81)   /* 0-4: ID3, 5-7: LSB ID2         */
 187 #define HID2(x)         ((x) + 0xC82)   /* product                        */
 188 #define HID3(x)         ((x) + 0xC83)   /* firmware revision              */
 189 
 190 /*
 191  * AIC-7770 I/O range to reserve for a card
 192  */
 193 #define MINREG(x)       ((x) + 0xC00ul)
 194 #define MAXREG(x)       ((x) + 0xCBFul)
 195 
 196 /* -------------------- AIC-7770 offset definitions ----------------------- */
 197 
 198 /*
 199  * SCSI Sequence Control (p. 3-11).
 200  * Each bit, when set starts a specific SCSI sequence on the bus
 201  */
 202 #define SCSISEQ(x)              ((x) + 0xC00ul)
 203 #define         TEMODEO         0x80
 204 #define         ENSELO          0x40
 205 #define         ENSELI          0x20
 206 #define         ENRSELI         0x10
 207 #define         ENAUTOATNO      0x08
 208 #define         ENAUTOATNI      0x04
 209 #define         ENAUTOATNP      0x02
 210 #define         SCSIRSTO        0x01
 211 
 212 /*
 213  * SCSI Transfer Control 1 Register (pp. 3-14,15).
 214  * Controls the SCSI module data path.
 215  */
 216 #define SXFRCTL1(x)             ((x) + 0xC02ul)
 217 #define         BITBUCKET       0x80
 218 #define         SWRAPEN         0x40
 219 #define         ENSPCHK         0x20
 220 #define         STIMESEL        0x18
 221 #define         ENSTIMER        0x04
 222 #define         ACTNEGEN        0x02
 223 #define         STPWEN          0x01            /* Powered Termination */
 224 
 225 /*
 226  * SCSI Control Signal Read Register (p. 3-15).
 227  * Reads the actual state of the SCSI bus pins
 228  */
 229 #define SCSISIGI(x)             ((x) + 0xC03ul)
 230 #define         CDI             0x80
 231 #define         IOI             0x40
 232 #define         MSGI            0x20
 233 #define         ATNI            0x10
 234 #define         SELI            0x08
 235 #define         BSYI            0x04
 236 #define         REQI            0x02
 237 #define         ACKI            0x01
 238 
 239 /*
 240  * SCSI Contol Signal Write Register (p. 3-16).
 241  * Writing to this register modifies the control signals on the bus. Only
 242  * those signals that are allowed in the current mode (Initiator/Target) are
 243  * asserted.
 244  */
 245 #define SCSISIGO(x)             ((x) + 0xC03ul)
 246 #define         CDO             0x80
 247 #define         IOO             0x40
 248 #define         MSGO            0x20
 249 #define         ATNO            0x10
 250 #define         SELO            0x08
 251 #define         BSYO            0x04
 252 #define         REQO            0x02
 253 #define         ACKO            0x01
 254 
 255 /*
 256  * SCSI Rate
 257  */
 258 #define SCSIRATE(x)             ((x) + 0xC04ul)
 259 
 260 /*
 261  * SCSI ID (p. 3-18).
 262  * Contains the ID of the board and the current target on the
 263  * selected channel
 264  */
 265 #define SCSIID(x)               ((x) + 0xC05ul)
 266 #define         TID             0xF0            /* Target ID mask */
 267 #define         OID             0x0F            /* Our ID mask */
 268 
 269 /*
 270  * SCSI Status 0 (p. 3-21)
 271  * Contains one set of SCSI Interrupt codes
 272  * These are most likely of interest to the sequencer
 273  */
 274 #define SSTAT0(x)               ((x) + 0xC0Bul)
 275 #define         TARGET          0x80            /* Board is a target */
 276 #define         SELDO           0x40            /* Selection Done */
 277 #define         SELDI           0x20            /* Board has been selected */
 278 #define         SELINGO         0x10            /* Selection In Progress */
 279 #define         SWRAP           0x08            /* 24bit counter wrap */
 280 #define         SDONE           0x04            /* STCNT = 0x000000 */
 281 #define         SPIORDY         0x02            /* SCSI PIO Ready */
 282 #define         DMADONE         0x01            /* DMA transfer completed */
 283 
 284 /*
 285  * Clear SCSI Interrupt 1 (p. 3-23)
 286  * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 287  */
 288 #define CLRSINT1(x)             ((x) + 0xC0Cul)
 289 #define         CLRSELTIMEO     0x80
 290 #define         CLRATNO         0x40
 291 #define         CLRSCSIRSTI     0x20
 292 /*  UNUSED                      0x10 */
 293 #define         CLRBUSFREE      0x08
 294 #define         CLRSCSIPERR     0x04
 295 #define         CLRPHASECHG     0x02
 296 #define         CLRREQINIT      0x01
 297 
 298 /*
 299  * SCSI Status 1 (p. 3-24)
 300  * These interrupt bits are of interest to the kernel driver
 301  */
 302 #define SSTAT1(x)               ((x) + 0xC0Cul)
 303 #define         SELTO           0x80
 304 #define         ATNTARG         0x40
 305 #define         SCSIRSTI        0x20
 306 #define         PHASEMIS        0x10
 307 #define         BUSFREE         0x08
 308 #define         SCSIPERR        0x04
 309 #define         PHASECHG        0x02
 310 #define         REQINIT         0x01
 311 
 312 /*
 313  * SCSI Interrrupt Mode 1 (pp. 3-28,29).
 314  * Set bits in this register enable the corresponding
 315  * interrupt source.
 316  */
 317 #define SIMODE1(x)              ((x) + 0xC11ul)
 318 #define         ENSELTIMO       0x80
 319 #define         ENATNTARG       0x40
 320 #define         ENSCSIRST       0x20
 321 #define         ENPHASEMIS      0x10
 322 #define         ENBUSFREE       0x08
 323 #define         ENSCSIPERR      0x04
 324 #define         ENPHASECHG      0x02
 325 #define         ENREQINIT       0x01
 326 
 327 /*
 328  * Selection/Reselection ID (p. 3-31)
 329  * Upper four bits are the device id. The ONEBIT is set when the re/selecting
 330  * device did not set its own ID.
 331  */
 332 #define SELID(x)                ((x) + 0xC19ul)
 333 #define         SELID_MASK      0xF0
 334 #define         ONEBIT          0x08
 335 /*  UNUSED                      0x07 */
 336 
 337 /*
 338  * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 339  * Controls the reading and writing of an external serial 1-bit
 340  * EEPROM Device.  In order to access the serial EEPROM, you must
 341  * first set the SEEMS bit that generates a request to the memory
 342  * port for access to the serial EEPROM device.  When the memory
 343  * port is not busy servicing another request, it reconfigures
 344  * to allow access to the serial EEPROM.  When this happens, SEERDY
 345  * gets set high to verify that the memory port access has been
 346  * granted.  See aic7xxx_read_eprom for detailed information on
 347  * the protocol necessary to read the serial EEPROM.
 348  */
 349 #define SEECTL(x)               ((x) + 0xC1Eul)
 350 #define         EXTARBACK       0x80
 351 #define         EXTARBREQ       0x40
 352 #define         SEEMS           0x20
 353 #define         SEERDY          0x10
 354 #define         SEECS           0x08
 355 #define         SEECK           0x04
 356 #define         SEEDO           0x02
 357 #define         SEEDI           0x01
 358 
 359 /*
 360  * SCSI Block Control (p. 3-32)
 361  * Controls Bus type and channel selection. In a twin channel configuration
 362  * addresses 0x00-0x1E are gated to the appropriate channel based on this
 363  * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
 364  * on a wide bus.
 365  */
 366 #define SBLKCTL(x)              ((x) + 0xC1Ful)
 367 /*  UNUSED                      0xC0 */
 368 #define         AUTOFLUSHDIS    0x20            /* used for Rev C check */
 369 /*  UNUSED                      0x10 */
 370 #define         SELBUSB         0x08
 371 /*  UNUSED                      0x04 */
 372 #define         SELWIDE         0x02
 373 /*  UNUSED                      0x01 */
 374 #define         SELSINGLE       0x00
 375 
 376 /*
 377  * Sequencer Control (p. 3-33)
 378  * Error detection mode and speed configuration
 379  */
 380 #define SEQCTL(x)               ((x) + 0xC60ul)
 381 #define         PERRORDIS       0x80
 382 #define         PAUSEDIS        0x40
 383 #define         FAILDIS         0x20
 384 #define         FASTMODE        0x10
 385 #define         BRKADRINTEN     0x08
 386 #define         STEP            0x04
 387 #define         SEQRESET        0x02
 388 #define         LOADRAM         0x01
 389 
 390 /*
 391  * Sequencer RAM Data (p. 3-34)
 392  * Single byte window into the Scratch Ram area starting at the address
 393  * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
 394  * four bytes in sucessesion. The SEQADDRs will increment after the most
 395  * significant byte is written
 396  */
 397 #define SEQRAM(x)               ((x) + 0xC61ul)
 398 
 399 /*
 400  * Sequencer Address Registers (p. 3-35)
 401  * Only the first bit of SEQADDR1 holds addressing information
 402  */
 403 #define SEQADDR0(x)             ((x) + 0xC62ul)
 404 #define SEQADDR1(x)             ((x) + 0xC63ul)
 405 
 406 #define ACCUM(x)                ((x) + 0xC64ul)         /* accumulator */
 407 
 408 /*
 409  * Board Control (p. 3-43)
 410  */
 411 #define BCTL(x)                 ((x) + 0xC84ul)
 412 /*   RSVD                       0xF0 */
 413 #define         ACE             0x08    /* Support for external processors */
 414 /*   RSVD                       0x06 */
 415 #define         ENABLE          0x01
 416 
 417 /*
 418  * Bus On/Off Time (p. 3-44)
 419  */
 420 #define BUSTIME(x)              ((x) + 0xC85ul)
 421 #define         BOFF            0xF0
 422 #define         BON             0x0F
 423 
 424 /*
 425  * Bus Speed (p. 3-45)
 426  */
 427 #define BUSSPD(x)               ((x) + 0xC86ul)
 428 #define         DFTHRSH         0xC0
 429 #define         STBOFF          0x38
 430 #define         STBON           0x07
 431 
 432 /*
 433  * Host Control (p. 3-47) R/W
 434  * Overal host control of the device.
 435  */
 436 #define HCNTRL(x)               ((x) + 0xC87ul)
 437 /*    UNUSED                    0x80 */
 438 #define         POWRDN          0x40
 439 /*    UNUSED                    0x20 */
 440 #define         SWINT           0x10
 441 #define         IRQMS           0x08
 442 #define         PAUSE           0x04
 443 #define         INTEN           0x02
 444 #define         CHIPRST         0x01
 445 #define         REQ_PAUSE       IRQMS | PAUSE | INTEN
 446 #define         UNPAUSE_274X    IRQMS | INTEN
 447 #define         UNPAUSE_284X    INTEN
 448 #define         UNPAUSE_294X    IRQMS | INTEN
 449 
 450 /*
 451  * SCB Pointer (p. 3-49)
 452  * Gate one of the four SCBs into the SCBARRAY window.
 453  */
 454 #define SCBPTR(x)               ((x) + 0xC90ul)
 455 
 456 /*
 457  * Interrupt Status (p. 3-50)
 458  * Status for system interrupts
 459  */
 460 #define INTSTAT(x)              ((x) + 0xC91ul)
 461 #define         SEQINT_MASK     0xF0            /* SEQINT Status Codes */
 462 #define                 BAD_PHASE       0x00
 463 #define                 SEND_REJECT     0x10
 464 #define                 NO_IDENT        0x20
 465 #define                 NO_MATCH        0x30
 466 #define                 MSG_SDTR        0x40
 467 #define                 MSG_WDTR        0x50
 468 #define                 MSG_REJECT      0x60
 469 #define                 BAD_STATUS      0x70
 470 #define                 RESIDUAL        0x80
 471 #define                 ABORT_TAG       0x90
 472 #define                 AWAITING_MSG    0xa0
 473 #define         BRKADRINT 0x08
 474 #define         SCSIINT   0x04
 475 #define         CMDCMPLT  0x02
 476 #define         SEQINT    0x01
 477 #define         INT_PEND  (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
 478 
 479 /*
 480  * Hard Error (p. 3-53)
 481  * Reporting of catastrophic errors. You usually cannot recover from
 482  * these without a full board reset.
 483  */
 484 #define ERROR(x)                ((x) + 0xC92ul)
 485 /*    UNUSED                    0xF0 */
 486 #define         PARERR          0x08
 487 #define         ILLOPCODE       0x04
 488 #define         ILLSADDR        0x02
 489 #define         ILLHADDR        0x01
 490 
 491 /*
 492  * Clear Interrupt Status (p. 3-52)
 493  */
 494 #define CLRINT(x)               ((x) + 0xC92ul)
 495 #define         CLRBRKADRINT    0x08
 496 #define         CLRSCSIINT      0x04
 497 #define         CLRCMDINT       0x02
 498 #define         CLRSEQINT       0x01
 499 
 500 /*
 501  * SCB Auto Increment (p. 3-59)
 502  * Byte offset into the SCB Array and an optional bit to allow auto
 503  * incrementing of the address during download and upload operations
 504  */
 505 #define SCBCNT(x)               ((x) + 0xC9Aul)
 506 #define         SCBAUTO         0x80
 507 #define         SCBCNT_MASK     0x1F
 508 
 509 /*
 510  * Queue In FIFO (p. 3-60)
 511  * Input queue for queued SCBs (commands that the seqencer has yet to start)
 512  */
 513 #define QINFIFO(x)              ((x) + 0xC9Bul)
 514 
 515 /*
 516  * Queue In Count (p. 3-60)
 517  * Number of queued SCBs
 518  */
 519 #define QINCNT(x)               ((x) + 0xC9Cul)
 520 
 521 /*
 522  * Queue Out FIFO (p. 3-61)
 523  * Queue of SCBs that have completed and await the host
 524  */
 525 #define QOUTFIFO(x)             ((x) + 0xC9Dul)
 526 
 527 /*
 528  * Queue Out Count (p. 3-61)
 529  * Number of queued SCBs in the Out FIFO
 530  */
 531 #define QOUTCNT(x)              ((x) + 0xC9Eul)
 532 
 533 #define SCBARRAY(x)             ((x) + 0xCA0ul)
 534 
 535 /* ---------------- END AIC-7770 Register Definitions ----------------- */
 536 
 537 /* --------------------- AIC-7870-only definitions -------------------- */
 538 
 539 #define DSPCISTATUS(x)          ((x) + 0xC86ul)
 540 #define         DFTHRESH        0xC0
 541 
 542 /* Scratch RAM offset definitions */
 543 
 544 /* ---------------------- Scratch RAM Offsets ------------------------- */
 545 /* These offsets are either to values that are initialized by the board's
 546  * BIOS or are specified by the Linux sequencer code. If I can figure out
 547  * how to read the EISA configuration info at probe time, the cards could
 548  * be run without BIOS support installed
 549  */
 550 
 551 /*
 552  * 1 byte per target starting at this address for configuration values
 553  */
 554 #define HA_TARG_SCRATCH(x)      ((x) + 0xC20ul)
 555 
 556 /*
 557  * The sequencer will stick the first byte of any rejected message here so
 558  * we can see what is getting thrown away.
 559  */
 560 #define HA_REJBYTE(x)           ((x) + 0xC31ul)
 561 
 562 /*
 563  * Bit vector of targets that have disconnection disabled.
 564  */
 565 #define HA_DISC_DSB             ((x) + 0xc32ul)
 566 
 567 /*
 568  * Length of pending message
 569  */
 570 #define HA_MSG_LEN(x)           ((x) + 0xC34ul)
 571 
 572 /*
 573  * Outgoing Message Body
 574  */
 575 #define HA_MSG_START(x)         ((x) + 0xC35ul)
 576 
 577 /*
 578  * These are offsets into the card's scratch ram. Some of the values are
 579  * specified in the AHA2742 technical reference manual and are initialized
 580  * by the BIOS at boot time.
 581  */
 582 #define HA_ARG_1(x)             ((x) + 0xC4Aul) /* sdtr <-> rate parameters */
 583 #define HA_RETURN_1(x)          ((x) + 0xC4Aul)
 584 #define         SEND_SENSE      0x80
 585 #define         SEND_SDTR       0x80
 586 #define         SEND_WDTR       0x80
 587 #define         SEND_REJ        0x40
 588 
 589 #define HA_SIGSTATE(x)          ((x) + 0xC4Bul) /* value in SCSISIGO */
 590 #define HA_SCBCOUNT(x)          ((x) + 0xC52ul) /* number of hardware SCBs */
 591 
 592 #define HA_FLAGS(x)             ((x) + 0xC53ul) /* TWIN and WIDE bus flags */
 593 #define         SINGLE_BUS      0x00
 594 #define         TWIN_BUS        0x01
 595 #define         WIDE_BUS        0x02
 596 #define         ACTIVE_MSG      0x20
 597 #define         IDENTIFY_SEEN   0x40
 598 #define         RESELECTING     0x80
 599 
 600 #define HA_ACTIVE0(x)           ((x) + 0xC54ul) /* Active bits; targets 0-7 */
 601 #define HA_ACTIVE1(x)           ((x) + 0xC55ul) /* Active bits; targets 8-15 */
 602 #define SAVED_TCL(x)            ((x) + 0xC56ul) /* Saved target, channel, LUN */
 603 #define WAITING_SCBH(x)         ((x) + 0xC57ul) /* Head of disconnected targets list. */
 604 #define WAITING_SCBT(x)         ((x) + 0xC58ul) /* Tail of disconnected targets list. */
 605 
 606 #define HA_SCSICONF(x)          ((x) + 0xC5Aul) /* SCSI config register */
 607 #define HA_INTDEF(x)            ((x) + 0xC5Cul) /* interrupt def'n register */
 608 #define HA_HOSTCONF(x)          ((x) + 0xC5Dul) /* host config def'n register */
 609 
 610 #define MSG_ABORT               0x06
 611 #define MSG_BUS_DEVICE_RESET    0x0c
 612 #define BUS_8_BIT               0x00
 613 #define BUS_16_BIT              0x01
 614 #define BUS_32_BIT              0x02
 615 
 616 
 617 /*
 618  *
 619  * Define the format of the SEEPROM registers (16 bits).
 620  *
 621  */
 622 struct seeprom_config {
 623 
 624 /*
 625  * SCSI ID Configuration Flags
 626  */
 627 #define CFXFER          0x0007          /* synchronous transfer rate */
 628 #define CFSYNCH         0x0008          /* enable synchronous transfer */
 629 #define CFDISC          0x0010          /* enable disconnection */
 630 #define CFWIDEB         0x0020          /* wide bus device */
 631 /* UNUSED               0x00C0 */
 632 #define CFSTART         0x0100          /* send start unit SCSI command */
 633 #define CFINCBIOS       0x0200          /* include in BIOS scan */
 634 #define CFRNFOUND       0x0400          /* report even if not found */
 635 /* UNUSED               0xF800 */
 636   unsigned short device_flags[16];      /* words 0-15 */
 637 
 638 /*
 639  * BIOS Control Bits
 640  */
 641 #define CFSUPREM        0x0001          /* support all removeable drives */
 642 #define CFSUPREMB       0x0002          /* support removeable drives for boot only */
 643 #define CFBIOSEN        0x0004          /* BIOS enabled */
 644 /* UNUSED               0x0008 */
 645 #define CFSM2DRV        0x0010          /* support more than two drives */
 646 /* UNUSED               0x0060 */
 647 #define CFEXTEND        0x0080          /* extended translation enabled */
 648 /* UNUSED               0xFF00 */
 649   unsigned short bios_control;          /* word 16 */
 650 
 651 /*
 652  * Host Adapter Control Bits
 653  */
 654 /* UNUSED               0x0003 */
 655 #define CFWSTERM        0x0008          /* SCSI high byte termination (wide card) */
 656 #define CFSTERM         0x0004          /* SCSI low byte termination (non-wide cards) */
 657 #define CFSPARITY       0x0010          /* SCSI parity */
 658 /* UNUSED               0x0020 */
 659 #define CFRESETB        0x0040          /* reset SCSI bus at IC initialization */
 660 /* UNUSED               0xFF80 */
 661   unsigned short adapter_control;       /* word 17 */
 662 
 663 /*
 664  * Bus Release, Host Adapter ID
 665  */
 666 #define CFSCSIID        0x000F          /* host adapter SCSI ID */
 667 /* UNUSED               0x00F0 */
 668 #define CFBRTIME        0xFF00          /* bus release time */
 669   unsigned short brtime_id;             /* word 18 */
 670 
 671 /*
 672  * Maximum targets
 673  */
 674 #define CFMAXTARG       0x00FF  /* maximum targets */
 675 /* UNUSED               0xFF00 */
 676   unsigned short max_targets;           /* word 19 */
 677 
 678   unsigned short res_1[11];             /* words 20-30 */
 679   unsigned short checksum;              /* word 31 */
 680 
 681 };
 682 
 683 
 684 #define AIC7XXX_DEBUG
 685 
 686 /*
 687  * Pause the sequencer and wait for it to actually stop - this
 688  * is important since the sequencer can disable pausing for critical
 689  * sections.
 690  */
 691 #define PAUSE_SEQUENCER(p) \
 692   outb(p->pause, HCNTRL(p->base));                      \
 693   while ((inb(HCNTRL(p->base)) & PAUSE) == 0)           \
 694     ;                                                   \
 695 
 696 /*
 697  * Unpause the sequencer. Unremarkable, yet done often enough to
 698  * warrant an easy way to do it.
 699  */
 700 #define UNPAUSE_SEQUENCER(p) \
 701   outb(p->unpause, HCNTRL(p->base))
 702 
 703 /*
 704  * Restart the sequencer program from address zero
 705  */
 706 #define RESTART_SEQUENCER(p) \
 707   do {                                                  \
 708     outb(SEQRESET | FASTMODE, SEQCTL(p->base)); \
 709   } while (inb(SEQADDR0(p->base)) != 0 &&               \
 710            inb(SEQADDR1(p->base)) != 0);                \
 711   UNPAUSE_SEQUENCER(p);
 712 
 713 /*
 714  * If an error occurs during a data transfer phase, run the comand
 715  * to completion - it's easier that way - making a note of the error
 716  * condition in this location. This then will modify a DID_OK status
 717  * into an appropriate error for the higher-level SCSI code.
 718  */
 719 #define aic7xxx_error(cmd)      ((cmd)->SCp.Status)
 720 
 721 /*
 722  * Keep track of the targets returned status.
 723  */
 724 #define aic7xxx_status(cmd)     ((cmd)->SCp.sent_command)
 725 
 726 /*
 727  * The position of the SCSI commands scb within the scb array.
 728  */
 729 #define aic7xxx_position(cmd)   ((cmd)->SCp.have_data_in)
 730 
 731 /*
 732  * Since the sequencer code DMAs the scatter-gather structures
 733  * directly from memory, we use this macro to assert that the
 734  * kernel structure hasn't changed.
 735  */
 736 #define SG_STRUCT_CHECK(sg) \
 737   ((char *)&(sg).address - (char *)&(sg) != 0 ||  \
 738    (char *)&(sg).length  - (char *)&(sg) != 8 ||  \
 739    sizeof((sg).address) != 4 ||                   \
 740    sizeof((sg).length)  != 4 ||                   \
 741    sizeof(sg)           != 12)
 742 
 743 /*
 744  * "Static" structures. Note that these are NOT initialized
 745  * to zero inside the kernel - we have to initialize them all
 746  * explicitly.
 747  *
 748  * We support multiple adapter cards per interrupt, but keep a
 749  * linked list of Scsi_Host structures for each IRQ.  On an interrupt,
 750  * use the IRQ as an index into aic7xxx_boards[] to locate the card
 751  * information.
 752  */
 753 static struct Scsi_Host *aic7xxx_boards[MAXIRQ + 1];
 754 
 755 /*
 756  * When we detect and register the card, it is possible to
 757  * have the card raise a spurious interrupt.  Because we need
 758  * to support multiple cards, we cannot tell which card caused
 759  * the spurious interrupt.  And, we might not even have added
 760  * the card info to the linked list at the time the spurious
 761  * interrupt gets raised.  This variable is suppose to keep track
 762  * of when we are registering a card and how many spurious
 763  * interrupts we have encountered.
 764  *
 765  *   0 - do not allow spurious interrupts.
 766  *   1 - allow 1 spurious interrupt
 767  *   2 - have 1 spurious interrupt, do not allow any more.
 768  *
 769  * I've made it an integer instead of a boolean in case we
 770  * want to allow more than one spurious interrupt for debugging
 771  * purposes.  Otherwise, it could just go from true to false to
 772  * true (or something like that).
 773  *
 774  * When the driver detects the cards, we'll set the count to 1
 775  * for each card detection and registration.  After the registration
 776  * of a card completes, we'll set the count back to 0.  So far, it
 777  * seems to be enough to allow a spurious interrupt only during
 778  * card registration; if a spurious interrupt is going to occur,
 779  * this is where it happens.
 780  *
 781  * We should be able to find a way to avoid getting the spurious
 782  * interrupt.  But until we do, we have to keep this ugly code.
 783  */
 784 static int aic7xxx_spurious_count;
 785 
 786 /*
 787  * The driver keeps up to four scb structures per card in memory. Only the
 788  * first 26 bytes of the structure are valid for the hardware, the rest used
 789  * for driver level bookeeping. The driver is further optimized
 790  * so that we only have to download the first 19 bytes since as long
 791  * as we always use S/G, the last fields should be zero anyway.
 792  */
 793 #ifdef AIC7XXX_USE_SG
 794 #define SCB_DOWNLOAD_SIZE       19      /* amount to actually download */
 795 #else
 796 #define SCB_DOWNLOAD_SIZE       26
 797 #endif
 798 
 799 #define SCB_UPLOAD_SIZE         19      /* amount to actually upload */
 800 
 801 struct aic7xxx_scb {
 802 /* ------------    Begin hardware supported fields    ---------------- */
 803 /*1 */  unsigned char control;
 804 #define SCB_NEEDWDTR 0x80                       /* Initiate Wide Negotiation */
 805 #define SCB_NEEDSDTR 0x40                       /* Initiate Sync Negotiation */
 806 #define SCB_NEEDDMA  0x08                       /* SCB needs to be DMA'd from
 807                                                  * from host memory
 808                                                  */
 809 #define SCB_REJ_MDP      0x80                   /* Reject MDP message */
 810 #define SCB_DISEN        0x40                   /* SCB Disconnect enable */
 811 #define SCB_TE           0x20                   /* Tag enable */
 812 /*      RESERVED         0x10 */
 813 #define SCB_WAITING      0x08                   /* Waiting */
 814 #define SCB_DIS          0x04                   /* Disconnected */
 815 #define SCB_TAG_TYPE     0x03
 816 #define         SIMPLE_QUEUE 0x00               /* Simple Queue */
 817 #define         HEAD_QUEUE   0x01               /* Head of Queue */
 818 #define         ORD_QUEUE    0x02               /* Ordered Queue */
 819 /*              ILLEGAL      0x03 */
 820 /*2 */  unsigned char target_channel_lun;       /* 4/1/3 bits */
 821 /*3 */  unsigned char SG_segment_count;
 822 /*7 */  unsigned char SG_list_pointer[4] __attribute__ ((packed));
 823 /*11*/  unsigned char SCSI_cmd_pointer[4] __attribute__ ((packed));
 824 /*12*/  unsigned char SCSI_cmd_length;
 825 /*14*/  unsigned char RESERVED[2];              /* must be zero */
 826 /*15*/  unsigned char target_status;
 827 /*18*/  unsigned char residual_data_count[3];
 828 /*19*/  unsigned char residual_SG_segment_count;
 829 /*23*/  unsigned char data_pointer[4] __attribute__ ((packed));
 830 /*26*/  unsigned char data_count[3];
 831 /*30*/  unsigned char host_scb[4] __attribute__ ((packed));
 832 /*31*/  u_char next_waiting;            /* Used to thread SCBs awaiting selection. */
 833 #define SCB_LIST_NULL 0x10              /* SCB list equivelent to NULL */
 834 #if 0
 835         /*
 836          *  No real point in transferring this to the
 837          *  SCB registers.
 838          */
 839         unsigned char RESERVED[1];
 840 #endif
 841 
 842         /*-----------------end of hardware supported fields----------------*/
 843         struct aic7xxx_scb *next;       /* next ptr when in free list */
 844         Scsi_Cmnd          *cmd;        /* Scsi_Cmnd for this scb */
 845         int                 state;      /* current state of scb */
 846 #define SCB_FREE               0x00
 847 #define SCB_ACTIVE             0x01
 848 #define SCB_ABORTED            0x02
 849 #define SCB_DEVICE_RESET       0x04
 850 #define SCB_IMMED              0x08
 851 #define SCB_SENSE              0x10
 852         unsigned int        position;       /* Position in scb array */
 853 #ifdef AIC7XXX_USE_SG
 854         struct scatterlist  sg;
 855         struct scatterlist  sense_sg;
 856 #endif
 857         unsigned char       sense_cmd[6];   /* Allocate 6 characters for sense command */
 858 };
 859 
 860 static struct {
 861   unsigned char errno;
 862   const char *errmesg;
 863 } hard_error[] = {
 864   { ILLHADDR,  "Illegal Host Access" },
 865   { ILLSADDR,  "Illegal Sequencer Address referrenced" },
 866   { ILLOPCODE, "Illegal Opcode in sequencer program" },
 867   { PARERR,    "Sequencer Ram Parity Error" }
 868 };
 869 
 870 static unsigned char
 871 generic_sense[] = { REQUEST_SENSE, 0, 0, 0, 255, 0 };
 872 
 873 /*
 874  * The maximum number of SCBs we could have for ANY type
 875  * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE
 876  * SEQUENCER CODE IF THIS IS MODIFIED!
 877  */
 878 #define AIC7XXX_MAXSCB  16
 879 
 880 /*
 881  * Define a structure used for each host adapter, only one per IRQ.
 882  */
 883 struct aic7xxx_host {
 884   int                      base;             /* card base address */
 885   int                      maxscb;           /* hardware SCBs */
 886   int                      numscb;           /* current number of scbs */
 887   int                      extended;         /* extended xlate? */
 888   aha_type                 type;             /* card type */
 889   aha_bus_type             bus_type;         /* normal/twin/wide bus */
 890   unsigned char            a_scanned;        /* 0 not scanned, 1 scanned */
 891   unsigned char            b_scanned;        /* 0 not scanned, 1 scanned */
 892   unsigned int             isr_count;        /* Interrupt count */
 893   volatile unsigned char   unpause;          /* unpause value for HCNTRL */
 894   volatile unsigned char   pause;            /* pause value for HCNTRL */
 895   volatile unsigned short  needsdtr_copy;    /* default config */
 896   volatile unsigned short  needsdtr;
 897   volatile unsigned short  sdtr_pending;
 898   volatile unsigned short  needwdtr_copy;    /* default config */
 899   volatile unsigned short  needwdtr;
 900   volatile unsigned short  wdtr_pending;
 901   struct seeprom_config    seeprom;
 902   int                      have_seeprom;
 903   struct Scsi_Host        *next;             /* allow for multiple IRQs */
 904   struct aic7xxx_scb       scb_array[AIC7XXX_MAXSCB];  /* active commands */
 905   struct aic7xxx_scb      *free_scb;         /* list of free SCBs */
 906 };
 907 
 908 struct aic7xxx_host_config {
 909   int              irq;        /* IRQ number */
 910   int              base;       /* I/O base */
 911   int              maxscb;     /* hardware SCBs */
 912   int              unpause;    /* unpause value for HCNTRL */
 913   int              pause;      /* pause value for HCNTRL */
 914   int              scsi_id;    /* host SCSI ID */
 915   int              scsi_id_b;  /* host SCSI ID B channel for twin cards */
 916   int              extended;   /* extended xlate? */
 917   int              busrtime;   /* bus release time */
 918   aha_type         type;       /* card type */
 919   aha_bus_type     bus_type;   /* normal/twin/wide bus */
 920   aha_status_type  parity;     /* bus parity enabled/disabled */
 921   aha_status_type  low_term;   /* bus termination low byte */
 922   aha_status_type  high_term;  /* bus termination high byte (wide cards only) */
 923 };
 924 
 925 /*
 926  * Valid SCSIRATE values. (p. 3-17)
 927  * Provides a mapping of tranfer periods in ns to the proper value to
 928  * stick in the scsiscfr reg to use that transfer rate.
 929  */
 930 static struct {
 931   short period;
 932   short rate;
 933   const char *english;
 934 } aic7xxx_syncrates[] = {
 935   { 100,   0,  "10.0" },
 936   { 125,   1,  "8.0"  },
 937   { 150,   2,  "6.67" },
 938   { 175,   3,  "5.7"  },
 939   { 200,   4,  "5.0"  },
 940   { 225,   5,  "4.4"  },
 941   { 250,   6,  "4.0"  },
 942   { 275,   7,  "3.6"  }
 943 };
 944 
 945 static int num_aic7xxx_syncrates =
 946     sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
 947 
 948 #ifdef AIC7XXX_DEBUG
 949 
 950 static void
 951 debug(const char *fmt, ...)
     /*  */
 952 {
 953   va_list ap;
 954   char buf[256];
 955 
 956   va_start(ap, fmt);
 957   vsprintf(buf, fmt, ap);
 958   printk(buf);
 959   va_end(ap);
 960 }
 961 
 962 static void
 963 debug_config(struct aic7xxx_host_config *p)
     /*  */
 964 {
 965   int host_conf, scsi_conf;
 966   unsigned char brelease;
 967   unsigned char dfthresh;
 968 
 969   static int DFT[] = { 0, 50, 75, 100 };
 970   static int SST[] = { 256, 128, 64, 32 };
 971   static const char *BUSW[] = { "", "-TWIN", "-WIDE" };
 972 
 973   host_conf = inb(HA_HOSTCONF(p->base));
 974   scsi_conf = inb(HA_SCSICONF(p->base));
 975 
 976   /*
 977    * The 7870 gets the bus release time and data FIFO threshold
 978    * from the serial EEPROM (stored in the config structure) and
 979    * scsi_conf register respectively.  The 7770 gets the bus
 980    * release time and data FIFO threshold from the scsi_conf and
 981    * host_conf registers respectively.
 982    */
 983   if ((p->type == AIC_274x) || (p->type == AIC_284x))
 984   {
 985     dfthresh = host_conf >> 6;
 986   }
 987   else
 988   {
 989     dfthresh = scsi_conf >> 6;
 990   }
 991 
 992   brelease = p->busrtime;
 993   if (brelease == 0)
 994   {
 995     brelease = 2;
 996   }
 997 
 998   switch (p->type)
 999   {
1000     case AIC_274x:
1001       printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1002       break;
1003 
1004     case AIC_284x:
1005       printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1006       break;
1007 
1008     case AIC_7870:
1009       printk("AIC7870%s (PCI-bus):\n", BUSW[p->bus_type]);
1010       break;
1011 
1012     case AIC_7850:
1013       printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
1014       break;
1015 
1016     case AIC_7872:
1017       printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
1018       break;
1019 
1020     default:
1021       panic("aic7xxx debug_config: internal error\n");
1022   }
1023 
1024   printk("    irq %d\n"
1025          "    bus release time %d bclks\n"
1026          "    data fifo threshold %d%%\n",
1027          p->irq,
1028          brelease,
1029          DFT[dfthresh]);
1030 
1031   printk("    SCSI CHANNEL A:\n"
1032          "        scsi id %d\n"
1033          "        scsi selection timeout %d ms\n"
1034          "        scsi bus reset at power-on %sabled\n",
1035          scsi_conf & 0x07,
1036          SST[(scsi_conf >> 3) & 0x03],
1037          (scsi_conf & 0x40) ? "en" : "dis");
1038 
1039   if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
1040   { /* Set the parity for 7770 based cards. */
1041     p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
1042   }
1043   if (p->parity != AIC_UNKNOWN)
1044   {
1045     printk("        scsi bus parity %sabled\n",
1046            (p->parity == AIC_ENABLED) ? "en" : "dis");
1047   }
1048 
1049   if (p->type == AIC_274x)
1050   {
1051     p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
1052   }
1053   if (p->low_term != AIC_UNKNOWN)
1054   {
1055     printk("        scsi bus termination (low byte) %sabled\n",
1056           (p->low_term == AIC_ENABLED) ? "en" : "dis");
1057   }
1058   if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1059   {
1060     printk("        scsi bus termination (high byte) %sabled\n",
1061           (p->high_term == AIC_ENABLED) ? "en" : "dis");
1062   }
1063 }
1064 #else
1065 #  define debug(fmt, args...)
1066 #  define debug_config(x)
1067 #endif AIC7XXX_DEBUG
1068 
1069 /*
1070  * XXX - these options apply unilaterally to _all_ 274x/284x/294x
1071  *       cards in the system. This should be fixed, but then,
1072  *       does anyone really have more than one in a machine?
1073  */
1074 static int aic7xxx_extended = 0;        /* extended translation on? */
1075 static int aic7xxx_no_reset = 0;        /* no resetting of SCSI bus */
1076 
1077 /*+F*************************************************************************
1078  * Function:
1079  *   aic7xxx_setup
1080  *
1081  * Description:
1082  *   Handle Linux boot parameters.
1083  *-F*************************************************************************/
1084 void
1085 aic7xxx_setup(char *s, int *dummy)
     /*  */
1086 {
1087   int   i;
1088   char *p;
1089 
1090   static struct {
1091     const char *name;
1092     int *flag;
1093   } options[] = {
1094     { "extended",    &aic7xxx_extended },
1095     { "no_reset",    &aic7xxx_no_reset },
1096     { NULL,          NULL}
1097   };
1098 
1099   for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1100   {
1101     for (i = 0; options[i].name; i++)
1102     {
1103       if (!strcmp(options[i].name, p))
1104       {
1105         *(options[i].flag) = !0;
1106       }
1107     }
1108   }
1109 }
1110 
1111 /*+F*************************************************************************
1112  * Function:
1113  *   aic7xxx_loadseq
1114  *
1115  * Description:
1116  *   Load the sequencer code into the controller memory.
1117  *-F*************************************************************************/
1118 static void
1119 aic7xxx_loadseq(int base)
     /*  */
1120 {
1121   static unsigned char seqprog[] = {
1122     /*
1123      * Each sequencer instruction is 29 bits
1124      * long (fill in the excess with zeroes)
1125      * and has to be loaded from least -> most
1126      * significant byte, so this table has the
1127      * byte ordering reversed.
1128      */
1129 #   include "aic7xxx_seq.h"
1130   };
1131 
1132   /*
1133    * When the AIC-7770 is paused (as on chip reset), the
1134    * sequencer address can be altered and a sequencer
1135    * program can be loaded by writing it, byte by byte, to
1136    * the sequencer RAM port - the Adaptec documentation
1137    * recommends using REP OUTSB to do this, hence the inline
1138    * assembly. Since the address autoincrements as we load
1139    * the program, reset it back to zero afterward. Disable
1140    * sequencer RAM parity error detection while loading, and
1141    * make sure the LOADRAM bit is enabled for loading.
1142    */
1143   outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1144 
1145   asm volatile("cld\n\t"
1146                "rep\n\t"
1147                "outsb"
1148                : /* no output */
1149                :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1150                :"si", "cx", "dx");
1151 
1152   /*
1153    * WARNING!  This is a magic sequence!  After extensive
1154    * experimentation, it seems that you MUST turn off the
1155    * LOADRAM bit before you play with SEQADDR again, else
1156    * you will end up with parity errors being flagged on
1157    * your sequencer program. (You would also think that
1158    * turning off LOADRAM and setting SEQRESET to reset the
1159    * address to zero would work, but you need to do it twice
1160    * for it to take effect on the address. Timing problem?)
1161    */
1162   do {
1163     /*
1164      * Actually, reset it until
1165      * the address shows up as
1166      * zero just to be safe..
1167      */
1168     outb(SEQRESET | FASTMODE, SEQCTL(base));
1169   } while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1170 }
1171 
1172 /*+F*************************************************************************
1173  * Function:
1174  *   aic7xxx_delay
1175  *
1176  * Description:
1177  *   Delay for specified amount of time.
1178  *-F*************************************************************************/
1179 static void
1180 aic7xxx_delay(int seconds)
     /*  */
1181 {
1182   unsigned long i;
1183 
1184   i = jiffies + (seconds * HZ);  /* compute time to stop */
1185 
1186   while (jiffies < i)
1187   {
1188     ;  /* Do nothing! */
1189   }
1190 }
1191 
1192 /*+F*************************************************************************
1193  * Function:
1194  *   rcs_version
1195  *
1196  * Description:
1197  *   Return a string containing just the RCS version number from either
1198  *   an Id or Revison RCS clause.
1199  *-F*************************************************************************/
1200 const char *
1201 rcs_version(const char *version_info)
     /*  */
1202 {
1203   static char buf[10];
1204   char *bp, *ep;
1205 
1206   bp = NULL;
1207   strcpy(buf, "????");
1208   if (!strncmp(version_info, "$Id: ", 5))
1209   {
1210     if ((bp = strchr(version_info, ' ')) != NULL)
1211     {
1212       bp++;
1213       if ((bp = strchr(bp, ' ')) != NULL)
1214       {
1215         bp++;
1216       }
1217     }
1218   }
1219   else
1220   {
1221     if (!strncmp(version_info, "$Revision: ", 11))
1222     {
1223       if ((bp = strchr(version_info, ' ')) != NULL)
1224       {
1225         bp++;
1226       }
1227     }
1228   }
1229 
1230   if (bp != NULL)
1231   {
1232     if ((ep = strchr(bp, ' ')) != NULL)
1233     {
1234       register int len = ep - bp;
1235 
1236       strncpy(buf, bp, len);
1237       buf[len] = '\0';
1238     }
1239   }
1240 
1241   return buf;
1242 }
1243 
1244 /*+F*************************************************************************
1245  * Function:
1246  *   aic7xxx_info
1247  *
1248  * Description:
1249  *   Return a string describing the driver.
1250  *-F*************************************************************************/
1251 const char *
1252 aic7xxx_info(struct Scsi_Host *notused)
     /*  */
1253 {
1254   static char buffer[128];
1255 
1256   strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1257   strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1258   strcat(buffer, "/");
1259   strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1260   strcat(buffer, "/");
1261   strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1262 
1263   return buffer;
1264 }
1265 
1266 /*+F*************************************************************************
1267  * Function:
1268  *   aic7xxx_putscb
1269  *
1270  * Description:
1271  *   Transfer a SCB to the controller.
1272  *-F*************************************************************************/
1273 static void
1274 aic7xxx_putscb(int base, struct aic7xxx_scb *scb)
     /*  */
1275 {
1276 #ifdef AIC7XXX_USE_DMA
1277   /*
1278    * All we need to do, is to output the position
1279    * of the SCB in the SCBARRAY to the QINFIFO
1280    * of the host adapter.
1281    */
1282   outb(scb->position, QINFIFO(base));
1283 #else
1284   /*
1285    * By turning on the SCB auto increment, any reference
1286    * to the SCB I/O space postincrements the SCB address
1287    * we're looking at. So turn this on and dump the relevant
1288    * portion of the SCB to the card.
1289    */
1290   outb(SCBAUTO, SCBCNT(base));
1291 
1292   asm volatile("cld\n\t"
1293                "rep\n\t"
1294                "outsb"
1295                : /* no output */
1296                :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1297                :"si", "cx", "dx");
1298 
1299   outb(0, SCBCNT(base));
1300 #endif
1301 }
1302 
1303 /*+F*************************************************************************
1304  * Function:
1305  *   aic7xxx_putdmascb
1306  *
1307  * Description:
1308  *   DMA a SCB to the controller.
1309  *-F*************************************************************************/
1310 static void
1311 aic7xxx_putdmascb(int base, struct aic7xxx_scb *scb)
     /*  */
1312 {
1313   /*
1314    * By turning on the SCB auto increment, any reference
1315    * to the SCB I/O space postincrements the SCB address
1316    * we're looking at. So turn this on and dump the relevant
1317    * portion of the SCB to the card.
1318    */
1319   outb(SCBAUTO, SCBCNT(base));
1320 
1321   asm volatile("cld\n\t"
1322                "rep\n\t"
1323                "outsb"
1324                : /* no output */
1325                :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1326                :"si", "cx", "dx");
1327 
1328   outb(0, SCBCNT(base));
1329 }
1330 
1331 /*+F*************************************************************************
1332  * Function:
1333  *   aic7xxx_getscb
1334  *
1335  * Description:
1336  *   Get a SCB from the controller.
1337  *-F*************************************************************************/
1338 static void
1339 aic7xxx_getscb(int base, struct aic7xxx_scb *scb)
     /*  */
1340 {
1341   /*
1342    * This is almost identical to aic7xxx_putscb().
1343    */
1344   outb(SCBAUTO, SCBCNT(base));
1345 
1346   asm volatile("cld\n\t"
1347                "rep\n\t"
1348                "insb"
1349                : /* no output */
1350                :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1351                :"di", "cx", "dx");
1352 
1353   outb(0, SCBCNT(base));
1354 }
1355 
1356 /*+F*************************************************************************
1357  * Function:
1358  *   aic7xxx_length
1359  *
1360  * Description:
1361  *   How much data should be transferred for this SCSI command? Stop
1362  *   at segment sg_last if it's a scatter-gather command so we can
1363  *   compute underflow easily.
1364  *-F*************************************************************************/
1365 static unsigned
1366 aic7xxx_length(Scsi_Cmnd *cmd, int sg_last)
     /*  */
1367 {
1368   int i, segments;
1369   unsigned length;
1370   struct scatterlist *sg;
1371 
1372   segments = cmd->use_sg - sg_last;
1373   sg = (struct scatterlist *) cmd->buffer;
1374 
1375   if (cmd->use_sg)
1376   {
1377     for (i = length = 0; i < cmd->use_sg && i < segments; i++)
1378     {
1379       length += sg[i].length;
1380     }
1381   }
1382   else
1383   {
1384     length = cmd->request_bufflen;
1385   }
1386 
1387   return (length);
1388 }
1389 
1390 /*+F*************************************************************************
1391  * Function:
1392  *   aic7xxx_scsirate
1393  *
1394  * Description:
1395  *   Look up the valid period to SCSIRATE conversion in our table
1396  *-F*************************************************************************/
1397 static void
1398 aic7xxx_scsirate(unsigned char *scsirate, unsigned char period,
     /*  */
1399                  unsigned char offset, int target)
1400 {
1401   int i;
1402 
1403   for (i = 0; i < num_aic7xxx_syncrates; i++)
1404   {
1405     if ((aic7xxx_syncrates[i].period - period) >= 0)
1406     {
1407       *scsirate = (aic7xxx_syncrates[i].rate << 4) | (offset & 0x0F);
1408       printk("aic7xxx: target %d now synchronous at %sMb/s, offset = 0x%x\n",
1409              target, aic7xxx_syncrates[i].english, offset);
1410       return;
1411     }
1412   }
1413 
1414   /*
1415    * Default to asyncronous transfer
1416    */
1417   *scsirate = 0;
1418   printk("aic7xxx: target %d using asynchronous transfers\n", target);
1419 }
1420 
1421 /*+F*************************************************************************
1422  * Function:
1423  *   aic7xxx_isr
1424  *
1425  * Description:
1426  *   SCSI controller interrupt handler.
1427  *
1428  *   NOTE: Since we declared this using SA_INTERRUPT, interrupts should
1429  *         be disabled all through this function unless we say otherwise.
1430  *-F*************************************************************************/
1431 static void
1432 aic7xxx_isr(int irq, struct pt_regs * regs)
     /*  */
1433 {
1434   int base, intstat;
1435   struct aic7xxx_host *p;
1436   struct aic7xxx_scb *scb;
1437   unsigned char active, ha_flags, transfer;
1438   unsigned char scsi_id, bus_width;
1439   unsigned char offset, rate, scratch;
1440   unsigned char max_offset, rej_byte;
1441   unsigned char head, tail;
1442   unsigned short target_mask;
1443   long flags;
1444   void *addr;
1445   int actual;
1446   int target, tcl;
1447   int scbptr;
1448   Scsi_Cmnd *cmd;
1449 
1450   p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1451 
1452   /*
1453    * Search for the host with a pending interrupt.  If we can't find
1454    * one, then we've encountered a spurious interrupt.
1455    */
1456   while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
1457   {
1458     if (p->next == NULL)
1459     {
1460       p = NULL;
1461     }
1462     else
1463     {
1464       p = (struct aic7xxx_host *) p->next->hostdata;
1465     }
1466   }
1467 
1468   if (p == NULL)
1469   {
1470     if (aic7xxx_spurious_count == 1)
1471     {
1472       aic7xxx_spurious_count = 2;
1473       printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1474       return;
1475     }
1476     else
1477     {
1478       /*
1479        * The best we can do is to set p back to head of list and process
1480        * the erroneous interrupt - most likely a BRKADRINT.
1481        */
1482       p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1483     }
1484   }
1485 
1486   p->isr_count++; /* Keep track of interrupts for /proc/scsi */
1487 
1488   if ((p->a_scanned == 0) && (p->isr_count == 1))
1489   {
1490     /*
1491      * We must only have one card at this IRQ and it must have been
1492      * added to the board data before the spurious interrupt occurred.
1493      * It is sufficient that we check isr_count and not the spurious
1494      * interrupt count.
1495      */
1496     printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1497     return;
1498   }
1499 
1500   base = p->base;
1501   /*
1502    * Handle all the interrupt sources - especially for SCSI
1503    * interrupts, we won't get a second chance at them.
1504    */
1505   intstat = inb(INTSTAT(base));
1506 
1507   if (intstat & BRKADRINT)
1508   {
1509     int i;
1510     unsigned char errno = inb(ERROR(base));
1511 
1512     printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
1513     for (i = 0; i < NUMBER(hard_error); i++)
1514     {
1515       if (errno & hard_error[i].errno)
1516       {
1517         printk("  %s\n", hard_error[i].errmesg);
1518       }
1519     }
1520 
1521     panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
1522           inb(ERROR(base)),
1523           inb(SEQADDR1(base)) << 8 | inb(SEQADDR0(base)));
1524   }
1525 
1526   if (intstat & SEQINT)
1527   {
1528     /*
1529      * Although the sequencer is paused immediately on
1530      * a SEQINT, an interrupt for a SCSIINT or a CMDCMPLT
1531      * condition will have unpaused the sequencer before
1532      * this point.
1533      */
1534     PAUSE_SEQUENCER(p);
1535 
1536     switch (intstat & SEQINT_MASK)
1537     {
1538       case BAD_PHASE:
1539         panic("aic7xxx_isr: unknown scsi bus phase\n");
1540         break;
1541 
1542       case SEND_REJECT:
1543         rej_byte = inb(HA_REJBYTE(base));
1544         scsi_id = inb(SCSIID(base)) >> 0x04;
1545         scbptr = inb(SCBPTR(base));
1546         scb = &(p->scb_array[scbptr]);
1547         if (rej_byte != 0x20)
1548         {
1549           debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
1550                 rej_byte);
1551         }
1552         else
1553         {
1554           printk("aic7xxx_isr warning: Tagged message rejected for target %d,"
1555                  " channel %c.\n",
1556                  scsi_id, (inb(SBLKCTL(base)) & SELBUSB ? 'B': 'A'));
1557           scb->cmd->device->tagged_supported = 0;
1558           scb->cmd->device->tagged_queue = 0;
1559         }
1560         break;
1561 
1562       case NO_IDENT:
1563         panic("aic7xxx_isr: reconnecting target %d at seqaddr 0x%x "
1564               "didn't issue IDENTIFY message\n",
1565               (inb(SELID(base)) >> 4) & 0x0F,
1566               (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
1567         break;
1568 
1569       case NO_MATCH:
1570         tcl = inb(SCBARRAY(base) + 1);
1571         target = (tcl >> 4) & 0x0F;
1572         /* Purposefully mask off the top bit of targets 8-15. */
1573         target_mask = 0x01 << (target & 0x07);
1574 
1575         debug("aic7xxx_isr: sequencer couldn't find match "
1576               "for reconnecting target %d, channel %d, lun %d - "
1577               "issuing ABORT\n", target, (tcl & 0x08) >> 3, tcl & 0x07);
1578         if (tcl & 0x88)
1579         {
1580           /* Second channel stores its info in byte
1581            * two of HA_ACTIVE
1582            */
1583           active = inb(HA_ACTIVE1(base));
1584           active = active & ~(target_mask);
1585           outb(active, HA_ACTIVE1(base));
1586         }
1587         else
1588         {
1589           active = inb(HA_ACTIVE0(base));
1590           active = active & ~(target_mask);
1591           outb(active, HA_ACTIVE0(base));
1592         }
1593 #ifdef AIC7XXX_USE_DMA
1594         outb(SCB_NEEDDMA, SCBARRAY(base));
1595 #endif
1596 
1597         /*
1598          * Check out why this use to be outb(0x80, CLRINT(base))
1599          * clear the timeout
1600          */
1601         outb(CLRSELTIMEO, CLRSINT1(base));
1602         RESTART_SEQUENCER(p);
1603         break;
1604 
1605       case MSG_SDTR:
1606         /*
1607          * Help the sequencer to translate the negotiated
1608          * transfer rate. Transfer is 1/4 the period
1609          * in ns as is returned by the sync negotiation
1610          * message. So, we must multiply by four.
1611          */
1612         transfer = (inb(HA_ARG_1(base)) << 2);
1613         offset = inb(ACCUM(base));
1614         scsi_id = inb(SCSIID(base)) >> 0x04;
1615         if (inb(SBLKCTL(base)) & 0x08)
1616         {
1617           scsi_id = scsi_id + 8;  /* B channel */
1618         }
1619         target_mask = (0x01 << scsi_id);
1620         scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1621         /*
1622          * The maximum offset for a wide device is 0x08; for a
1623          * 8-bit bus device the maximum offset is 0x0f.
1624          */
1625         if (scratch & 0x80)
1626         {
1627           max_offset = 0x08;
1628         }
1629         else
1630         {
1631           max_offset = 0x0f;
1632         }
1633         aic7xxx_scsirate(&rate, transfer, MIN(offset, max_offset), scsi_id);
1634         /*
1635          * Preserve the wide transfer flag.
1636          */
1637         rate = rate | (scratch & 0x80);
1638         outb(rate, HA_TARG_SCRATCH(base) + scsi_id);
1639         outb(rate, SCSIRATE(base));
1640         if ((rate & 0xf) == 0)
1641         { /*
1642            * The requested rate was so low that asynchronous transfers
1643            * are faster (not to mention the controller won't support
1644            * them), so we issue a reject to ensure we go to asynchronous
1645            * transfers.
1646            */
1647            outb(SEND_REJ, HA_RETURN_1(base));
1648         }
1649         else
1650         {
1651           /*
1652            * See if we initiated Sync Negotiation
1653            */
1654           if (p->sdtr_pending & target_mask)
1655           {
1656             /*
1657              * Don't send an SDTR back to the target.
1658              */
1659             outb(0, HA_RETURN_1(base));
1660           }
1661           else
1662           {
1663             /*
1664              * Send our own SDTR in reply.
1665              */
1666             printk("aic7xxx_isr: Sending SDTR!!\n");
1667             outb(SEND_SDTR, HA_RETURN_1(base));
1668           }
1669         }
1670         /*
1671          * Clear the flags.
1672          */
1673         p->needsdtr = p->needsdtr & ~target_mask;
1674         p->sdtr_pending = p->sdtr_pending & ~target_mask;
1675         break;
1676 
1677       case MSG_WDTR:
1678       {
1679         bus_width = inb(ACCUM(base));
1680         scsi_id = inb(SCSIID(base)) >> 0x04;
1681         if (inb(SBLKCTL(base)) & 0x08)
1682         {
1683           scsi_id = scsi_id + 8;  /* B channel */
1684         }
1685         printk("aic7xxx_isr: Received MSG_WDTR, scsi_id = %d, "
1686                "needwdtr = 0x%x\n", scsi_id, p->needwdtr);
1687         scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1688 
1689         target_mask = (0x01 << scsi_id);
1690         if (p->wdtr_pending & target_mask)
1691         {
1692           /*
1693            * Don't send an WDTR back to the target, since we asked first.
1694            */
1695           outb(0, HA_RETURN_1(base));
1696           switch (bus_width)
1697           {
1698             case BUS_8_BIT:
1699               scratch = scratch & 0x7F;
1700               break;
1701 
1702             case BUS_16_BIT:
1703               printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1704                      scsi_id);
1705               scratch = scratch | 0x80;
1706               break;
1707           }
1708         }
1709         else
1710         {
1711           /*
1712            * Send our own WDTR in reply.
1713            */
1714           printk("aic7xxx_isr: Will send WDTR!!\n");
1715           switch (bus_width)
1716           {
1717             case BUS_8_BIT:
1718               scratch = scratch & 0x7F;
1719               break;
1720 
1721             case BUS_32_BIT:
1722               /* Negotiate 16 bits. */
1723               bus_width = BUS_16_BIT;
1724               /* Yes, we mean to fall thru here */
1725 
1726             case BUS_16_BIT:
1727               printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1728                      scsi_id);
1729               scratch = scratch | 0x80;
1730               break;
1731           }
1732           outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
1733         }
1734         p->needwdtr = p->needwdtr & ~target_mask;
1735         p->wdtr_pending = p->wdtr_pending & ~target_mask;
1736         outb(scratch, HA_TARG_SCRATCH(base) + scsi_id);
1737         outb(scratch, SCSIRATE(base));
1738         break;
1739       }
1740 
1741       case MSG_REJECT:
1742       {
1743         /*
1744          * What we care about here is if we had an
1745          * outstanding SDTR or WDTR message for this
1746          * target. If we did, this is a signal that
1747          * the target is refusing negotiation.
1748          */
1749 
1750         unsigned char targ_scratch, scsi_id;
1751         unsigned short mask;
1752 
1753         scsi_id = inb(SCSIID(base)) >> 0x04;
1754         if (inb(SBLKCTL(base)) & 0x08)
1755         {
1756           scsi_id = scsi_id + 8;
1757         }
1758 
1759         mask = (0x01 << scsi_id);
1760 
1761         targ_scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1762 
1763         if (p->wdtr_pending & mask)
1764         {
1765           /*
1766            * note 8bit xfers and clear flag
1767            */
1768           targ_scratch = targ_scratch & 0x7F;
1769           p->needwdtr = p->needwdtr & ~mask;
1770           p->wdtr_pending = p->wdtr_pending & ~mask;
1771           outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1772           printk("aic7xxx: target %d refusing WIDE negotiation. Using "
1773                  "8 bit transfers\n", scsi_id);
1774         }
1775         else
1776         {
1777           if (p->sdtr_pending & mask)
1778           {
1779             /*
1780              * note asynch xfers and clear flag
1781              */
1782             targ_scratch = targ_scratch & 0xF0;
1783             p->needsdtr = p->needsdtr & ~mask;
1784             p->sdtr_pending = p->sdtr_pending & ~mask;
1785             outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1786             printk("aic7xxx: target %d refusing syncronous negotiation. Using "
1787                    "asyncronous transfers\n", scsi_id);
1788           }
1789           /*
1790            * Otherwise, we ignore it.
1791            */
1792         }
1793         outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1794         outb(targ_scratch, SCSIRATE(base));
1795         break;
1796       }
1797 
1798       case BAD_STATUS:
1799         scsi_id = inb(SCSIID(base)) >> 0x04;
1800         scbptr = inb(SCBPTR(base));
1801         scb = &(p->scb_array[scbptr]);
1802         outb(0, HA_RETURN_1(base));   /* CHECK_CONDITION may change this */
1803         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1804         {
1805           printk("aic7xxx_isr: referenced scb not valid "
1806                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1807                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1808         }
1809         else
1810         {
1811           cmd = scb->cmd;
1812           aic7xxx_getscb(base, scb);
1813           aic7xxx_status(cmd) = scb->target_status;
1814 
1815           cmd->result = cmd->result | scb->target_status;
1816 
1817           /*
1818            * This test is just here for debugging purposes.
1819            * It will go away when the timeout problem is resolved.
1820            */
1821           switch (status_byte(scb->target_status))
1822           {
1823             case GOOD:
1824               break;
1825 
1826             case CHECK_CONDITION:
1827               if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
1828               {
1829                 void         *req_buf;
1830 #ifndef AIC7XXX_USE_SG
1831                 unsigned int  req_buflen;
1832 #endif
1833 
1834                 /* Update the timeout for the SCSI command. */
1835 /*                update_timeout(cmd, SENSE_TIMEOUT); */
1836 
1837                 /* Send a sense command to the requesting target. */
1838                 cmd->flags = cmd->flags | WAS_SENSE;
1839                 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
1840                        sizeof(generic_sense));
1841 
1842                 scb->sense_cmd[1] = cmd->lun << 5;
1843                 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
1844 
1845 #ifdef AIC7XXX_USE_SG
1846                 scb->sense_sg.address = (char *) &cmd->sense_buffer;
1847                 scb->sense_sg.length = sizeof(cmd->sense_buffer);
1848                 req_buf = &scb->sense_sg;
1849 #else
1850                 req_buf = &cmd->sense_buffer;
1851                 req_buflen = sizeof(cmd->sense_buffer);
1852 #endif
1853                 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
1854                 memset(scb, 0, SCB_DOWNLOAD_SIZE);
1855                 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
1856                     ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
1857                 addr = scb->sense_cmd;
1858                 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
1859                 memcpy(scb->SCSI_cmd_pointer, &addr,
1860                        sizeof(scb->SCSI_cmd_pointer));
1861 #ifdef AIC7XXX_USE_SG
1862                 scb->SG_segment_count = 1;
1863                 memcpy(scb->SG_list_pointer, &req_buf,
1864                         sizeof(scb->SG_list_pointer));
1865 #else
1866                 scb->SG_segment_count = 0;
1867                 memcpy(scb->data_pointer, &req_buf,
1868                         sizeof(scb->data_pointer));
1869                 memcpy(scb->data_count, &req_buflen, 3);
1870 #endif
1871 
1872                 outb(SCBAUTO, SCBCNT(base));
1873                 asm volatile("cld\n\t"
1874                              "rep\n\t"
1875                              "outsb"
1876                              : /* no output */
1877                              :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1878                              :"si", "cx", "dx");
1879                 outb(0, SCBCNT(base));
1880                 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
1881 
1882                 /*
1883                  * Add this SCB to the "waiting for selection" list.
1884                  */
1885                 head = inb(WAITING_SCBH(base));
1886                 tail = inb(WAITING_SCBT(base));
1887                 if (head & SCB_LIST_NULL)
1888                 { /* list is empty */
1889                   head = scb->position;
1890                   tail = SCB_LIST_NULL;
1891                 }
1892                 else
1893                 {
1894                   if (tail & SCB_LIST_NULL)
1895                   { /* list has one element */
1896                     tail = scb->position;
1897                     outb(head, SCBPTR(base));
1898                     outb(tail, (SCBARRAY(base) + 30));
1899                   }
1900                   else
1901                   { /* list has more than one element */
1902                     outb(tail, SCBPTR(base));
1903                     tail = scb->position;
1904                     outb(tail, (SCBARRAY(base) + 30));
1905                   }
1906                 }
1907                 outb(head, WAITING_SCBH(base));
1908                 outb(tail, WAITING_SCBT(base));
1909                 outb(SEND_SENSE, HA_RETURN_1(base));
1910               }  /* first time sense, no errors */
1911               else
1912               {
1913                 /*
1914                  * Indicate that we asked for sense, have the sequencer do
1915                  * a normal command complete, and have the scsi driver handle
1916                  * this condition.
1917                  */
1918                 cmd->flags = cmd->flags | ASKED_FOR_SENSE;
1919               }
1920               break;
1921 
1922             case BUSY:
1923               printk("aic7xxx_isr: Target busy\n");
1924               if (!aic7xxx_error(cmd))
1925               {
1926                 aic7xxx_error(cmd) = DID_BUS_BUSY;
1927               }
1928               break;
1929 
1930             case QUEUE_FULL:
1931               printk("aic7xxx_isr: Queue full\n");
1932               if (!aic7xxx_error(cmd))
1933               {
1934                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1935               }
1936               break;
1937 
1938             default:
1939               printk("aic7xxx_isr: Unexpected target status 0x%x\n",
1940                      scb->target_status);
1941               if (!aic7xxx_error(cmd))
1942               {
1943                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1944               }
1945               break;
1946           }  /* end switch */
1947         }  /* end else of */
1948         break;
1949 
1950       case RESIDUAL:
1951         scbptr = inb(SCBPTR(base));
1952         scb = &(p->scb_array[scbptr]);
1953         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1954         {
1955           printk("aic7xxx_isr: referenced scb not valid "
1956                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1957                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1958         }
1959         else
1960         {
1961           cmd = scb->cmd;
1962           /*
1963            *  Don't destroy valid residual information with
1964            *  residual coming from a check sense operation.
1965            */
1966           if (!(cmd->flags & WAS_SENSE))
1967           {
1968             /*
1969              *  We had an underflow. At this time, there's only
1970              *  one other driver that bothers to check for this,
1971              *  and cmd->underflow seems to be set rather half-
1972              *  heartedly in the higher-level SCSI code.
1973              */
1974             actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
1975 
1976             actual -= ((inb(SCBARRAY(base + 17)) << 16) |
1977                        (inb(SCBARRAY(base + 16)) <<  8) |
1978                        inb(SCBARRAY(base + 15)));
1979 
1980             if (actual < cmd->underflow)
1981             {
1982               printk("aic7xxx: target %d underflow - "
1983                      "wanted (at least) %u, got %u\n",
1984                      cmd->target, cmd->underflow, actual);
1985 
1986               aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1987               aic7xxx_status(cmd) = scb->target_status;
1988             }
1989           }
1990         }
1991         break;
1992 
1993       case ABORT_TAG:
1994         scbptr = inb(SCBPTR(base));
1995         scb = &(p->scb_array[scbptr]);
1996         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1997         {
1998           printk("aic7xxx_isr: referenced scb not valid "
1999                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2000                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
2001         }
2002         else
2003         {
2004           cmd = scb->cmd;
2005           /*
2006            * We didn't recieve a valid tag back from the target
2007            * on a reconnect.
2008            */
2009           printk("aic7xxx_isr: invalid tag recieved on channel %c "
2010                  "target %d, lun %d -- sending ABORT_TAG\n",
2011                   (cmd->channel & 0x01) ? 'B':'A',
2012                   cmd->target, cmd->lun & 0x07);
2013           /*
2014            *  This is a critical section, since we don't want the
2015            *  queue routine mucking with the host data.
2016            */
2017           save_flags(flags);
2018           cli();
2019 
2020           /*
2021            *  Process the command after marking the scb as free
2022            *  and adding it to the free list.
2023            */
2024           scb->state = SCB_FREE;
2025           scb->cmd = NULL;
2026           scb->next = p->free_scb;      /* preserve next pointer */
2027           p->free_scb = scb;            /* add at head of list */
2028 
2029           restore_flags(flags);
2030           cmd->result = (DID_RETRY_COMMAND << 16);
2031           cmd->scsi_done(cmd);
2032         }
2033         break;
2034 
2035       case AWAITING_MSG:
2036         scbptr = inb(SCBPTR(base));
2037         scb = &(p->scb_array[scbptr]);
2038         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2039         {
2040           printk("aic7xxx_isr: referenced scb not valid "
2041                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2042                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
2043         }
2044         else
2045         {
2046           /*
2047            * This SCB had a zero length command, informing the sequencer
2048            * that we wanted to send a special message to this target.
2049            * We only do this for BUS_DEVICE_RESET messages currently.
2050            */
2051            if (scb->state & SCB_DEVICE_RESET)
2052            {
2053              outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
2054              outb(1, HA_MSG_LEN(base));
2055            }
2056            else
2057            {
2058              panic("aic7xxx_isr: AWAITING_SCB for an SCB that does "
2059                    "not have a waiting message");
2060            }
2061         }
2062         break;
2063 
2064       default:               /* unknown */
2065         debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
2066               intstat, inb(SCSISIGI(base)));
2067         break;
2068     }
2069     outb(CLRSEQINT, CLRINT(base));
2070     UNPAUSE_SEQUENCER(p);
2071   }
2072 
2073   if (intstat & SCSIINT)
2074   {
2075     int status = inb(SSTAT1(base));
2076 
2077     scbptr = inb(SCBPTR(base));
2078     scb = &p->scb_array[scbptr];
2079     if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2080     {
2081       printk("aic7xxx_isr: no command for scb (scsiint)\n");
2082       /*
2083        * Turn off the interrupt and set status
2084        * to zero, so that it falls through the
2085        * reset of the SCSIINT code.
2086        */
2087       outb(status, CLRSINT1(base));
2088       UNPAUSE_SEQUENCER(p);
2089       outb(CLRSCSIINT, CLRINT(base));
2090       status = 0;
2091       scb = NULL;
2092     }
2093     else
2094     {
2095       cmd = scb->cmd;
2096 
2097       /*
2098        * Only the SCSI Status 1 register has information
2099        * about exceptional conditions that we'd have a
2100        * SCSIINT about; anything in SSTAT0 will be handled
2101        * by the sequencer. Note that there can be multiple
2102        * bits set.
2103        */
2104       if (status & SELTO)
2105       {
2106         unsigned char target_mask = (1 << (cmd->target & 0x07));
2107         unsigned char waiting;
2108 
2109         /*
2110          * Hardware selection timer has expired. Turn
2111          * off SCSI selection sequence.
2112          */
2113         outb(ENRSELI, SCSISEQ(base));
2114         cmd->result = (DID_TIME_OUT << 16);
2115         /*
2116          * Clear an pending messages for the timed out
2117          * target and mark the target as free.
2118          */
2119         ha_flags = inb(HA_FLAGS(base));
2120         outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2121 
2122         if (scb->target_channel_lun & 0x88)
2123         {
2124           active = inb(HA_ACTIVE1(base));
2125           active = active & ~(target_mask);
2126           outb(active, HA_ACTIVE1(base));
2127         }
2128         else
2129         {
2130           active = inb(HA_ACTIVE0(base));
2131           active = active & ~(target_mask);
2132           outb(active, HA_ACTIVE0(base));
2133         }
2134 
2135 #ifdef AIC7XXX_USE_DMA
2136         outb(SCB_NEEDDMA, SCBARRAY(base));
2137 #endif
2138 
2139         /*
2140          * Shut off the offending interrupt sources, reset
2141          * the sequencer address to zero and unpause it,
2142          * then call the high-level SCSI completion routine.
2143          *
2144          * WARNING!  This is a magic sequence!  After many
2145          * hours of guesswork, turning off the SCSI interrupts
2146          * in CLRSINT? does NOT clear the SCSIINT bit in
2147          * INTSTAT. By writing to the (undocumented, unused
2148          * according to the AIC-7770 manual) third bit of
2149          * CLRINT, you can clear INTSTAT. But, if you do it
2150          * while the sequencer is paused, you get a BRKADRINT
2151          * with an Illegal Host Address status, so the
2152          * sequencer has to be restarted first.
2153          */
2154         outb(CLRSELTIMEO, CLRSINT1(base));
2155 
2156         outb(CLRSCSIINT, CLRINT(base));
2157 
2158         /* Shift the waiting for selection queue forward */
2159         waiting = inb(WAITING_SCBH(base));
2160         outb(waiting, SCBPTR(base));
2161         waiting = inb(SCBARRAY(base) + 30);
2162         outb(waiting, WAITING_SCBH(base));
2163 
2164         RESTART_SEQUENCER(p);
2165         /*
2166          * This is a critical section, since we don't want the
2167          * queue routine mucking with the host data.
2168          */
2169         save_flags(flags);
2170         cli();
2171 
2172         /*
2173          * Process the command after marking the scb as free
2174          * and adding it to the free list.
2175          */
2176         scb->state = SCB_FREE;
2177         scb->cmd = NULL;
2178         scb->next = p->free_scb;        /* preserve next pointer */
2179         p->free_scb = scb;              /* add at head of list */
2180 
2181         restore_flags(flags);
2182 
2183         cmd->scsi_done(cmd);
2184 #if 0
2185   printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2186          scb->position, scb->state, (unsigned int) scb->cmd);
2187 #endif
2188       }
2189       else
2190       {
2191         if (status & SCSIPERR)
2192         {
2193           /*
2194            * A parity error has occurred during a data
2195            * transfer phase. Flag it and continue.
2196            */
2197           printk("aic7xxx: parity error on target %d, "
2198                  "channel %d, lun %d\n",
2199                  cmd->target,
2200                  cmd->channel & 0x01,
2201                  cmd->lun & 0x07);
2202           aic7xxx_error(cmd) = DID_PARITY;
2203 
2204           /*
2205            * Clear interrupt and resume as above.
2206            */
2207           outb(CLRSCSIPERR, CLRSINT1(base));
2208           UNPAUSE_SEQUENCER(p);
2209 
2210           outb(CLRSCSIINT, CLRINT(base));
2211           scb = NULL;
2212         }
2213         else
2214         {
2215           if (!(status & BUSFREE))
2216           {
2217              /*
2218               * We don't know what's going on. Turn off the
2219               * interrupt source and try to continue.
2220               */
2221              printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2222              outb(status, CLRSINT1(base));
2223              UNPAUSE_SEQUENCER(p);
2224              outb(CLRSCSIINT, CLRINT(base));
2225              scb = NULL;
2226           }
2227         }
2228       }
2229     }  /* else */
2230   }
2231 
2232   if (intstat & CMDCMPLT)
2233   {
2234     int complete;
2235 
2236     /*
2237      * The sequencer will continue running when it
2238      * issues this interrupt. There may be >1 commands
2239      * finished, so loop until we've processed them all.
2240      */
2241     do {
2242       complete = inb(QOUTFIFO(base));
2243 
2244       scb = &(p->scb_array[complete]);
2245       if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2246       {
2247         printk("aic7xxx warning: "
2248                "no command for scb %d (cmdcmplt)\n"
2249                "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x\n",
2250                complete, inb(QOUTFIFO(base)),
2251                scb->state, (unsigned int) scb->cmd);
2252         outb(CLRCMDINT, CLRINT(base));
2253         continue;
2254       }
2255       cmd = scb->cmd;
2256 
2257       cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2258       if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2259       { /* Got sense information. */
2260         cmd->flags = cmd->flags & ASKED_FOR_SENSE;
2261       }
2262 #if 0
2263       printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2264              scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2265 #endif
2266       /*
2267        * This is a critical section, since we don't want the
2268        * queue routine mucking with the host data.
2269        */
2270       save_flags(flags);
2271       cli();
2272 
2273       scb->state = SCB_FREE;
2274       scb->next = p->free_scb;
2275       scb->cmd = NULL;
2276       p->free_scb = &(p->scb_array[scb->position]);
2277 
2278       restore_flags(flags);
2279 #if 0
2280   if (scb != &p->scb_array[scb->position])
2281   {
2282     printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
2283   }
2284   printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2285          scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2286 #endif
2287 
2288       cmd->scsi_done(cmd);
2289 
2290       /*
2291        * Clear interrupt status before checking
2292        * the output queue again. This eliminates
2293        * a race condition whereby a command could
2294        * complete between the queue poll and the
2295        * interrupt clearing, so notification of the
2296        * command being complete never made it back
2297        * up to the kernel.
2298        */
2299       outb(CLRCMDINT, CLRINT(base));
2300     } while (inb(QOUTCNT(base)));
2301   }
2302 }
2303 
2304 /*+F*************************************************************************
2305  * Function:
2306  *   aic7xxx_probe
2307  *
2308  * Description:
2309  *   Probing for EISA boards: it looks like the first two bytes
2310  *   are a manufacturer code - three characters, five bits each:
2311  *
2312  *               BYTE 0   BYTE 1   BYTE 2   BYTE 3
2313  *              ?1111122 22233333 PPPPPPPP RRRRRRRR
2314  *
2315  *   The characters are baselined off ASCII '@', so add that value
2316  *   to each to get the real ASCII code for it. The next two bytes
2317  *   appear to be a product and revision number, probably vendor-
2318  *   specific. This is what is being searched for at each port,
2319  *   and what should probably correspond to the ID= field in the
2320  *   ECU's .cfg file for the card - if your card is not detected,
2321  *   make sure your signature is listed in the array.
2322  *
2323  *   The fourth byte's lowest bit seems to be an enabled/disabled
2324  *   flag (rest of the bits are reserved?).
2325  *-F*************************************************************************/
2326 static aha_type
2327 aic7xxx_probe(int slot, int base)
     /*  */
2328 {
2329   int i;
2330   unsigned char buf[4];
2331 
2332   static struct {
2333     int n;
2334     unsigned char signature[sizeof(buf)];
2335     aha_type type;
2336   } AIC7xxx[] = {
2337     { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x },  /* host adapter 274x */
2338     { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x },  /* motherboard 274x  */
2339     { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x },  /* 284x, BIOS enabled */
2340     { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x }   /* 284x, BIOS disabled */
2341   };
2342 
2343   /*
2344    * The VL-bus cards need to be primed by
2345    * writing before a signature check.
2346    */
2347   for (i = 0; i < sizeof(buf); i++)
2348   {
2349     outb(0x80 + i, base);
2350     buf[i] = inb(base + i);
2351   }
2352 
2353   for (i = 0; i < NUMBER(AIC7xxx); i++)
2354   {
2355     /*
2356      * Signature match on enabled card?
2357      */
2358     if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
2359     {
2360       if (inb(base + 4) & 1)
2361       {
2362         return (AIC7xxx[i].type);
2363       }
2364 
2365       printk("aic7xxx disabled at slot %d, ignored\n", slot);
2366     }
2367   }
2368 
2369   return (AIC_NONE);
2370 }
2371 
2372 /*+F*************************************************************************
2373  * Function:
2374  *   read_seeprom
2375  *
2376  * Description:
2377  *   Reads the serial EEPROM and returns 1 if successful and 0 if
2378  *   not successful.
2379  *
2380  *   The instruction set of the 93C46 chip is as follows:
2381  *
2382  *               Start  OP
2383  *     Function   Bit  Code  Address    Data     Description
2384  *     -------------------------------------------------------------------
2385  *     READ        1    10   A5 - A0             Reads data stored in memory,
2386  *                                               starting at specified address
2387  *     EWEN        1    00   11XXXX              Write enable must preceed
2388  *                                               all programming modes
2389  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
2390  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
2391  *     ERAL        1    00   10XXXX              Erase all registers
2392  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
2393  *     EWDS        1    00   00XXXX              Disables all programming
2394  *                                               instructions
2395  *     *Note: A value of X for address is a don't care condition.
2396  *
2397  *   The 93C46 has a four wire interface: clock, chip select, data in, and
2398  *   data out.  In order to perform one of the above functions, you need
2399  *   to enable the chip select for a clock period (typically a minimum of
2400  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
2401  *   respectively.  While the chip select remains high, you can clock in
2402  *   the instructions (above) starting with the start bit, followed by the
2403  *   OP code, Address, and Data (if needed).  For the READ instruction, the
2404  *   requested 16-bit register contents is read from the data out line but
2405  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
2406  *   first).  The clock cycling from low to high initiates the next data
2407  *   bit to be sent from the chip.
2408  *
2409  *   The 7870 interface to the 93C46 serial EEPROM is through the SEECTL
2410  *   register.  After successful arbitration for the memory port, the
2411  *   SEECS bit of the SEECTL register is connected to the chip select.
2412  *   The SEECK, SEEDO, and SEEDI are connected to the clock, data out,
2413  *   and data in lines respectively.  The SEERDY bit of SEECTL is useful
2414  *   in that it gives us an 800 nsec timer.  After a write to the SEECTL
2415  *   register, the SEERDY goes high 800 nsec later.  The one exception
2416  *   to this is when we first request access to the memory port.  The
2417  *   SEERDY goes high to signify that access has been granted and, for
2418  *   this case, has no implied timing.
2419  *
2420  *-F*************************************************************************/
2421 static int
2422 read_seeprom(int base, struct seeprom_config *sc)
     /*  */
2423 {
2424   int i = 0, k = 0;
2425   unsigned long timeout;
2426   unsigned char temp;
2427   unsigned short checksum = 0;
2428   unsigned short *seeprom = (unsigned short *) sc;
2429   struct seeprom_cmd {
2430     unsigned char len;
2431     unsigned char bits[3];
2432   };
2433   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
2434 
2435 #define CLOCK_PULSE(p) \
2436   while ((inb(SEECTL(base)) & SEERDY) == 0)     \
2437   {                                             \
2438     ;  /* Do nothing */                         \
2439   }
2440 
2441   /*
2442    * Request access of the memory port.  When access is
2443    * granted, SEERDY will go high.  We use a 1 second
2444    * timeout which should be near 1 second more than
2445    * is needed.  Reason: after the 7870 chip reset, there
2446    * should be no contention.
2447    */
2448   outb(SEEMS, SEECTL(base));
2449   timeout = jiffies + 100;  /* 1 second timeout */
2450   while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
2451   {
2452     ;  /* Do nothing!  Wait for access to be granted. */
2453   }
2454   if ((inb(SEECTL(base)) & SEERDY) == 0)
2455   {
2456     outb(0, SEECTL(base));
2457     return (0);
2458   }
2459 
2460   /*
2461    * Read the first 32 registers of the seeprom.  For the 7870,
2462    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
2463    * but only the first 32 are used by Adaptec BIOS.  The loop
2464    * will range from 0 to 31.
2465    */
2466   for (k = 0; k < (sizeof(*sc) / 2); k++)
2467   {
2468     /* Send chip select for one clock cycle. */
2469     outb(SEEMS | SEECK | SEECS, SEECTL(base));
2470     CLOCK_PULSE(base);
2471 
2472     /*
2473      * Now we're ready to send the read command followed by the
2474      * address of the 16-bit register we want to read.
2475      */
2476     for (i = 0; i < seeprom_read.len; i++)
2477     {
2478       temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
2479       outb(temp, SEECTL(base));
2480       CLOCK_PULSE(base);
2481       temp = temp ^ SEECK;
2482       outb(temp, SEECTL(base));
2483       CLOCK_PULSE(base);
2484     }
2485     /* Send the 6 bit address (MSB first, LSB last). */
2486     for (i = 5; i >= 0; i--)
2487     {
2488       temp = k;
2489       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
2490       temp = SEEMS | SEECS | (temp << 1);
2491       outb(temp, SEECTL(base));
2492       CLOCK_PULSE(base);
2493       temp = temp ^ SEECK;
2494       outb(temp, SEECTL(base));
2495       CLOCK_PULSE(base);
2496     }
2497 
2498     /*
2499      * Now read the 16 bit register.  An initial 0 precedes the
2500      * register contents which begins with bit 15 (MSB) and ends
2501      * with bit 0 (LSB).  The initial 0 will be shifted off the
2502      * top of our word as we let the loop run from 0 to 16.
2503      */
2504     for (i = 0; i <= 16; i++)
2505     {
2506       temp = SEEMS | SEECS;
2507       outb(temp, SEECTL(base));
2508       CLOCK_PULSE(base);
2509       temp = temp ^ SEECK;
2510       seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
2511       outb(temp, SEECTL(base));
2512       CLOCK_PULSE(base);
2513     }
2514 
2515     /*
2516      * The serial EEPROM has a checksum in the last word.  Keep a
2517      * running checksum for all words read except for the last
2518      * word.  We'll verify the checksum after all words have been
2519      * read.
2520      */
2521     if (k < (sizeof(*sc) / 2) - 1)
2522     {
2523       checksum = checksum + seeprom[k];
2524     }
2525 
2526     /* Reset the chip select for the next command cycle. */
2527     outb(SEEMS, SEECTL(base));
2528     CLOCK_PULSE(base);
2529     outb(SEEMS | SEECK, SEECTL(base));
2530     CLOCK_PULSE(base);
2531     outb(SEEMS, SEECTL(base));
2532     CLOCK_PULSE(base);
2533   }
2534 
2535   if (checksum != sc->checksum)
2536   {
2537     printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
2538     return (0);
2539   }
2540 
2541 #if 0
2542   printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
2543   printk("Serial EEPROM:");
2544   for (k = 0; k < (sizeof(*sc) / 2); k++)
2545   {
2546     if (((k % 8) == 0) && (k != 0))
2547     {
2548       printk("\n              ");
2549     }
2550     printk(" 0x%x", seeprom[k]);
2551   }
2552   printk("\n");
2553 #endif
2554 
2555   /* Release access to the memory port and the serial EEPROM. */
2556   outb(0, SEECTL(base));
2557   return (1);
2558 }
2559 
2560 /*+F*************************************************************************
2561  * Function:
2562  *   detect_maxscb
2563  *
2564  * Description:
2565  *   Return the maximum number of SCB's allowed for a given controller.
2566  *-F*************************************************************************/
2567 static int
2568 detect_maxscb(aha_type type, int base)
     /*  */
2569 {
2570   unsigned char sblkctl_reg;
2571   int maxscb = 0;
2572 
2573   switch (type)
2574   {
2575     case AIC_274x:
2576     case AIC_284x:
2577       /*
2578        * Check for Rev C or E boards. Rev E boards can supposedly have
2579        * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.
2580        * Until we know how to access more than 4 SCBs for the Rev E chips,
2581        * we limit them, along with the Rev C chips, to 4 SCBs.
2582        *
2583        * The Rev E boards have a read/write autoflush bit in the
2584        * SBLKCTL registor, while in the Rev C boards it is read only.
2585        */
2586       sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
2587       outb(sblkctl_reg, SBLKCTL(base));
2588       if (inb(SBLKCTL(base)) == sblkctl_reg)
2589       {  /* We detected a Rev E board. */
2590         printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
2591         outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
2592         maxscb = 4;
2593       }
2594       else
2595       {
2596         printk("aic7770: Rev C and previous; using 4 SCB's\n");
2597         maxscb = 4;
2598       }
2599       break;
2600 
2601     case AIC_7850:
2602       maxscb = 3;
2603       break;
2604 
2605     case AIC_7870:
2606       maxscb = 16;
2607       break;
2608 
2609     case AIC_7872:
2610       /*
2611        * Really has 255, but we'll wait to verify that we access
2612        * them the same way and do not have to set the card to
2613        * use the memory port to access external SCB RAM.
2614        */
2615       maxscb = 16;
2616       break;
2617 
2618     case AIC_NONE:
2619       /*
2620        * This should never happen... But just in case.
2621        */
2622       break;
2623   }
2624 
2625   return (maxscb);
2626 }
2627 
2628 /*+F*************************************************************************
2629  * Function:
2630  *   aic7xxx_register
2631  *
2632  * Description:
2633  *   Register a Adaptec aic7xxx chip SCSI controller with the kernel.
2634  *-F*************************************************************************/
2635 static int
2636 aic7xxx_register(Scsi_Host_Template *template, aha_type type,
     /*  */
2637                  int base, unsigned char irq)
2638 {
2639   static const char * board_name[] = {"", "274x", "284x", "7870", "7850", "7872"};
2640   int i;
2641   unsigned char sblkctl;
2642   int max_targets;
2643   int found = 1;
2644   unsigned char target_settings;
2645   unsigned char scsi_conf, host_conf;
2646   int have_seeprom = 0;
2647   struct Scsi_Host *host;
2648   struct aic7xxx_host *p;
2649   struct aic7xxx_host_config config;
2650   struct seeprom_config sc;
2651 
2652   config.type = type;
2653   config.base = base;
2654   config.irq = irq;
2655   config.parity = AIC_UNKNOWN;
2656   config.low_term = AIC_UNKNOWN;
2657   config.high_term = AIC_UNKNOWN;
2658   config.busrtime = 0;
2659 
2660   /*
2661    * Lock out other contenders for our i/o space.
2662    */
2663   request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
2664 
2665   switch (type)
2666   {
2667     case AIC_274x:
2668 #if 0
2669       printk("aha274x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2670 #endif
2671       /*
2672        * For some 274x boards, we must clear the CHIPRST bit
2673        * and pause the sequencer. For some reason, this makes
2674        * the driver work. For 284x boards, we give it a
2675        * CHIPRST just like the 294x boards.
2676        *
2677        * Use the BIOS settings to determine the interrupt
2678        * trigger type (level or edge) and use this value
2679        * for pausing and unpausing the sequencer.
2680        */
2681       config.unpause = (inb(HCNTRL(config.base)) & IRQMS) | INTEN;
2682       config.pause = config.unpause | PAUSE;
2683       config.extended = aic7xxx_extended;
2684 
2685       /*
2686        * I don't think we need to kick the reset again, the initial probe
2687        * does a reset, it seems that this is kicking a dead horse here.
2688        * So... I will try to just verify that the chip has come out of the
2689        * reset state and continue the same as the 284x.
2690        * In the Calgary version of the driver:
2691        *   1) Chip Reset
2692        *   2) Set unpause to IRQMS | INTEN
2693        *   3) If an interrupt occured without any commands queued, the
2694        *      unpause was set to just INTEN
2695        * I changed the initial reset code to just mask in the CHIPRST bit
2696        * and try to leave the other settings alone.
2697        *
2698        * I don't think we need the warning about chip reset not being clear.
2699        * On both my test machines (2842 & 2940), they work just fine with a
2700        * HCNTRL() of 0x5 (PAUSE | CHIPRST). Notice though, the 274x also
2701        * adds the INTEN flag, where neither the 284x or 294x do.
2702        */
2703       outb(config.pause | CHIPRST, HCNTRL(config.base));
2704       aic7xxx_delay(1);
2705       if (inb(HCNTRL(config.base)) & CHIPRST)
2706       {
2707         printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
2708       }
2709       outb(config.pause, HCNTRL(config.base));
2710 
2711       /*
2712        * Just to be on the safe side with the 274x, we will re-read the irq
2713        * since there was some issue about reseting the board.
2714        */
2715       config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2716       host_conf = inb(HA_HOSTCONF(config.base));
2717       config.busrtime = host_conf & 0x3C;
2718       /* XXX Is this valid for motherboard based controllers? */
2719       /* Setup the FIFO threshold and the bus off time */
2720       outb(host_conf & DFTHRSH, BUSSPD(config.base));
2721       outb((host_conf << 2) & BOFF, BUSTIME(config.base));
2722 
2723       /*
2724        * A reminder until this can be detected automatically.
2725        */
2726       printk("aha274x: extended translation %sabled\n",
2727              config.extended ? "en" : "dis");
2728       break;
2729 
2730     case AIC_284x:
2731 #if 0
2732       printk("aha284x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2733 #endif
2734       outb(CHIPRST, HCNTRL(config.base));
2735       config.unpause = UNPAUSE_284X;
2736       config.pause = REQ_PAUSE; /* DWG would like to be like the rest */
2737       config.extended = aic7xxx_extended;
2738       config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2739       host_conf = inb(HA_HOSTCONF(config.base));
2740       config.busrtime = host_conf & 0x3C;
2741       /* XXX Is this valid for motherboard based controllers? */
2742       /* Setup the FIFO threshold and the bus off time */
2743       outb(host_conf & DFTHRSH, BUSSPD(config.base));
2744       outb((host_conf << 2) & BOFF, BUSTIME(config.base));
2745 
2746       /*
2747        * A reminder until this can be detected automatically.
2748        */
2749       printk("aha284x: extended translation %sabled\n",
2750              config.extended ? "en" : "dis");
2751       break;
2752 
2753     case AIC_7850:
2754     case AIC_7870:
2755     case AIC_7872:
2756 #if 0
2757       printk("aic%s hcntrl=0x%x\n", board_name[type], inb(HCNTRL(config.base)));
2758 #endif
2759 
2760       outb(CHIPRST, HCNTRL(config.base));
2761       config.unpause = UNPAUSE_294X;
2762       config.pause = config.unpause | PAUSE;
2763       config.extended = aic7xxx_extended;
2764       config.scsi_id = 7;
2765 
2766       printk("aic78xx: Reading SEEPROM... ");
2767       have_seeprom = read_seeprom(base, &sc);
2768       if (!have_seeprom)
2769       {
2770         printk("aic78xx: unable to read SEEPROM\n");
2771       }
2772       else
2773       {
2774         printk("done\n");
2775         config.extended = (sc.bios_control & CFEXTEND) >> 7;
2776         config.scsi_id = (sc.brtime_id & CFSCSIID);
2777         config.parity = (sc.adapter_control & CFSPARITY) ?
2778                          AIC_ENABLED : AIC_DISABLED;
2779         config.low_term = (sc.adapter_control & CFSTERM) ?
2780                               AIC_ENABLED : AIC_DISABLED;
2781         config.high_term = (sc.adapter_control & CFWSTERM) ?
2782                               AIC_ENABLED : AIC_DISABLED;
2783         config.busrtime = (sc.brtime_id & CFBRTIME) >> 8;
2784       }
2785 
2786       /*
2787        * XXX - force data fifo threshold to 100%. Why does this
2788        *       need to be done?
2789        */
2790       outb(inb(DSPCISTATUS(config.base)) | DFTHRESH, DSPCISTATUS(config.base));
2791       outb(config.scsi_id | DFTHRESH, HA_SCSICONF(config.base));
2792 
2793       /*
2794        * In case we are a wide card, place scsi ID in second conf byte.
2795        */
2796       outb(config.scsi_id, (HA_SCSICONF(config.base) + 1));
2797 
2798       /*
2799        * A reminder until this can be detected automatically.
2800        */
2801       printk("aic%s: extended translation %sabled\n", board_name[type],
2802              config.extended ? "en" : "dis");
2803       break;
2804 
2805     default:
2806       panic("aic7xxx_register: internal error\n");
2807   }
2808 
2809   config.maxscb = detect_maxscb(type, base);
2810 
2811   if ((config.type == AIC_274x) || (config.type == AIC_284x))
2812   {
2813     if (config.pause & IRQMS)
2814     {
2815       printk("aic7xxx: Using Level Sensitive Interrupts\n");
2816     }
2817     else
2818     {
2819       printk("aic7xxx: Using Edge Triggered Interrupts\n");
2820     }
2821   }
2822 
2823   /*
2824    * Read the bus type from the SBLKCTL register. Set the FLAGS
2825    * register in the sequencer for twin and wide bus cards.
2826    */
2827   sblkctl = inb(SBLKCTL(base)) & 0x0F;  /* mask out upper two bits */
2828   switch (sblkctl)
2829   {
2830     case 0:     /* narrow/normal bus */
2831       config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2832       config.bus_type = AIC_SINGLE;
2833       outb(0, HA_FLAGS(base));
2834       break;
2835 
2836     case 2:     /* Wide bus */
2837       config.scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
2838       config.bus_type = AIC_WIDE;
2839       printk("aic7xxx: Enabling wide channel of %s-Wide\n",
2840              board_name[config.type]);
2841       outb(WIDE_BUS, HA_FLAGS(base));
2842       break;
2843 
2844     case 8:     /* Twin bus */
2845       config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2846 #ifdef AIC7XXX_TWIN_SUPPORT
2847       config.scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
2848       config.bus_type = AIC_TWIN;
2849       printk("aic7xxx: Enabled channel B of %s-Twin\n",
2850              board_name[config.type]);
2851       outb(TWIN_BUS, HA_FLAGS(base));
2852 #else
2853       config.bus_type = AIC_SINGLE;
2854       printk("aic7xxx: Channel B of %s-Twin will be ignored\n",
2855              board_name[config.type]);
2856       outb(0, HA_FLAGS(base));
2857 #endif
2858       break;
2859 
2860     default:
2861       printk("aic7xxx is an unsupported type 0x%x, please "
2862              "mail deang@ims.com\n", inb(SBLKCTL(base)));
2863       outb(0, HA_FLAGS(base));
2864       return (0);
2865   }
2866 
2867   /*
2868    * Clear the upper two bits. For the 294x cards, clearing the
2869    * upper two bits, will take the card out of diagnostic mode
2870    * and make the host adatper LED follow bus activity (will not
2871    * always be on).
2872    */
2873   outb(sblkctl, SBLKCTL(base));
2874 
2875   /*
2876    * The IRQ level in i/o port 4 maps directly onto the real
2877    * IRQ number. If it's ok, register it with the kernel.
2878    *
2879    * NB. the Adaptec documentation says the IRQ number is only
2880    *     in the lower four bits; the ECU information shows the
2881    *     high bit being used as well. Which is correct?
2882    *
2883    * The 294x cards (PCI) get their interrupt from PCI BIOS.
2884    */
2885   if (((config.type == AIC_274x) || (config.type == AIC_284x))
2886       && (config.irq < 9 || config.irq > 15))
2887   {
2888     printk("aic7xxx uses unsupported IRQ level, ignoring\n");
2889     return (0);
2890   }
2891 
2892   /*
2893    * Check the IRQ to see if it is shared by another aic7xxx
2894    * controller. If it is and sharing of IRQs is not defined,
2895    * then return 0 hosts found. If sharing of IRQs is allowed
2896    * or the IRQ is not shared by another host adapter, then
2897    * proceed.
2898    */
2899 #ifndef AIC7XXX_SHARE_IRQS
2900    if (aic7xxx_boards[config.irq] != NULL)
2901    {
2902      printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
2903      return (0);
2904    }
2905 #endif
2906 
2907   /*
2908    * Print out debugging information before re-enabling
2909    * the card - a lot of registers on it can't be read
2910    * when the sequencer is active.
2911    */
2912   debug_config(&config);
2913 
2914   /*
2915    * Before registry, make sure that the offsets of the
2916    * struct scatterlist are what the sequencer will expect,
2917    * otherwise disable scatter-gather altogether until someone
2918    * can fix it. This is important since the sequencer will
2919    * DMA elements of the SG array in while executing commands.
2920    */
2921   if (template->sg_tablesize != SG_NONE)
2922   {
2923     struct scatterlist sg;
2924 
2925     if (SG_STRUCT_CHECK(sg))
2926     {
2927       printk("aic7xxx warning: kernel scatter-gather "
2928              "structures changed, disabling it\n");
2929       template->sg_tablesize = SG_NONE;
2930     }
2931   }
2932 
2933   /*
2934    * Register each "host" and fill in the returned Scsi_Host
2935    * structure as best we can. Some of the parameters aren't
2936    * really relevant for bus types beyond ISA, and none of the
2937    * high-level SCSI code looks at it anyway. Why are the fields
2938    * there? Also save the pointer so that we can find the
2939    * information when an IRQ is triggered.
2940    */
2941   host = scsi_register(template, sizeof(struct aic7xxx_host));
2942   host->can_queue = config.maxscb;
2943 #ifdef AIC7XXX_TAGGED_QUEUEING
2944   host->cmd_per_lun = 2;
2945 #else
2946   host->cmd_per_lun = 1;
2947 #endif
2948   host->this_id = config.scsi_id;
2949   host->irq = config.irq;
2950   if (config.bus_type == AIC_WIDE)
2951   {
2952     host->max_id = 16;
2953   }
2954   if (config.bus_type == AIC_TWIN)
2955   {
2956     host->max_channel = 1;
2957   }
2958 
2959   p = (struct aic7xxx_host *) host->hostdata;
2960 
2961   /* Initialize the scb array by setting the state to free. */
2962   for (i = 0; i < AIC7XXX_MAXSCB; i++)
2963   {
2964     p->scb_array[i].state = SCB_FREE;
2965     p->scb_array[i].next = NULL;
2966     p->scb_array[i].cmd = NULL;
2967   }
2968 
2969   p->isr_count = 0;
2970   p->a_scanned = 0;
2971   p->b_scanned = 0;
2972   p->base = config.base;
2973   p->maxscb = config.maxscb;
2974   p->numscb = 0;
2975   p->extended = config.extended;
2976   p->type = config.type;
2977   p->bus_type = config.bus_type;
2978   p->have_seeprom = have_seeprom;
2979   p->seeprom = sc;
2980   p->free_scb = NULL;
2981   p->next = NULL;
2982 
2983   p->unpause = config.unpause;
2984   p->pause = config.pause;
2985 
2986   if (aic7xxx_boards[config.irq] == NULL)
2987   {
2988     /*
2989      * Warning! This must be done before requesting the irq.  It is
2990      * possible for some boards to raise an interrupt as soon as
2991      * they are enabled.  So when we request the irq from the Linux
2992      * kernel, an interrupt is triggered immediately.  Therefore, we
2993      * must ensure the board data is correctly set before the request.
2994      */
2995     aic7xxx_boards[config.irq] = host;
2996 
2997     /*
2998      * Register IRQ with the kernel.
2999      */
3000     if (request_irq(config.irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
3001     {
3002       printk("aic7xxx couldn't register irq %d, ignoring\n", config.irq);
3003       aic7xxx_boards[config.irq] = NULL;
3004       return (0);
3005     }
3006   }
3007   else
3008   {
3009     /*
3010      * We have found a host adapter sharing an IRQ of a previously
3011      * registered host adapter. Add this host adapter's Scsi_Host
3012      * to the beginning of the linked list of hosts at the same IRQ.
3013      */
3014     p->next = aic7xxx_boards[config.irq];
3015     aic7xxx_boards[config.irq] = host;
3016   }
3017 
3018   /*
3019    * Load the sequencer program, then re-enable the board -
3020    * resetting the AIC-7770 disables it, leaving the lights
3021    * on with nobody home. On the PCI bus you *may* be home,
3022    * but then your mailing address is dynamically assigned
3023    * so no one can find you anyway :-)
3024    */
3025   printk("aic7xxx: Downloading sequencer code..");
3026   aic7xxx_loadseq(base);
3027 
3028   /* Set Fast Mode and Enable the board */
3029   outb(FASTMODE, SEQCTL(base));
3030 
3031   if ((p->type == AIC_274x || p->type == AIC_284x))
3032   {
3033     outb(ENABLE, BCTL(base));
3034   }
3035 
3036   printk("done.\n");
3037 
3038   /*
3039    * Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels
3040    */
3041   if (p->bus_type == AIC_TWIN)
3042   {
3043     /*
3044      * The device is gated to channel B after a chip reset,
3045      * so set those values first.
3046      */
3047     outb(config.scsi_id_b, SCSIID(base));
3048     scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
3049     scsi_conf = scsi_conf | ENSTIMER | ACTNEGEN | STPWEN;
3050     outb(scsi_conf, SXFRCTL1(base));
3051     outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3052     /* Select Channel A */
3053     outb(0, SBLKCTL(base));
3054   }
3055   outb(config.scsi_id, SCSIID(base));
3056   scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
3057   outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3058   outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3059 
3060   /* Look at the information that board initialization or the board
3061    * BIOS has left us. In the lower four bits of each target's
3062    * scratch space any value other than 0 indicates that we should
3063    * initiate synchronous transfers. If it's zero, the user or the
3064    * BIOS has decided to disable synchronous negotiation to that
3065    * target so we don't activate the needsdtr flag.
3066    */
3067   p->needsdtr_copy = 0;
3068   p->sdtr_pending = 0;
3069   p->needwdtr_copy = 0;
3070   p->wdtr_pending = 0;
3071   if (p->bus_type == AIC_SINGLE)
3072   {
3073     max_targets = 8;
3074   }
3075   else
3076   {
3077     max_targets = 16;
3078   }
3079 
3080   for (i = 0; i < max_targets; i++)
3081   {
3082     if (have_seeprom)
3083     {
3084       target_settings = (sc.device_flags[i] & CFXFER) << 4;
3085       if (sc.device_flags[i] & CFSYNCH)
3086       {
3087         p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
3088       }
3089       if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
3090       {
3091         p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3092       }
3093     }
3094     else
3095     {
3096       target_settings = inb(HA_TARG_SCRATCH(base) + i);
3097       if (target_settings & 0x0F)
3098       {
3099         p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
3100         /*
3101          * Default to asynchronous transfers (0 offset)
3102          */
3103         target_settings = target_settings & 0xF0;
3104       }
3105       /*
3106        * If we are not wide, forget WDTR. This makes the driver
3107        * work on some cards that don't leave these fields cleared
3108        * when BIOS is not installed.
3109        */
3110       if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
3111       {
3112         p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3113         target_settings = target_settings & 0x7F;
3114       }
3115     }
3116     outb(target_settings, (HA_TARG_SCRATCH(base) + i));
3117   }
3118 
3119   p->needsdtr = p->needsdtr_copy;
3120   p->needwdtr = p->needwdtr_copy;
3121 #if 0
3122   printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
3123   printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
3124 #endif 0
3125 
3126   /*
3127    * Clear the control byte for every SCB so that the sequencer
3128    * doesn't get confused and think that one of them is valid
3129    */
3130   for (i = 0; i < config.maxscb; i++)
3131   {
3132     outb(i, SCBPTR(base));
3133     outb(0, SCBARRAY(base));
3134   }
3135 
3136   /*
3137    * For reconnecting targets, the sequencer code needs to
3138    * know how many SCBs it has to search through.
3139    */
3140   outb(config.maxscb, HA_SCBCOUNT(base));
3141 
3142   /*
3143    * Clear the active flags - no targets are busy.
3144    */
3145   outb(0, HA_ACTIVE0(base));
3146   outb(0, HA_ACTIVE1(base));
3147 
3148   /* We don't have any waiting selections */
3149   outb (SCB_LIST_NULL, WAITING_SCBH(base));
3150   outb (SCB_LIST_NULL, WAITING_SCBT(base));
3151 
3152   /*
3153    * Reset the SCSI bus. Is this necessary?
3154    *   There may be problems for a warm boot without resetting
3155    *   the SCSI bus. Either BIOS settings in scratch RAM
3156    *   will not get reinitialized, or devices may stay at
3157    *   previous negotiated settings (SDTR and WDTR) while
3158    *   the driver will think that no negotiations have been
3159    *   performed.
3160    *
3161    * Some devices need a long time to "settle" after a SCSI
3162    * bus reset.
3163    */
3164 
3165   if (!aic7xxx_no_reset)
3166   {
3167     printk("Resetting the SCSI bus...\n");
3168     if (p->bus_type == AIC_TWIN)
3169     {
3170       /*
3171        * Select channel B.
3172        */
3173       outb(2, SBLKCTL(base));
3174       outb(SCSIRSTO, SCSISEQ(base));
3175       udelay(1000);
3176       outb(0, SCSISEQ(base));
3177       /*
3178        * Select channel A.
3179        */
3180       outb(0, SBLKCTL(base));
3181     }
3182 
3183     outb(SCSIRSTO, SCSISEQ(base));
3184     udelay(1000);
3185     outb(0, SCSISEQ(base));
3186     aic7xxx_delay(AIC7XXX_RESET_DELAY);
3187   }
3188 
3189   /*
3190    * Unpause the sequencer before returning and enable
3191    * interrupts - we shouldn't get any until the first
3192    * command is sent to us by the high-level SCSI code.
3193    */
3194   UNPAUSE_SEQUENCER(p);
3195   return (found);
3196 }
3197 
3198 /*+F*************************************************************************
3199  * Function:
3200  *   aic7xxx_detect
3201  *
3202  * Description:
3203  *   Try to detect and register an Adaptec 7770 or 7870 SCSI controller.
3204  *-F*************************************************************************/
3205 int
3206 aic7xxx_detect(Scsi_Host_Template *template)
     /*  */
3207 {
3208   aha_type type = AIC_NONE;
3209   int found = 0, slot, base;
3210   unsigned char irq = 0;
3211   int i;
3212 
3213   template->proc_dir = &proc_scsi_aic7xxx;
3214 
3215   /*
3216    * Since we may allow sharing of IRQs, it is imperative
3217    * that we "null-out" the aic7xxx_boards array. It is
3218    * not guaranteed to be initialized to 0 (NULL). We use
3219    * a NULL entry to indicate that no prior hosts have
3220    * been found/registered for that IRQ.
3221    */
3222   for (i = 0; i <= MAXIRQ; i++)
3223   {
3224     aic7xxx_boards[i] = NULL;
3225   }
3226 
3227   /*
3228    * Initialize the spurious count to 0.
3229    */
3230   aic7xxx_spurious_count = 0;
3231 
3232   /*
3233    * EISA/VL-bus card signature probe.
3234    */
3235   for (slot = MINSLOT; slot <= MAXSLOT; slot++)
3236   {
3237     base = SLOTBASE(slot);
3238 
3239     if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
3240     {
3241       /*
3242        * Some other driver has staked a
3243        * claim to this i/o region already.
3244        */
3245       continue;
3246     }
3247 
3248     type = aic7xxx_probe(slot, HID0(base));
3249     if (type != AIC_NONE)
3250     {
3251       /*
3252        * We found a card, allow 1 spurious interrupt.
3253        */
3254       aic7xxx_spurious_count = 1;
3255 
3256 #if 0
3257       printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3258       outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3259       irq = inb(HA_INTDEF(base)) & 0x0F;
3260 #endif
3261 
3262       /*
3263        * We "find" a AIC-7770 if we locate the card
3264        * signature and we can set it up and register
3265        * it with the kernel without incident.
3266        */
3267       found += aic7xxx_register(template, type, base, irq);
3268 
3269       /*
3270        * Disallow spurious interrupts.
3271        */
3272       aic7xxx_spurious_count = 0;
3273     }
3274   }
3275 
3276 #ifdef CONFIG_PCI
3277 
3278 #define DEVREVID  0x08
3279 #define DEVCONFIG 0x40
3280 #define DEVSTATUS 0x41
3281 #define RAMPSM    0x02
3282 
3283   /*
3284    * PCI-bus probe.
3285    */
3286   if (pcibios_present())
3287   {
3288     int error;
3289     int done = 0;
3290     unsigned int io_port;
3291     unsigned short index = 0;
3292     unsigned char pci_bus, pci_device_fn;
3293     unsigned char devrevid, devconfig, devstatus;
3294     char rev_id[] = {'B', 'C', 'D'};
3295 
3296     while (!done)
3297     {
3298       if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3299                                 PCI_DEVICE_ID_ADAPTEC_294x,
3300                                 index, &pci_bus, &pci_device_fn)) ||
3301            (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3302                                 PCI_DEVICE_ID_ADAPTEC_2940,
3303                                 index, &pci_bus, &pci_device_fn)))
3304       {
3305         type = AIC_7870;
3306       }
3307       else
3308       {
3309         if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3310                                 PCI_DEVICE_ID_ADAPTEC_7850,
3311                                 index, &pci_bus, &pci_device_fn))
3312         {
3313           type = AIC_7850;
3314         }
3315         else
3316         {
3317           if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3318                                   PCI_DEVICE_ID_ADAPTEC_7872,
3319                                   index, &pci_bus, &pci_device_fn))
3320           {
3321             type = AIC_7872;
3322           }
3323           else
3324           {
3325             type = AIC_NONE;
3326             done = 1;
3327           }
3328         }
3329       }
3330 
3331       if (!done)
3332       {
3333         /*
3334          * Read esundry information from PCI BIOS.
3335          */
3336         error = pcibios_read_config_dword(pci_bus, pci_device_fn,
3337                                           PCI_BASE_ADDRESS_0, &io_port);
3338 
3339         if (error)
3340         {
3341           panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
3342         }
3343 
3344         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3345                                          PCI_INTERRUPT_LINE, &irq);
3346         if (error)
3347         {
3348           panic("aic7xxx_detect: error %d reading irq.\n", error);
3349         }
3350 
3351         /*
3352          * Make the base I/O register look like EISA and VL-bus.
3353          */
3354         base = io_port - 0xC01;
3355 
3356         /*
3357          * I don't think we need to bother with allowing
3358          * spurious interrupts for the 787x/7850, but what
3359          * the hey.
3360          */
3361         aic7xxx_spurious_count = 1;
3362 
3363 #if 0
3364         printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3365 #endif
3366         outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3367 
3368         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3369                                          DEVREVID, &devrevid);
3370         if (devrevid < 3)
3371         {
3372           printk("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
3373         }
3374         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3375                                          DEVCONFIG, &devconfig);
3376         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3377                                          DEVSTATUS, &devstatus);
3378         printk("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
3379                devconfig, devstatus);
3380         if (devstatus & RAMPSM)
3381         {
3382           printk("aic7xxx_detect: detected external SCB RAM, "
3383                  "mail deang@ims.com for test patch");
3384         }
3385 
3386         found += aic7xxx_register(template, type, base, irq);
3387 
3388         /*
3389          * Disable spurious interrupts.
3390          */
3391         aic7xxx_spurious_count = 0;
3392 
3393         index += 1;
3394       }
3395     }
3396   }
3397 #endif CONFIG_PCI
3398 
3399   template->name = aic7xxx_info(NULL);
3400   return (found);
3401 }
3402 
3403 
3404 /*+F*************************************************************************
3405  * Function:
3406  *   aic7xxx_buildscb
3407  *
3408  * Description:
3409  *   Build a SCB.
3410  *-F*************************************************************************/
3411 static void
3412 aic7xxx_buildscb(struct aic7xxx_host *p,
     /*  */
3413                  Scsi_Cmnd *cmd,
3414                  struct aic7xxx_scb *scb)
3415 {
3416   void *addr;
3417   unsigned length;
3418   unsigned short mask;
3419 
3420   /*
3421    * Setup the control byte if we need negotiation and have not
3422    * already requested it.
3423    */
3424 #ifdef AIC7XXX_TAGGED_QUEUEING
3425   if (cmd->device->tagged_supported)
3426   {
3427     if (cmd->device->tagged_queue == 0)
3428     {
3429       printk("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
3430              "channel %d\n", cmd->target, cmd->channel);
3431       cmd->device->tagged_queue = 1;
3432       cmd->device->current_tag = 1;  /* enable tagging */
3433     }
3434     cmd->tag = cmd->device->current_tag;
3435     cmd->device->current_tag = cmd->device->current_tag + 1;
3436     scb->control = scb->control | SCB_TE;
3437   }
3438 #endif
3439   mask = (0x01 << cmd->target);
3440   if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
3441   {
3442     p->wdtr_pending = p->wdtr_pending | mask;
3443     scb->control = scb->control | SCB_NEEDWDTR;
3444 #if 0
3445     printk("Sending WDTR request to target %d.\n", cmd->target);
3446 #endif
3447   }
3448   else
3449   {
3450     if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
3451     {
3452       p->sdtr_pending = p->sdtr_pending | mask;
3453       scb->control = scb->control | SCB_NEEDSDTR;
3454 #if 0
3455       printk("Sending SDTR request to target %d.\n", cmd->target);
3456 #endif
3457     }
3458   }
3459 
3460 #if 0
3461   printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
3462          cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
3463 #endif
3464   scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
3465         ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
3466 
3467   /*
3468    * The interpretation of request_buffer and request_bufflen
3469    * changes depending on whether or not use_sg is zero; a
3470    * non-zero use_sg indicates the number of elements in the
3471    * scatter-gather array.
3472    *
3473    * The AIC-7770 can't support transfers of any sort larger
3474    * than 2^24 (three-byte count) without backflips. For what
3475    * the kernel is doing, this shouldn't occur. I hope.
3476    */
3477   length = aic7xxx_length(cmd, 0);
3478 
3479   if (length > 0xFFFFFF)
3480   {
3481     panic("aic7xxx_buildscb: can't transfer > 2^24 - 1 bytes\n");
3482   }
3483 
3484   /*
3485    * XXX - this relies on the host data being stored in a
3486    *       little-endian format.
3487    */
3488   addr = cmd->cmnd;
3489   scb->SCSI_cmd_length = cmd->cmd_len;
3490   memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
3491 
3492   if (cmd->use_sg)
3493   {
3494 #if 0
3495     debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
3496           cmd->use_sg, length);
3497 #endif
3498     scb->SG_segment_count = cmd->use_sg;
3499     memcpy(scb->SG_list_pointer, &cmd->request_buffer,
3500            sizeof(scb->SG_list_pointer));
3501   }
3502   else
3503   {
3504 #if 0
3505     debug("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
3506           (unsigned long) cmd->request_buffer, cmd->request_bufflen);
3507 #endif
3508 #ifdef AIC7XXX_USE_SG
3509     scb->SG_segment_count = 1;
3510     scb->sg.address = (char *) cmd->request_buffer;
3511     scb->sg.length = cmd->request_bufflen;
3512     addr = &scb->sg;
3513     memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
3514 #else
3515     scb->SG_segment_count = 0;
3516     memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
3517     memcpy(scb->data_count, &cmd->request_bufflen, 3);
3518 #endif
3519   }
3520 }
3521 
3522 /*+F*************************************************************************
3523  * Function:
3524  *   aic7xxx_queue
3525  *
3526  * Description:
3527  *   Queue a SCB to the controller.
3528  *-F*************************************************************************/
3529 int
3530 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
     /*  */
3531 {
3532   long flags;
3533 #ifndef AIC7XXX_USE_DMA
3534   int old_scbptr;
3535 #endif
3536   struct aic7xxx_host *p;
3537   struct aic7xxx_scb *scb;
3538   unsigned char curscb;
3539 
3540   p = (struct aic7xxx_host *) cmd->host->hostdata;
3541 
3542   /* Check to see if channel was scanned. */
3543  if (!p->a_scanned && (cmd->channel == 0))
3544   {
3545     printk("aic7xxx: Scanning channel A for devices.\n");
3546     p->a_scanned = 1;
3547   }
3548   else
3549   {
3550     if (!p->b_scanned && (cmd->channel == 1))
3551     {
3552       printk("aic7xxx: Scanning channel B for devices.\n");
3553       p->b_scanned = 1;
3554     }
3555   }
3556 
3557 #if 0
3558   debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
3559         cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
3560         cmd->lun & 0x07);
3561 #endif
3562 
3563   /*
3564    * This is a critical section, since we don't want the
3565    * interrupt routine mucking with the host data or the
3566    * card. Since the kernel documentation is vague on
3567    * whether or not we are in a cli/sti pair already, save
3568    * the flags to be on the safe side.
3569    */
3570   save_flags(flags);
3571   cli();
3572 
3573   /*
3574    * Find a free slot in the SCB array to load this command
3575    * into. Since can_queue is set to the maximum number of
3576    * SCBs for the card, we should always find one.
3577    *
3578    * First try to find an scb in the free list. If there are
3579    * none in the free list, then check the current number of
3580    * of scbs and take an unused one from the scb array.
3581    */
3582   scb = p->free_scb;
3583   if (scb != NULL)
3584   { /* found one in the free list */
3585     p->free_scb = scb->next;   /* remove and update head of list */
3586     /*
3587      * Warning! For some unknown reason, the scb at the head
3588      * of the free list is not the same address that it should
3589      * be. That's why we set the scb pointer taken by the
3590      * position in the array. The scb at the head of the list
3591      * should match this address, but it doesn't.
3592      */
3593     scb = &(p->scb_array[scb->position]);
3594     scb->control = 0;
3595     scb->state = SCB_ACTIVE;
3596   }
3597   else
3598   {
3599     if (p->numscb >= p->maxscb)
3600     {
3601       panic("aic7xxx_queue: couldn't find a free scb\n");
3602     }
3603     else
3604     {
3605       /*
3606        * Initialize the scb within the scb array. The
3607        * position within the array is the position on
3608        * the board that it will be loaded.
3609        */
3610       scb = &(p->scb_array[p->numscb]);
3611       memset(scb, 0, sizeof(*scb));
3612 
3613       scb->position = p->numscb;
3614       p->numscb++;
3615       scb->state = SCB_ACTIVE;
3616       scb->next_waiting = SCB_LIST_NULL;
3617       memcpy(scb->host_scb, &scb, sizeof(scb));
3618 #ifdef AIC7XXX_USE_DMA
3619       scb->control = SCB_NEEDDMA;
3620 #endif
3621       PAUSE_SEQUENCER(p);
3622       curscb = inb(SCBPTR(p->base));
3623       outb(scb->position, SCBPTR(p->base));
3624       aic7xxx_putdmascb(p->base, scb);
3625       outb(curscb, SCBPTR(p->base));
3626       UNPAUSE_SEQUENCER(p);
3627       scb->control = 0;
3628     }
3629   }
3630 
3631   scb->cmd = cmd;
3632   aic7xxx_position(cmd) = scb->position;
3633 
3634   /*
3635    * Construct the SCB beforehand, so the sequencer is
3636    * paused a minimal amount of time.
3637    */
3638   aic7xxx_buildscb(p, cmd, scb);
3639 
3640 #if 0
3641   if (scb != &p->scb_array[scb->position])
3642   {
3643     printk("aic7xxx_queue: address of scb by position does not match scb address\n");
3644   }
3645   printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
3646          scb->position, (unsigned int) scb->cmd,
3647          scb->state, (unsigned int) p->free_scb);
3648 #endif
3649   /*
3650    * Pause the sequencer so we can play with its registers -
3651    * wait for it to acknowledge the pause.
3652    *
3653    * XXX - should the interrupts be left on while doing this?
3654    */
3655   PAUSE_SEQUENCER(p);
3656 
3657   /*
3658    * Save the SCB pointer and put our own pointer in - this
3659    * selects one of the four banks of SCB registers. Load
3660    * the SCB, then write its pointer into the queue in FIFO
3661    * and restore the saved SCB pointer.
3662    */
3663 #ifdef AIC7XXX_USE_DMA
3664   aic7xxx_putscb(p->base, scb);
3665 #else
3666   old_scbptr = inb(SCBPTR(p->base));
3667   outb(scb->position, SCBPTR(p->base));
3668 
3669   aic7xxx_putscb(p->base, scb);
3670 
3671   outb(scb->position, QINFIFO(p->base));
3672   outb(old_scbptr, SCBPTR(p->base));
3673 #endif
3674   /*
3675    * Make sure the Scsi_Cmnd pointer is saved, the struct it
3676    * points to is set up properly, and the parity error flag
3677    * is reset, then unpause the sequencer and watch the fun
3678    * begin.
3679    */
3680   cmd->scsi_done = fn;
3681   aic7xxx_error(cmd) = DID_OK;
3682   aic7xxx_status(cmd) = 0;
3683 
3684   cmd->result = 0;
3685   memset(&cmd->sense_buffer, 0, sizeof(cmd->sense_buffer));
3686 
3687   UNPAUSE_SEQUENCER(p);
3688   restore_flags(flags);
3689   return (0);
3690 }
3691 
3692 /* return values from aic7xxx_kill */
3693 typedef enum {
3694   k_ok,             /* scb found and message sent */
3695   k_busy,           /* message already present */
3696   k_absent,         /* couldn't locate scb */
3697   k_disconnect,     /* scb found, but disconnected */
3698 } k_state;
3699 
3700 /*+F*************************************************************************
3701  * Function:
3702  *   aic7xxx_kill
3703  *
3704  * Description:
3705  *   This must be called with interrupts disabled - it's going to
3706  *   be messing around with the host data, and an interrupt being
3707  *   fielded in the middle could get ugly.
3708  *
3709  *   Since so much of the abort and reset code is shared, this
3710  *   function performs more magic than it really should. If the
3711  *   command completes ok, then it will call scsi_done with the
3712  *   result code passed in. The unpause parameter controls whether
3713  *   or not the sequencer gets unpaused - the reset function, for
3714  *   instance, may want to do something more aggressive.
3715  *
3716  *   Note that the command is checked for in our SCB_array first
3717  *   before the sequencer is paused, so if k_absent is returned,
3718  *   then the sequencer is NOT paused.
3719  *-F*************************************************************************/
3720 static k_state
3721 aic7xxx_kill(Scsi_Cmnd *cmd, unsigned char message,
     /*  */
3722              unsigned int result, int unpause)
3723 {
3724   struct aic7xxx_host *p;
3725   struct aic7xxx_scb *scb;
3726   int i, active_scb, found, queued;
3727   unsigned char scbsave[AIC7XXX_MAXSCB];
3728   unsigned char flags;
3729   int scb_control;
3730   k_state status;
3731 
3732   p = (struct aic7xxx_host *) cmd->host->hostdata;
3733   scb = &p->scb_array[aic7xxx_position(cmd)];
3734 
3735 #if 0
3736   printk("aic7xxx_kill: In the kill function...\n");
3737 #endif
3738   PAUSE_SEQUENCER(p);
3739 
3740   /*
3741    * Case 1: In the QINFIFO
3742    *
3743    * This is the best case, really. Check to see if the
3744    * command is still in the sequencer's input queue. If
3745    * so, simply remove it. Reload the queue afterward.
3746    */
3747   queued = inb(QINCNT(p->base));
3748 
3749   for (i = found = 0; i < (queued - found); i++)
3750   {
3751     scbsave[i] = inb(QINFIFO(p->base));
3752 
3753     if (scbsave[i] == scb->position)
3754     {
3755       found = 1;
3756       i--;
3757     }
3758   }
3759 
3760   for (queued = 0; queued < i; queued++)
3761   {
3762     outb(scbsave[queued], QINFIFO(p->base));
3763   }
3764 
3765   if (found)
3766   {
3767     status = k_ok;
3768     goto complete;
3769   }
3770 
3771   active_scb = inb(SCBPTR(p->base));
3772   /*
3773    * Case 2: Not the active command
3774    *
3775    * Check the current SCB bank. If it's not the one belonging
3776    * to the command we want to kill, select the scb we want to
3777    * abort and turn off the disconnected bit. The driver will
3778    * then abort the command and notify us of the abort.
3779    */
3780   if (active_scb != scb->position)
3781   {
3782     outb(scb->position, SCBPTR(p->base));
3783     scb_control = inb(SCBARRAY(p->base));
3784     scb_control = scb_control & ~SCB_DIS;
3785     outb(scb_control, SCBARRAY(p->base));
3786     outb(active_scb, SCBPTR(p->base));
3787     status = k_disconnect;
3788     goto complete;
3789   }
3790 
3791   scb_control = inb(SCBARRAY(p->base));
3792   if (scb_control & SCB_DIS)
3793   {
3794     scb_control = scb_control & ~SCB_DIS;
3795     outb(scb_control, SCBARRAY(p->base));
3796     status = k_disconnect;
3797     goto complete;
3798   }
3799 
3800   /*
3801    * Presumably at this point our target command is active. Check
3802    * to see if there's a message already in effect. If not, place
3803    * our message in and assert ATN so the target goes into MESSAGE
3804    * OUT phase.
3805    */
3806   flags = inb(HA_FLAGS(p->base));
3807   if (flags & ACTIVE_MSG)
3808   {
3809     /*
3810      * If there is a message in progress, reset the bus
3811      * and have all devices renegotiate.
3812      */
3813     if (cmd->channel & 0x01)
3814     {
3815       p->needsdtr = p->needsdtr_copy & 0xFF00;
3816       p->sdtr_pending = p->sdtr_pending & 0x00FF;
3817       outb(0, HA_ACTIVE1(p->base));
3818     }
3819     else
3820     {
3821       if (p->bus_type == AIC_WIDE)
3822       {
3823         p->needsdtr = p->needsdtr_copy;
3824         p->needwdtr = p->needwdtr_copy;
3825         p->sdtr_pending = 0;
3826         p->wdtr_pending = 0;
3827         outb(0, HA_ACTIVE0(p->base));
3828         outb(0, HA_ACTIVE1(p->base));
3829       }
3830       else
3831       {
3832         p->needsdtr = p->needsdtr_copy & 0x00FF;
3833         p->sdtr_pending = p->sdtr_pending & 0xFF00;
3834         outb(0, HA_ACTIVE0(p->base));
3835       }
3836     }
3837     /* Reset the bus. */
3838     outb(SCSIRSTO, SCSISEQ(p->base));
3839     udelay(1000);
3840     outb(0, SCSISEQ(p->base));
3841     aic7xxx_delay(AIC7XXX_RESET_DELAY);
3842 
3843     status = k_busy;
3844     goto complete;
3845   }
3846 
3847   outb(flags | ACTIVE_MSG, HA_FLAGS(p->base));    /* active message */
3848   outb(1, HA_MSG_LEN(p->base));                   /* length = 1 */
3849   outb(message, HA_MSG_START(p->base));           /* message body */
3850 
3851   /*
3852    * Assert ATN. Use the value of SCSISIGO saved by the
3853    * sequencer code so we don't alter its contents radically
3854    * in the middle of something critical.
3855    */
3856   outb(inb(HA_SIGSTATE(p->base)) | 0x10, SCSISIGO(p->base));
3857 
3858   status = k_ok;
3859 
3860   /*
3861    * The command has been killed. Do the bookkeeping, unpause
3862    * the sequencer, and notify the higher-level SCSI code.
3863    */
3864 complete:
3865   if (unpause)
3866   {
3867     UNPAUSE_SEQUENCER(p);
3868   }
3869 
3870   /*
3871    * Mark the scb as free and clear the scbs command pointer.
3872    * Add the scb to the head of the free list being careful
3873    * to preserve the next pointers.
3874    */
3875   scb->state = SCB_FREE;          /* mark the scb as free */
3876   scb->cmd = NULL;                /* clear the command pointer */
3877   scb->next = p->free_scb;        /* preserve next pointer */
3878   p->free_scb = scb;              /* add at head of free list */
3879   cmd->result = cmd->result << 16;
3880   cmd->scsi_done(cmd);
3881   return (status);
3882 }
3883 
3884 /*+F*************************************************************************
3885  * Function:
3886  *   aic7xxx_abort
3887  *
3888  * Description:
3889  *   Abort the current SCSI command(s).
3890  *-F*************************************************************************/
3891 int
3892 aic7xxx_abort(Scsi_Cmnd *cmd)
     /*  */
3893 {
3894   int rv;
3895   long flags;
3896 
3897   save_flags(flags);
3898   cli();
3899 
3900   switch (aic7xxx_kill(cmd, ABORT, DID_ABORT, !0))
3901   {
3902     case k_ok:          rv = SCSI_ABORT_SUCCESS;        break;
3903     case k_busy:        rv = SCSI_ABORT_BUSY;           break;
3904     case k_absent:      rv = SCSI_ABORT_NOT_RUNNING;    break;
3905     case k_disconnect:  rv = SCSI_ABORT_SNOOZE;         break;
3906     default:            panic("aic7xxx_abort: internal error\n");
3907   }
3908 
3909   restore_flags(flags);
3910   return (rv);
3911 }
3912 
3913 /*+F*************************************************************************
3914  * Function:
3915  *   aic7xxx_reset
3916  *
3917  * Description:
3918  *   Resetting the bus always succeeds - is has to, otherwise the
3919  *   kernel will panic! Try a surgical technique - sending a BUS
3920  *   DEVICE RESET message - on the offending target before pulling
3921  *   the SCSI bus reset line.
3922  *-F*************************************************************************/
3923 int
3924 aic7xxx_reset(Scsi_Cmnd *cmd)
     /*  */
3925 {
3926   long flags;
3927   struct aic7xxx_host *p;
3928 
3929   p = (struct aic7xxx_host *) cmd->host->hostdata;
3930   save_flags(flags);
3931   cli();
3932 
3933   switch (aic7xxx_kill(cmd, BUS_DEVICE_RESET, DID_RESET, 0))
3934   {
3935     case k_ok:
3936       /*
3937        * The RESET message was sent to the target
3938        * with no problems. Flag that target as
3939        * needing a SDTR negotiation on the next
3940        * connection and restart the sequencer.
3941        */
3942       p->needsdtr = p->needsdtr & (1 << cmd->target);
3943       UNPAUSE_SEQUENCER(p);
3944       break;
3945 
3946     case k_absent:
3947       /*
3948        * The sequencer will not be paused if aic7xxx_kill()
3949        * couldn't find the command.
3950        */
3951       PAUSE_SEQUENCER(p);
3952       /* falls through */
3953 
3954     case k_busy:
3955       cmd->result = DID_RESET << 16;  /* return reset code */
3956       cmd->scsi_done(cmd);
3957       break;
3958 
3959     case k_disconnect:
3960       /*
3961        * Do a hard reset of the SCSI bus. According to the
3962        * SCSI-2 draft specification, reset has to be asserted
3963        * for at least 25us. I'm invoking the kernel delay
3964        * function for 30us since I'm not totally trusting of
3965        * the busy loop timing.
3966        *
3967        * XXX - I'm not convinced this works. I tried resetting
3968        *       the bus before, trying to get the devices on the
3969        *       bus to revert to asynchronous transfer, and it
3970        *       never seemed to work.
3971        */
3972       debug("aic7xxx: attempting to reset scsi bus and card\n");
3973 
3974       outb(SCSIRSTO, SCSISEQ(p->base));
3975       udelay(1000);
3976       outb(0, SCSISEQ(p->base));
3977       aic7xxx_delay(AIC7XXX_RESET_DELAY);
3978 
3979       UNPAUSE_SEQUENCER(p);
3980 
3981       /*
3982        * Locate the command and return a "reset" status
3983        * for it. This is not completely correct and will
3984        * probably return to haunt me later.
3985        */
3986       cmd->result = DID_RESET << 16;  /* return reset code */
3987       cmd->scsi_done(cmd);
3988       break;
3989 
3990     default:
3991       panic("aic7xxx_reset: internal error\n");
3992   }
3993 
3994   restore_flags(flags);
3995   return (SCSI_RESET_SUCCESS);
3996 }
3997 
3998 /*+F*************************************************************************
3999  * Function:
4000  *   aic7xxx_biosparam
4001  *
4002  * Description:
4003  *   Return the disk geometry for the given SCSI device.
4004  *-F*************************************************************************/
4005 int
4006 aic7xxx_biosparam(Disk *disk, kdev_t dev, int geom[])
     /*  */
4007 {
4008   int heads, sectors, cylinders;
4009   struct aic7xxx_host *p;
4010 
4011   p = (struct aic7xxx_host *) disk->device->host->hostdata;
4012 
4013   /*
4014    * XXX - if I could portably find the card's configuration
4015    *       information, then this could be autodetected instead
4016    *       of left to a boot-time switch.
4017    */
4018   heads = 64;
4019   sectors = 32;
4020   cylinders = disk->capacity / (heads * sectors);
4021 
4022   if (p->extended && cylinders > 1024)
4023   {
4024     heads = 255;
4025     sectors = 63;
4026     cylinders = disk->capacity / (255 * 63);
4027   }
4028 
4029   geom[0] = heads;
4030   geom[1] = sectors;
4031   geom[2] = cylinders;
4032 
4033   return (0);
4034 }
4035 
4036 #ifdef MODULE
4037 /* Eventually this will go into an include file, but this will be later */
4038 Scsi_Host_Template driver_template = AIC7XXX;
4039 
4040 #include "scsi_module.c"
4041 #endif
4042 
4043 /*
4044  * Overrides for Emacs so that we almost follow Linus's tabbing style.
4045  * Emacs will notice this stuff at the end of the file and automatically
4046  * adjust the settings for this buffer only.  This must remain at the end
4047  * of the file.
4048  * ---------------------------------------------------------------------------
4049  * Local variables:
4050  * c-indent-level: 2
4051  * c-brace-imaginary-offset: 0
4052  * c-brace-offset: -2
4053  * c-argdecl-indent: 2
4054  * c-label-offset: -2
4055  * c-continued-statement-offset: 2
4056  * c-continued-brace-offset: 0
4057  * indent-tabs-mode: nil
4058  * tab-width: 8
4059  * End:
4060  */
/* */
root/drivers/scsi/aic7xxx.c

DEFINITIONS
