![[first]](../icons/first.png){kind=icon}
![[previous]](../icons/n_left.png){kind=icon}
![[next]](../icons/n_right.png){kind=icon}
![[last]](../icons/last.png){kind=icon}
![[top]](../icons/n_top.png){kind=icon}
![[bottom]](../icons/bottom.png){kind=icon}
![[index]](../icons/index.png){kind=icon}
![[help]](../icons/help.png){kind=icon}
*/
1 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8 #ifndef __ASM_MIPS_DMA_H
9 #define __ASM_MIPS_DMA_H
10
11 #include <asm/io.h> /* need byte IO */
12
13
14 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
15 #define dma_outb outb_p
16 #else
17 #define dma_outb outb
18 #endif
19
20 #define dma_inb inb
21
22 /*
23 * NOTES about DMA transfers:
24 *
25 * controller 1: channels 0-3, byte operations, ports 00-1F
26 * controller 2: channels 4-7, word operations, ports C0-DF
27 *
28 * - ALL registers are 8 bits only, regardless of transfer size
29 * - channel 4 is not used - cascades 1 into 2.
30 * - channels 0-3 are byte - addresses/counts are for physical bytes
31 * - channels 5-7 are word - addresses/counts are for physical words
32 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
33 * - transfer count loaded to registers is 1 less than actual count
34 * - controller 2 offsets are all even (2x offsets for controller 1)
35 * - page registers for 5-7 don't use data bit 0, represent 128K pages
36 * - page registers for 0-3 use bit 0, represent 64K pages
37 *
38 * DMA transfers are limited to the lower 16MB of _physical_ memory.
39 * Note that addresses loaded into registers must be _physical_ addresses,
40 * not logical addresses (which may differ if paging is active).
41 *
42 * Address mapping for channels 0-3:
43 *
44 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
45 * | ... | | ... | | ... |
46 * | ... | | ... | | ... |
47 * | ... | | ... | | ... |
48 * P7 ... P0 A7 ... A0 A7 ... A0
49 * | Page | Addr MSB | Addr LSB | (DMA registers)
50 *
51 * Address mapping for channels 5-7:
52 *
53 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
54 * | ... | \ \ ... \ \ \ ... \ \
55 * | ... | \ \ ... \ \ \ ... \ (not used)
56 * | ... | \ \ ... \ \ \ ... \
57 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
58 * | Page | Addr MSB | Addr LSB | (DMA registers)
59 *
60 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
61 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
62 * the hardware level, so odd-byte transfers aren't possible).
63 *
64 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
65 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
66 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
67 *
68 */
69
70 #define MAX_DMA_CHANNELS 8
71
72 /* The maximum address that we can perform a DMA transfer to on this platform */
73 #define MAX_DMA_ADDRESS 0x1000000
74
75 /* The maximum address that we can perform a DMA transfer to on this platform */
76 #define MAX_DMA_ADDRESS 0x1000000
77
78 /* 8237 DMA controllers */
79 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
80 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
81
82 /* DMA controller registers */
83 #define DMA1_CMD_REG 0x08 /* command register (w) */
84 #define DMA1_STAT_REG 0x08 /* status register (r) */
85 #define DMA1_REQ_REG 0x09 /* request register (w) */
86 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
87 #define DMA1_MODE_REG 0x0B /* mode register (w) */
88 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
89 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
90 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
91 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
92 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
93
94 #define DMA2_CMD_REG 0xD0 /* command register (w) */
95 #define DMA2_STAT_REG 0xD0 /* status register (r) */
96 #define DMA2_REQ_REG 0xD2 /* request register (w) */
97 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
98 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
99 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
100 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
101 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
102 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
103 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
104
105 #define DMA_ADDR_0 0x00 /* DMA address registers */
106 #define DMA_ADDR_1 0x02
107 #define DMA_ADDR_2 0x04
108 #define DMA_ADDR_3 0x06
109 #define DMA_ADDR_4 0xC0
110 #define DMA_ADDR_5 0xC4
111 #define DMA_ADDR_6 0xC8
112 #define DMA_ADDR_7 0xCC
113
114 #define DMA_CNT_0 0x01 /* DMA count registers */
115 #define DMA_CNT_1 0x03
116 #define DMA_CNT_2 0x05
117 #define DMA_CNT_3 0x07
118 #define DMA_CNT_4 0xC2
119 #define DMA_CNT_5 0xC6
120 #define DMA_CNT_6 0xCA
121 #define DMA_CNT_7 0xCE
122
123 #define DMA_PAGE_0 0x87 /* DMA page registers */
124 #define DMA_PAGE_1 0x83
125 #define DMA_PAGE_2 0x81
126 #define DMA_PAGE_3 0x82
127 #define DMA_PAGE_5 0x8B
128 #define DMA_PAGE_6 0x89
129 #define DMA_PAGE_7 0x8A
130
131 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
132 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
133 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
134
135 /* enable/disable a specific DMA channel */
136 static __inline__ void enable_dma(unsigned int dmanr)
/* ![[next]](../icons/right.png)
![[first]](../icons/n_first.png)
![[top]](../icons/top.png)
*/
137 {
138 if (dmanr<=3)
139 dma_outb(dmanr, DMA1_MASK_REG);
140 else
141 dma_outb(dmanr & 3, DMA2_MASK_REG);
142 }
143
144 static __inline__ void disable_dma(unsigned int dmanr)
/* ![[previous]](../icons/left.png)
*/
145 {
146 if (dmanr<=3)
147 dma_outb(dmanr | 4, DMA1_MASK_REG);
148 else
149 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
150 }
151
152 /* Clear the 'DMA Pointer Flip Flop'.
153 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
154 * Use this once to initialize the FF to a known state.
155 * After that, keep track of it. :-)
156 * --- In order to do that, the DMA routines below should ---
157 * --- only be used while interrupts are disabled! ---
158 */
159 static __inline__ void clear_dma_ff(unsigned int dmanr)
/* */
160 {
161 if (dmanr<=3)
162 dma_outb(0, DMA1_CLEAR_FF_REG);
163 else
164 dma_outb(0, DMA2_CLEAR_FF_REG);
165 }
166
167 /* set mode (above) for a specific DMA channel */
168 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
/* */
169 {
170 if (dmanr<=3)
171 dma_outb(mode | dmanr, DMA1_MODE_REG);
172 else
173 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
174 }
175
176 /* Set only the page register bits of the transfer address.
177 * This is used for successive transfers when we know the contents of
178 * the lower 16 bits of the DMA current address register, but a 64k boundary
179 * may have been crossed.
180 */
181 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
/* */
182 {
183 switch(dmanr) {
184 case 0:
185 dma_outb(pagenr, DMA_PAGE_0);
186 break;
187 case 1:
188 dma_outb(pagenr, DMA_PAGE_1);
189 break;
190 case 2:
191 dma_outb(pagenr, DMA_PAGE_2);
192 break;
193 case 3:
194 dma_outb(pagenr, DMA_PAGE_3);
195 break;
196 case 5:
197 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
198 break;
199 case 6:
200 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
201 break;
202 case 7:
203 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
204 break;
205 }
206 }
207
208
209 /* Set transfer address & page bits for specific DMA channel.
210 * Assumes dma flipflop is clear.
211 */
212 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
/* */
213 {
214 set_dma_page(dmanr, a>>16);
215 if (dmanr <= 3) {
216 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
217 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
218 } else {
219 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
220 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
221 }
222 }
223
224
225 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
226 * a specific DMA channel.
227 * You must ensure the parameters are valid.
228 * NOTE: from a manual: "the number of transfers is one more
229 * than the initial word count"! This is taken into account.
230 * Assumes dma flip-flop is clear.
231 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
232 */
233 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
/* */
234 {
235 count--;
236 if (dmanr <= 3) {
237 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
238 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
239 } else {
240 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
241 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
242 }
243 }
244
245
246 /* Get DMA residue count. After a DMA transfer, this
247 * should return zero. Reading this while a DMA transfer is
248 * still in progress will return unpredictable results.
249 * If called before the channel has been used, it may return 1.
250 * Otherwise, it returns the number of _bytes_ left to transfer.
251 *
252 * Assumes DMA flip-flop is clear.
253 */
254 static __inline__ int get_dma_residue(unsigned int dmanr)
/* ![[last]](../icons/n_last.png)
*/
255 {
256 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
257 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
258
259 /* using short to get 16-bit wrap around */
260 unsigned short count;
261
262 count = 1 + dma_inb(io_port);
263 count += dma_inb(io_port) << 8;
264
265 return (dmanr<=3)? count : (count<<1);
266 }
267
268
269 /* These are in kernel/dma.c: */
270 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
271 extern void free_dma(unsigned int dmanr); /* release it again */
272
273
274 #endif /* __ASM_MIPS_DMA_H */
![[bottom]](../icons/n_bottom.png){kind=icon}
*/