![[first]](../icons/first.png){kind=icon}
![[previous]](../icons/n_left.png){kind=icon}
![[next]](../icons/n_right.png){kind=icon}
![[last]](../icons/last.png){kind=icon}
![[top]](../icons/n_top.png){kind=icon}
![[bottom]](../icons/bottom.png){kind=icon}
![[index]](../icons/index.png){kind=icon}
![[help]](../icons/help.png){kind=icon}
*/
1 /*
2 * include/asm-alpha/dma.h
3 *
4 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
5 * use ISA-compatible dma. The only extension is support for high-page
6 * registers that allow to set the top 8 bits of a 32-bit DMA address.
7 * This register should be written last when setting up a DMA address
8 * as this will also enable DMA across 64 KB boundaries.
9 */
10
11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
12 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
13 * Written by Hennus Bergman, 1992.
14 * High DMA channel support & info by Hannu Savolainen
15 * and John Boyd, Nov. 1992.
16 */
17
18 #ifndef _ASM_DMA_H
19 #define _ASM_DMA_H
20
21 #include <asm/io.h> /* need byte IO */
22
23 #define dma_outb outb
24 #define dma_inb inb
25
26 /*
27 * NOTES about DMA transfers:
28 *
29 * controller 1: channels 0-3, byte operations, ports 00-1F
30 * controller 2: channels 4-7, word operations, ports C0-DF
31 *
32 * - ALL registers are 8 bits only, regardless of transfer size
33 * - channel 4 is not used - cascades 1 into 2.
34 * - channels 0-3 are byte - addresses/counts are for physical bytes
35 * - channels 5-7 are word - addresses/counts are for physical words
36 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
37 * - transfer count loaded to registers is 1 less than actual count
38 * - controller 2 offsets are all even (2x offsets for controller 1)
39 * - page registers for 5-7 don't use data bit 0, represent 128K pages
40 * - page registers for 0-3 use bit 0, represent 64K pages
41 *
42 * DMA transfers are limited to the lower 16MB of _physical_ memory.
43 * Note that addresses loaded into registers must be _physical_ addresses,
44 * not logical addresses (which may differ if paging is active).
45 *
46 * Address mapping for channels 0-3:
47 *
48 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
49 * | ... | | ... | | ... |
50 * | ... | | ... | | ... |
51 * | ... | | ... | | ... |
52 * P7 ... P0 A7 ... A0 A7 ... A0
53 * | Page | Addr MSB | Addr LSB | (DMA registers)
54 *
55 * Address mapping for channels 5-7:
56 *
57 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
58 * | ... | \ \ ... \ \ \ ... \ \
59 * | ... | \ \ ... \ \ \ ... \ (not used)
60 * | ... | \ \ ... \ \ \ ... \
61 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
62 * | Page | Addr MSB | Addr LSB | (DMA registers)
63 *
64 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
65 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
66 * the hardware level, so odd-byte transfers aren't possible).
67 *
68 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
69 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
70 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
71 *
72 */
73
74 #define MAX_DMA_CHANNELS 8
75
76 /* The maximum address that we can perform a DMA transfer to on this platform */
77 #define MAX_DMA_ADDRESS (~0UL)
78
79 /* 8237 DMA controllers */
80 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
81 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
82
83 /* DMA controller registers */
84 #define DMA1_CMD_REG 0x08 /* command register (w) */
85 #define DMA1_STAT_REG 0x08 /* status register (r) */
86 #define DMA1_REQ_REG 0x09 /* request register (w) */
87 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
88 #define DMA1_MODE_REG 0x0B /* mode register (w) */
89 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
90 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
91 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
92 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
93 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
94 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
95
96 #define DMA2_CMD_REG 0xD0 /* command register (w) */
97 #define DMA2_STAT_REG 0xD0 /* status register (r) */
98 #define DMA2_REQ_REG 0xD2 /* request register (w) */
99 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
100 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
101 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
102 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
103 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
104 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
105 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
106 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
107
108 #define DMA_ADDR_0 0x00 /* DMA address registers */
109 #define DMA_ADDR_1 0x02
110 #define DMA_ADDR_2 0x04
111 #define DMA_ADDR_3 0x06
112 #define DMA_ADDR_4 0xC0
113 #define DMA_ADDR_5 0xC4
114 #define DMA_ADDR_6 0xC8
115 #define DMA_ADDR_7 0xCC
116
117 #define DMA_CNT_0 0x01 /* DMA count registers */
118 #define DMA_CNT_1 0x03
119 #define DMA_CNT_2 0x05
120 #define DMA_CNT_3 0x07
121 #define DMA_CNT_4 0xC2
122 #define DMA_CNT_5 0xC6
123 #define DMA_CNT_6 0xCA
124 #define DMA_CNT_7 0xCE
125
126 #define DMA_PAGE_0 0x87 /* DMA page registers */
127 #define DMA_PAGE_1 0x83
128 #define DMA_PAGE_2 0x81
129 #define DMA_PAGE_3 0x82
130 #define DMA_PAGE_5 0x8B
131 #define DMA_PAGE_6 0x89
132 #define DMA_PAGE_7 0x8A
133
134 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
135 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
136 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
137 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
138 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
139 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
140 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
141 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
142
143 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
144 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
145 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
146
147 /* enable/disable a specific DMA channel */
148 static __inline__ void enable_dma(unsigned int dmanr)
/* ![[next]](../icons/right.png)
![[first]](../icons/n_first.png)
![[top]](../icons/top.png)
*/
149 {
150 if (dmanr<=3)
151 dma_outb(dmanr, DMA1_MASK_REG);
152 else
153 dma_outb(dmanr & 3, DMA2_MASK_REG);
154 }
155
156 static __inline__ void disable_dma(unsigned int dmanr)
/* ![[previous]](../icons/left.png)
*/
157 {
158 if (dmanr<=3)
159 dma_outb(dmanr | 4, DMA1_MASK_REG);
160 else
161 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
162 }
163
164 /* Clear the 'DMA Pointer Flip Flop'.
165 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
166 * Use this once to initialize the FF to a known state.
167 * After that, keep track of it. :-)
168 * --- In order to do that, the DMA routines below should ---
169 * --- only be used while interrupts are disabled! ---
170 */
171 static __inline__ void clear_dma_ff(unsigned int dmanr)
/* */
172 {
173 if (dmanr<=3)
174 dma_outb(0, DMA1_CLEAR_FF_REG);
175 else
176 dma_outb(0, DMA2_CLEAR_FF_REG);
177 }
178
179 /* set mode (above) for a specific DMA channel */
180 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
/* */
181 {
182 if (dmanr<=3)
183 dma_outb(mode | dmanr, DMA1_MODE_REG);
184 else
185 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
186 }
187
188 /* set extended mode for a specific DMA channel */
189 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
/* */
190 {
191 if (dmanr<=3)
192 dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
193 else
194 dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
195 }
196
197 /* Set only the page register bits of the transfer address.
198 * This is used for successive transfers when we know the contents of
199 * the lower 16 bits of the DMA current address register.
200 */
201 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
/* */
202 {
203 switch(dmanr) {
204 case 0:
205 dma_outb(pagenr, DMA_PAGE_0);
206 dma_outb((pagenr >> 8), DMA_HIPAGE_0);
207 break;
208 case 1:
209 dma_outb(pagenr, DMA_PAGE_1);
210 dma_outb((pagenr >> 8), DMA_HIPAGE_1);
211 break;
212 case 2:
213 dma_outb(pagenr, DMA_PAGE_2);
214 dma_outb((pagenr >> 8), DMA_HIPAGE_2);
215 break;
216 case 3:
217 dma_outb(pagenr, DMA_PAGE_3);
218 dma_outb((pagenr >> 8), DMA_HIPAGE_3);
219 break;
220 case 5:
221 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
222 dma_outb((pagenr >> 8), DMA_HIPAGE_5);
223 break;
224 case 6:
225 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
226 dma_outb((pagenr >> 8), DMA_HIPAGE_6);
227 break;
228 case 7:
229 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
230 dma_outb((pagenr >> 8), DMA_HIPAGE_7);
231 break;
232 }
233 }
234
235
236 /* Set transfer address & page bits for specific DMA channel.
237 * Assumes dma flipflop is clear.
238 */
239 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
/* */
240 {
241 if (dmanr <= 3) {
242 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
243 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
244 } else {
245 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
246 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
247 }
248 set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
249 }
250
251
252 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
253 * a specific DMA channel.
254 * You must ensure the parameters are valid.
255 * NOTE: from a manual: "the number of transfers is one more
256 * than the initial word count"! This is taken into account.
257 * Assumes dma flip-flop is clear.
258 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
259 */
260 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
/* */
261 {
262 count--;
263 if (dmanr <= 3) {
264 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
265 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
266 } else {
267 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
268 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
269 }
270 }
271
272
273 /* Get DMA residue count. After a DMA transfer, this
274 * should return zero. Reading this while a DMA transfer is
275 * still in progress will return unpredictable results.
276 * If called before the channel has been used, it may return 1.
277 * Otherwise, it returns the number of _bytes_ left to transfer.
278 *
279 * Assumes DMA flip-flop is clear.
280 */
281 static __inline__ int get_dma_residue(unsigned int dmanr)
/* ![[last]](../icons/n_last.png)
*/
282 {
283 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
284 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
285
286 /* using short to get 16-bit wrap around */
287 unsigned short count;
288
289 count = 1 + dma_inb(io_port);
290 count += dma_inb(io_port) << 8;
291
292 return (dmanr<=3)? count : (count<<1);
293 }
294
295
296 /* These are in kernel/dma.c: */
297 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
298 extern void free_dma(unsigned int dmanr); /* release it again */
299
300
301 #endif /* _ASM_DMA_H */
![[bottom]](../icons/n_bottom.png){kind=icon}
*/