drivers/net/seeq8005.h

/* */
   1 /* 
   2  * defines, etc for the seeq8005
   3  */
   4  
   5 /*
   6  * This file is distributed under GPL.
   7  *
   8  * This style and layout of this file is also copied
   9  * from many of the other linux network device drivers.
  10  */
  11 
  12 /* The number of low I/O ports used by the ethercard. */
  13 #define SEEQ8005_IO_EXTENT      16
  14 
  15 #define SEEQ_B          (ioaddr)
  16 
  17 #define SEEQ_CMD        (SEEQ_B)                /* Write only */
  18 #define SEEQ_STATUS     (SEEQ_B)                /* Read only */
  19 #define SEEQ_CFG1       (SEEQ_B + 2)
  20 #define SEEQ_CFG2       (SEEQ_B + 4)
  21 #define SEEQ_REA        (SEEQ_B + 6)            /* Receive End Area Register */
  22 #define SEEQ_RPR        (SEEQ_B + 10)           /* Receive Pointer Register */
  23 #define SEEQ_TPR        (SEEQ_B + 12)           /* Transmit Pointer Register */
  24 #define SEEQ_DMAAR      (SEEQ_B + 14)           /* DMA Address Register */
  25 #define SEEQ_BUFFER     (SEEQ_B + 8)            /* Buffer Window Register */
  26 
  27 #define DEFAULT_TEA     (0x3f)
  28 
  29 #define SEEQCMD_DMA_INT_EN      (0x0001)        /* DMA Interrupt Enable */
  30 #define SEEQCMD_RX_INT_EN       (0x0002)        /* Receive Interrupt Enable */
  31 #define SEEQCMD_TX_INT_EN       (0x0004)        /* Transmit Interrupt Enable */
  32 #define SEEQCMD_WINDOW_INT_EN   (0x0008)        /* What the hell is this for?? */
  33 #define SEEQCMD_INT_MASK        (0x000f)
  34 
  35 #define SEEQCMD_DMA_INT_ACK     (0x0010)        /* DMA ack */
  36 #define SEEQCMD_RX_INT_ACK      (0x0020)
  37 #define SEEQCMD_TX_INT_ACK      (0x0040)
  38 #define SEEQCMD_WINDOW_INT_ACK  (0x0080)
  39 #define SEEQCMD_ACK_ALL         (0x00f0)
  40 
  41 #define SEEQCMD_SET_DMA_ON      (0x0100)        /* Enables DMA Request logic */
  42 #define SEEQCMD_SET_RX_ON       (0x0200)        /* Enables Packet RX */
  43 #define SEEQCMD_SET_TX_ON       (0x0400)        /* Starts TX run */
  44 #define SEEQCMD_SET_DMA_OFF     (0x0800)
  45 #define SEEQCMD_SET_RX_OFF      (0x1000)
  46 #define SEEQCMD_SET_TX_OFF      (0x2000)
  47 #define SEEQCMD_SET_ALL_OFF     (0x3800)        /* set all logic off */
  48 
  49 #define SEEQCMD_FIFO_READ       (0x4000)        /* Set FIFO to read mode (read from Buffer) */
  50 #define SEEQCMD_FIFO_WRITE      (0x8000)        /* Set FIFO to write mode */
  51 
  52 #define SEEQSTAT_DMA_INT_EN     (0x0001)        /* Status of interrupt enable */
  53 #define SEEQSTAT_RX_INT_EN      (0x0002)
  54 #define SEEQSTAT_TX_INT_EN      (0x0004)
  55 #define SEEQSTAT_WINDOW_INT_EN  (0x0008)
  56 
  57 #define SEEQSTAT_DMA_INT        (0x0010)        /* Interrupt flagged */
  58 #define SEEQSTAT_RX_INT         (0x0020)
  59 #define SEEQSTAT_TX_INT         (0x0040)
  60 #define SEEQSTAT_WINDOW_INT     (0x0080)
  61 #define SEEQSTAT_ANY_INT        (0x00f0)
  62 
  63 #define SEEQSTAT_DMA_ON         (0x0100)        /* DMA logic on */
  64 #define SEEQSTAT_RX_ON          (0x0200)        /* Packet RX on */
  65 #define SEEQSTAT_TX_ON          (0x0400)        /* TX running */
  66 
  67 #define SEEQSTAT_FIFO_FULL      (0x2000)
  68 #define SEEQSTAT_FIFO_EMPTY     (0x4000)
  69 #define SEEQSTAT_FIFO_DIR       (0x8000)        /* 1=read, 0=write */
  70 
  71 #define SEEQCFG1_BUFFER_MASK    (0x000f)        /* define what mapps into the BUFFER register */
  72 #define SEEQCFG1_BUFFER_MAC0    (0x0000)        /* MAC station addresses 0-5 */
  73 #define SEEQCFG1_BUFFER_MAC1    (0x0001)
  74 #define SEEQCFG1_BUFFER_MAC2    (0x0002)
  75 #define SEEQCFG1_BUFFER_MAC3    (0x0003)
  76 #define SEEQCFG1_BUFFER_MAC4    (0x0004)
  77 #define SEEQCFG1_BUFFER_MAC5    (0x0005)
  78 #define SEEQCFG1_BUFFER_PROM    (0x0006)        /* The Address/CFG PROM */
  79 #define SEEQCFG1_BUFFER_TEA     (0x0007)        /* Transmit end area */
  80 #define SEEQCFG1_BUFFER_BUFFER  (0x0008)        /* Packet buffer memory */
  81 #define SEEQCFG1_BUFFER_INT_VEC (0x0009)        /* Interrupt Vector */
  82 
  83 #define SEEQCFG1_DMA_INTVL_MASK (0x0030)
  84 #define SEEQCFG1_DMA_CONT       (0x0000)
  85 #define SEEQCFG1_DMA_800ns      (0x0010)
  86 #define SEEQCFG1_DMA_1600ns     (0x0020)
  87 #define SEEQCFG1_DMA_3200ns     (0x0030)
  88 
  89 #define SEEQCFG1_DMA_LEN_MASK   (0x00c0)
  90 #define SEEQCFG1_DMA_LEN1       (0x0000)
  91 #define SEEQCFG1_DMA_LEN2       (0x0040)
  92 #define SEEQCFG1_DMA_LEN4       (0x0080)
  93 #define SEEQCFG1_DMA_LEN8       (0x00c0)
  94 
  95 #define SEEQCFG1_MAC_MASK       (0x3f00)        /* Dis/enable bits for MAC addresses */
  96 #define SEEQCFG1_MAC0_EN        (0x0100)
  97 #define SEEQCFG1_MAC1_EN        (0x0200)
  98 #define SEEQCFG1_MAC2_EN        (0x0400)
  99 #define SEEQCFG1_MAC3_EN        (0x0800)
 100 #define SEEQCFG1_MAC4_EN        (0x1000)
 101 #define SEEQCFG1_MAC5_EN        (0x2000)
 102 
 103 #define SEEQCFG1_MATCH_MASK     (0xc000)        /* Packet matching logic cfg bits */
 104 #define SEEQCFG1_MATCH_SPECIFIC (0x0000)        /* only matching MAC addresses */
 105 #define SEEQCFG1_MATCH_BROAD    (0x4000)        /* matching and broadcast addresses */
 106 #define SEEQCFG1_MATCH_MULTI    (0x8000)        /* matching, broadcast and multicast */
 107 #define SEEQCFG1_MATCH_ALL      (0xc000)        /* Promiscuous mode */
 108 
 109 #define SEEQCFG1_DEFAULT        (SEEQCFG1_BUFFER_BUFFER | SEEQCFG1_MAC0_EN | SEEQCFG1_MATCH_BROAD)
 110 
 111 #define SEEQCFG2_BYTE_SWAP      (0x0001)        /* 0=Intel byte-order */
 112 #define SEEQCFG2_AUTO_REA       (0x0002)        /* if set, Receive End Area will be updated when reading from Buffer */
 113 
 114 #define SEEQCFG2_CRC_ERR_EN     (0x0008)        /* enables receiving of packets with CRC errors */
 115 #define SEEQCFG2_DRIBBLE_EN     (0x0010)        /* enables receiving of non-aligned packets */
 116 #define SEEQCFG2_SHORT_EN       (0x0020)        /* enables receiving of short packets */
 117 
 118 #define SEEQCFG2_SLOTSEL        (0x0040)        /* 0= standard IEEE802.3, 1= smaller,faster, non-standard */
 119 #define SEEQCFG2_NO_PREAM       (0x0080)        /* 1= user supplies Xmit preamble bytes */
 120 #define SEEQCFG2_ADDR_LEN       (0x0100)        /* 1= 2byte addresses */
 121 #define SEEQCFG2_REC_CRC        (0x0200)        /* 0= recieved packets will have CRC stripped from them */
 122 #define SEEQCFG2_XMIT_NO_CRC    (0x0400)        /* dont xmit CRC with each packet (user supplies it) */
 123 #define SEEQCFG2_LOOPBACK       (0x0800)
 124 #define SEEQCFG2_CTRLO          (0x1000)
 125 #define SEEQCFG2_RESET          (0x8000)        /* software Hard-reset bit */
 126 
 127 struct seeq_pkt_hdr {
 128         unsigned short  next;                   /* address of next packet header */
 129         unsigned char   babble_int:1,           /* enable int on >1514 byte packet */
 130                         coll_int:1,             /* enable int on collision */
 131                         coll_16_int:1,          /* enable int on >15 collision */
 132                         xmit_int:1,             /* enable int on success (or xmit with <15 collision) */
 133                         unused:1,
 134                         data_follows:1,         /* if not set, process this as a header and pointer only */
 135                         chain_cont:1,           /* if set, more headers in chain                only cmd bit valid in recv header */
 136                         xmit_recv:1;            /* if set, a xmit packet, else a recieve packet.*/
 137         unsigned char   status;
 138 };
 139 
 140 #define SEEQPKTH_BAB_INT_EN     (0x01)          /* xmit only */
 141 #define SEEQPKTH_COL_INT_EN     (0x02)          /* xmit only */
 142 #define SEEQPKTH_COL16_INT_EN   (0x04)          /* xmit only */
 143 #define SEEQPKTH_XMIT_INT_EN    (0x08)          /* xmit only */
 144 #define SEEQPKTH_DATA_FOLLOWS   (0x20)          /* supposedly in xmit only */
 145 #define SEEQPKTH_CHAIN          (0x40)          /* more headers follow */
 146 #define SEEQPKTH_XMIT           (0x80)
 147 
 148 #define SEEQPKTS_BABBLE         (0x0100)        /* xmit only */
 149 #define SEEQPKTS_OVERSIZE       (0x0100)        /* recv only */
 150 #define SEEQPKTS_COLLISION      (0x0200)        /* xmit only */
 151 #define SEEQPKTS_CRC_ERR        (0x0200)        /* recv only */
 152 #define SEEQPKTS_COLL16         (0x0400)        /* xmit only */
 153 #define SEEQPKTS_DRIB           (0x0400)        /* recv only */
 154 #define SEEQPKTS_SHORT          (0x0800)        /* recv only */
 155 #define SEEQPKTS_DONE           (0x8000)
 156 #define SEEQPKTS_ANY_ERROR      (0x0f00)
/* */
root/drivers/net/seeq8005.h

INCLUDED FROM
