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*/
1 #ifndef _SPARC_ASI_H
2 #define _SPARC_ASI_H
3
4 /* asi.h: Address Space Identifier values for the sparc.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 *
8 * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
9 * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
10 */
11
12 /* These are sun4c, beware on other architectures. Although things should
13 * be similar under regular sun4's.
14 */
15
16 #include <linux/config.h>
17
18 #define ASI_NULL1 0x0
19 #define ASI_NULL2 0x1
20
21 /* sun4c and sun4 control registers and mmu/vac ops */
22 #define ASI_CONTROL 0x2
23 #define ASI_SEGMAP 0x3
24 #define ASI_PTE 0x4
25 #define ASI_HWFLUSHSEG 0x5 /* These are to initiate hw flushes of the cache */
26 #define ASI_HWFLUSHPAGE 0x6
27 #define ASI_REGMAP 0x6 /* Top level segmaps on Sun4's with MUTANT MMU */
28 #define ASI_HWFLUSHCONTEXT 0x7
29
30
31 #define ASI_USERTXT 0x8
32 #define ASI_KERNELTXT 0x9
33 #define ASI_USERDATA 0xa
34 #define ASI_KERNELDATA 0xb
35
36 /* VAC Cache flushing on sun4c and sun4 */
37
38 #define ASI_FLUSHSEG 0xc /* These are for "software" flushes of the cache */
39 #define ASI_FLUSHPG 0xd
40 #define ASI_FLUSHCTX 0xe
41
42 /* The following are now not so SS5 specific any more, it is pretty
43 * much a complete generic sun4m/V8 ASI assignment listing now.
44 *
45 * -- davem@caip.rutgers.edu
46 */
47
48 /* SPARCstation-5: only 6 bits are decoded. */
49 /* wo = Write Only, rw = Read Write; */
50 /* ss = Single Size, as = All Sizes; */
51 #define ASI_M_RES00 0x00 /* Don't touch... */
52 #define ASI_M_UNA01 0x01 /* Same here... */
53 #define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
54 #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
55 #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
56 #define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
57 #define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
58 #define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
59 #define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
60 #define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
61 #define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
62 #define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
63 #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
64 #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
65 #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
66 #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
67
68 /* The following cache flushing ASIs work only with the 'sta'
69 * instruction results are unpredictable for 'swap' and 'ldstuba' etc.
70 * So don't do it.
71 */
72
73 /* These ASI flushes affect external caches too. */
74 #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
75 #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
76 #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
77 #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
78 #define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
79
80 /* Block-copy operations are available on certain V8 cpus */
81 #define ASI_M_BCOPY 0x17 /* Block copy */
82
83 /* These affect only the ICACHE and are Ross HyperSparc specific. */
84 #define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
85 #define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
86 #define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
87 #define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
88 #define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
89
90 /* Block-fill operations are available on certain V8 cpus */
91 #define ASI_M_BFILL 0x1F
92
93 /* This allows direct access to main memory, actually 0x20 to 0x2f are
94 * the available ASI's for physical ram pass-through, but I don't have
95 * any idea what the other ones do....
96 */
97
98 #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
99 #define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
100 #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
101 #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
102 #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
103 #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
104 #define ASI_M_SBUS 0x2E /* Direct SBus access */
105 #define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
106
107
108 /* This is ROSS HyperSparc only. */
109 #define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
110
111 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Registerl rw, ss */
112
113 /* Sparc V9 TI UltraSparc ASI's */
114
115 /* ASIs 0x0-0x7f are Supervisor Only. 0x80-0xff are for anyone. */
116
117 /* You will notice that there are a lot of places where if a normal
118 * ASI is available on the V9, there is also a little-endian version.
119 */
120
121 #define ASI_V9_RESV0 0x00 /* Don't touch... */
122 #define ASI_V9_RESV1 0x01 /* Not here */
123 #define ASI_V9_RESV2 0x02 /* Or here */
124 #define ASI_V9_RESV3 0x03 /* nor here. */
125 #define ASI_V9_NUCLEUS 0x04 /* Impl-dep extra virtual access context */
126 #define ASI_V9_NUCLEUSL 0x0C /* Nucleus context, little-endian */
127 #define ASI_V9_USER_PRIM 0x10 /* User primary address space */
128 #define ASI_V9_USER_SEC 0x11 /* User secondary address space */
129
130 #define ASI_V9_MMUPASS 0x14 /* OBMEM (external cache, no data cache) */
131 #define ASI_V9_IOPASS 0x15 /* Like MMUPASS but for I/O areas (uncached) */
132 #define ASI_V9_USER_PRIML 0x18 /* User primary address space, little-endian. */
133 #define ASI_V9_USER_SECL 0x19 /* User secondary address space, little-endian. */
134 #define ASI_V9_MMUPASSL 0x1C /* OBMEM little-endian */
135 #define ASI_V9_IOPASSL 0x1D /* Like IOPASS but little-endian */
136 #define ASI_V9_ATOMICQ 0x24 /* Atomic 128-bit load address space */
137 #define ASI_V9_ATOMICQL 0x2C /* Atomic 128-bit load little-endian */
138 #define ASI_V9_LSTORECTL 0x45 /* ld/st control unit */
139 #define ASI_V9_DCACHE_ENT 0x46 /* Data cache entries */
140 #define ASI_V9_DCACHE_TAG 0x47 /* Data cache tags */
141 #define ASI_V9_IRQDISPS 0x48 /* IRQ dispatch status registers */
142 #define ASI_V9_IRQRECVS 0x49 /* IRQ receive status registers */
143 #define ASI_V9_MMUREGS 0x4A /* Spitfire MMU control register */
144 #define ASI_V9_ESTATE 0x4B /* Error state enable register */
145 #define ASI_V9_ASYNC_FSR 0x4C /* Asynchronous Fault Status reg */
146 #define ASI_V9_ASYNC_FAR 0x4D /* Asynchronous Fault Address reg */
147
148 #define ASI_V9_ECACHE_DIAG 0x4E /* External Cache diagnostics */
149
150 #define ASI_V9_TXTMMU 0x50 /* MMU for program text */
151 #define ASI_V9_TXTMMU_D1 0x51 /* XXX */
152 #define ASI_V9_TXTMMU_D2 0x52 /* XXX */
153 #define ASI_V9_TXTMMU_TDI 0x54 /* Text MMU TLB data in */
154 #define ASI_V9_TXTMMU_TDA 0x55 /* Text MMU TLB data access */
155 #define ASI_V9_TXTMMU_TTR 0x56 /* Text MMU TLB tag read */
156 #define ASI_V9_TXTMMU_TDM 0x57 /* Text MMU TLB de-map */
157
158 #define ASI_V9_DATAMMU 0x58 /* MMU for program data */
159 #define ASI_V9_DATAMMU_D1 0x59 /* XXX */
160 #define ASI_V9_DATAMMU_D2 0x5A /* XXX */
161 #define ASI_V9_DATAMMU_DD 0x5B /* XXX */
162 #define ASI_V9_DATAMMU_TDI 0x5C /* Data MMU TLB data in */
163 #define ASI_V9_DATAMMU_TDA 0x5D /* Data MMU TLB data access */
164 #define ASI_V9_DATAMMU_TTR 0x5E /* Data MMU TLB tag read */
165 #define ASI_V9_DATAMMU_TDM 0x5F /* Data MMU TLB de-map */
166
167 #define ASI_V9_ICACHE_D 0x66 /* Instruction cache data */
168 #define ASI_V9_ICACHE_T 0x67 /* Instruction cache tags */
169 #define ASI_V9_ICACHE_DEC 0x6E /* Instruction cache decode */
170 #define ASI_V9_ICACHE_NXT 0x6F /* Instruction cache next ent */
171
172 #define ASI_V9_HUH1 0x70 /* XXX */
173 #define ASI_V9_HUH2 0x71 /* XXX */
174
175 #define ASI_V9_ECACHE_ACC 0x76 /* External cache registers */
176
177 #define ASI_V9_INTR_DISP 0x77 /* Interrupt dispatch registers */
178 #define ASI_V9_HUH1L 0x78 /* XXX */
179 #define ASI_V9_HUH2L 0x79 /* XXX */
180 #define ASI_V9_INTR_RECV 0x7f /* Interrupt Receive registers */
181
182 #define ASI_V9_PRIMARY 0x80 /* Primary address space */
183 #define ASI_V9_SECONDARY 0x81 /* Secondary address space */
184 #define ASI_V9_PRIMARY_NF 0x82 /* Primary address space -- No Fault */
185 #define ASI_V9_SECONDARY_NF 0x83 /* Secondary address space -- No Fault */
186
187 #define ASI_V9_PRIMARYL 0x80 /* Primary address space, little-endian */
188 #define ASI_V9_SECONDARYL 0x81 /* Secondary address space, little-endian */
189 #define ASI_V9_PRIMARY_NFL 0x82 /* Primary address space, No Fault, l-endian */
190 #define ASI_V9_SECONDARY_NFL 0x83 /* Secondary address space, No Fault, l-endian */
191
192 #define ASI_V9_XXX1 0xC0 /* XXX */
193 #define ASI_V9_XXX2 0xC1 /* XXX */
194 #define ASI_V9_XXX3 0xC2 /* XXX */
195 #define ASI_V9_XXX4 0xC3 /* XXX */
196 #define ASI_V9_XXX5 0xC4 /* XXX */
197 #define ASI_V9_XXX6 0xC5 /* XXX */
198 #define ASI_V9_XXX7 0xC8 /* XXX */
199 #define ASI_V9_XXX8 0xC9 /* XXX */
200 #define ASI_V9_XXX9 0xCA /* XXX */
201 #define ASI_V9_XXX10 0xCB /* XXX */
202 #define ASI_V9_XXX11 0xCC /* XXX */
203 #define ASI_V9_XXX12 0xCD /* XXX */
204
205 #define ASI_V9_XXX13 0xD0 /* XXX */
206 #define ASI_V9_XXX14 0xD1 /* XXX */
207 #define ASI_V9_XXX15 0xD2 /* XXX */
208 #define ASI_V9_XXX16 0xD3 /* XXX */
209 #define ASI_V9_XXX17 0xD8 /* XXX */
210 #define ASI_V9_XXX18 0xD9 /* XXX */
211 #define ASI_V9_XXX19 0xDA /* XXX */
212 #define ASI_V9_XXX20 0xDB /* XXX */
213
214 #define ASI_V9_XXX21 0xE0 /* XXX */
215 #define ASI_V9_XXX22 0xE1 /* XXX */
216 #define ASI_V9_XXX23 0xF0 /* XXX */
217 #define ASI_V9_XXX24 0xF1 /* XXX */
218 #define ASI_V9_XXX25 0xF8 /* XXX */
219 #define ASI_V9_XXX26 0xF9 /* XXX */
220
221 #ifndef __ASSEMBLY__
222
223 /* Better to do these inline with gcc __asm__ statements. */
224
225 /* The following allow you to access physical memory directly without
226 * translation by the SRMMU. The only other way to do this is to
227 * turn off the SRMMU completely, and well... thats not good.
228 *
229 * TODO: For non-MBus SRMMU units we have to perform the following
230 * using this sequence.
231 * 1) Turn off traps
232 * 2) Turn on AC bit in SRMMU control register
233 * 3) Do our direct physical memory access
234 * 4) Restore old SRMMU control register value
235 * 5) Restore old %psr value
236 */
237
238 extern __inline__ unsigned int
239 ldb_sun4m_bypass(unsigned int addr)
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*/
240 {
241 unsigned int retval;
242
243 __asm__("lduba [%2] %1, %0\n\t" :
244 "=r" (retval) :
245 "i" (ASI_M_BYPASS), "r" (addr));
246
247 return retval;
248 }
249
250 extern __inline__ unsigned int
251 ldw_sun4m_bypass(unsigned int addr)
/* ![[previous]](../icons/left.png)
*/
252 {
253 unsigned int retval;
254
255 __asm__("lda [%2] %1, %0\n\t" :
256 "=r" (retval) :
257 "i" (ASI_M_BYPASS), "r" (addr));
258
259 return retval;
260 }
261
262 extern __inline__ void
263 stb_sun4m_bypass(unsigned char value, unsigned int addr)
/* */
264 {
265 __asm__("stba %0, [%2] %1\n\t" : :
266 "r" (value), "i" (ASI_M_BYPASS), "r" (addr) :
267 "memory");
268 }
269
270 extern __inline__ void
271 stw_sun4m_bypass(unsigned int value, unsigned int addr)
/* ![[last]](../icons/n_last.png)
*/
272 {
273 __asm__("sta %0, [%2] %1\n\t" : :
274 "r" (value), "i" (ASI_M_BYPASS), "r" (addr) :
275 "memory");
276 }
277
278 #endif /* !(__ASSEMBLY__) */
279
280
281 #endif /* _SPARC_ASI_H */
![[bottom]](../icons/n_bottom.png){kind=icon}
*/