include/asm-sparc/irq.h

/* */
   1 #ifndef _ALPHA_IRQ_H
   2 #define _ALPHA_IRQ_H
   3 
   4 /*
   5  *      linux/include/asm-sparc/irq.h
   6  *
   7  *      Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   8  */
   9 
  10 #include <linux/linkage.h>
  11 
  12 #include <asm/system.h>     /* For NCPUS */
  13 
  14 extern void disable_irq(unsigned int);
  15 extern void enable_irq(unsigned int);
  16 
  17 /* On the sun4m, just like the timers, we have both per-cpu and master
  18  * interrupt registers.
  19  */
  20 
  21 /* These registers are used for sending/receiving irqs from/to
  22  * different cpu's.   
  23  */
  24 struct sun4m_intreg_percpu {
  25         unsigned int tbt;        /* Interrupts still pending for this cpu. */
  26 
  27         /* These next two registers are WRITE-ONLY and are only
  28          * "on bit" sensitive, "off bits" written have NO affect.
  29          */
  30         unsigned int clear;  /* Clear this cpus irqs here. */
  31         unsigned int set;    /* Set this cpus irqs here. */
  32         unsigned char space[PAGE_SIZE - 12];
  33 };
  34 
  35 struct sun4m_intregs {
  36         struct sun4m_intreg_percpu cpu_intregs[NCPUS];
  37         unsigned int tbt;                /* IRQ's that are still pending. */
  38         unsigned int irqs;               /* Master IRQ bits. */
  39 
  40         /* Again, like the above, two these registers are WRITE-ONLY. */
  41         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
  42         unsigned int set;                /* Set master IRQ's by setting bits here. */
  43 
  44         /* This register is both READ and WRITE. */
  45         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
  46 };
  47 
  48 extern struct sun4m_intregs *sun4m_interrupts;
  49 
  50 /* Bit field defines for the interrupt registers on various
  51  * Sparc machines.
  52  */
  53 
  54 /* The sun4c interrupt register. */
  55 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  56 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  57 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  58 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  59 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  60 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  61 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  62 
  63 /* The sun4m interrupt registers.  MUST RESEARCH THESE SOME MORE XXX */
  64 #define SUN4M_INT_ENABLE  0x80000000
  65 #define SUN4M_INT_E14     0x00000080
  66 #define SUN4M_INT_E10     0x00080000
  67 
  68 #if 0 /* These aren't used on the Sparc (yet), but kept for
  69        * future reference, they could come in handy.
  70        */
  71 #define __STR(x) #x
  72 #define STR(x) __STR(x)
  73  
  74 #define SAVE_ALL "xx"
  75 
  76 #define SAVE_MOST "yy"
  77 
  78 #define RESTORE_MOST "zz"
  79 
  80 #define ACK_FIRST(mask) "aa"
  81 
  82 #define ACK_SECOND(mask) "dummy"
  83 
  84 #define UNBLK_FIRST(mask) "dummy"
  85 
  86 #define UNBLK_SECOND(mask) "dummy"
  87 
  88 #define IRQ_NAME2(nr) nr##_interrupt(void)
  89 #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
  90 #define FAST_IRQ_NAME(nr) IRQ_NAME2(fast_IRQ##nr)
  91 #define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
  92         
  93 #define BUILD_IRQ(chip,nr,mask) \
  94 asmlinkage void IRQ_NAME(nr); \
  95 asmlinkage void FAST_IRQ_NAME(nr); \
  96 asmlinkage void BAD_IRQ_NAME(nr); \
  97 asm code comes here
  98 #endif
  99 
 100 #endif
/* */
root/include/asm-sparc/irq.h

INCLUDED FROM
