root/include/asm-sparc/timer.h

/* */

INCLUDED FROM

   1 /* timer.h:  Definitions for the timer chips on the Sparc.
   2  *
   3  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5 #ifndef _SPARC_TIMER_H
   6 #define _SPARC_TIMER_H
   7 
   8 #include <asm/system.h>  /* For NCPUS */
   9 
  10 /* Timer structures. The interrupt timer has two properties which
  11  * are the counter (which is handled in do_timer in sched.c) and the limit.
  12  * This limit is where the timer's counter 'wraps' around. Oddly enough,
  13  * the sun4c timer when it hits the limit wraps back to 1 and not zero
  14  * thus when calculating the value at which it will fire a microsecond you
  15  * must adjust by one.  Thanks SUN for designing such great hardware ;(
  16  */
  17 
  18 /* Note that I am only going to use the timer that interrupts at
  19  * Sparc IRQ 10.  There is another one available that can fire at
  20  * IRQ 14. Currently it is left untouched, we keep the PROM's limit
  21  * register value and let the prom take these interrupts.  This allows
  22  * L1-A to work.
  23  */
  24 
  25 struct sun4c_timer_info {
  26   volatile unsigned int cur_count10;
  27   volatile unsigned int timer_limit10;
  28   volatile unsigned int cur_count14;
  29   volatile unsigned int timer_limit14;
  30 };
  31 
  32 #define SUN4C_TIMER_PHYSADDR   0xf3000000
  33 
  34 /* All accesses to the sun4c timer registers should use this macro. */
  35 #define  SUN4C_TIMER_STRUCT  ((volatile struct sun4c_timer_info *) TIMER_VADDR)
  36 
  37 /* A sun4m has two blocks of registers which are probably of the same
  38  * structure. LSI Logic's L64851 is told to _decrement_ from the limit
  39  * value. Aurora behaves similarly but its limit value is compacted in
  40  * other fashion (it's wider). Documented fields are defined here.
  41  */
  42 
  43 /* As with the interrupt register, we have two classes of timer registers
  44  * which are per-cpu and master.  Per-cpu timers only hit that cpu and are
  45  * only level 14 ticks, master timer hits all cpus and is level 10.
  46  */
  47 
  48 #define SUN4M_PRM_CNT_L       0x80000000
  49 #define SUN4M_PRM_CNT_LVALUE  0x7FFFFC00
  50 
  51 struct sun4m_timer_percpu_info {
  52   volatile unsigned int l14_timer_limit;    /* Initial value is 0x009c4000 */
  53   volatile unsigned int l14_cur_count;
  54 
  55   /* This register appears to be write only and/or inaccessible
  56    * on Uni-Processor sun4m machines.
  57    */
  58   volatile unsigned int l14_limit_noclear;  /* Data access error is here */
  59 
  60   volatile unsigned int cntrl;            /* =1 after POST on Aurora */
  61   volatile unsigned char space[PAGE_SIZE - 16];
  62 };
  63 
  64 struct sun4m_timer_regs {
  65         struct sun4m_timer_percpu_info cpu_timers[NCPUS];
  66         volatile unsigned int l10_timer_limit;
  67         volatile unsigned int l10_cur_count;
  68 
  69         /* Again, this appears to be write only and/or inaccessible
  70          * on uni-processor sun4m machines.
  71          */
  72         volatile unsigned int l10_limit_noclear;
  73 
  74         /* This register too, it must be magic. */
  75         volatile unsigned int foobar;
  76 
  77         volatile unsigned int cfg;     /* equals zero at boot time... */
  78 };
  79 
  80 extern struct sun4m_timer_regs *sun4m_timers;
  81 extern volatile unsigned int *master_l10_limit;
  82 
  83 #endif /* !(_SPARC_TIMER_H) */

/* */