root/include/linux/cyclades.h

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INCLUDED FROM

   1 /*
   2  * linux/include/linux/cyclades.h
   3  *
   4  * This file is maintained by Marcio Saito <marcio@cyclades.com> and
   5  * Randolph Bentson <bentson@grieg.seaslug.org>.
   6  *
   7  * This file contains the general definitions for the cyclades.c driver
   8  */
   9 
  10 /* PCI vendor and device ID's */
  11 
  12 #ifndef PCI_VENDOR_ID_CYCLADES
  13 #define PCI_VENDOR_ID_CYCLADES  0x120e
  14 #endif
  15 
  16 #ifndef PCI_DEVICE_ID_CYCLOMY
  17 #define PCI_DEVICE_ID_CYCLOMY   0x0100
  18 #endif
  19 
  20 /* Per card data structure */
  21 
  22 struct cyclades_card {
  23     int base_addr;
  24     int irq;
  25     int num_chips;      /* 0 if card is absent */
  26     int first_line;     /* minor number of first channel on card */
  27     int bus_index;      /* address shift - 0 for ISA, 1 for PCI */
  28 };
  29 
  30 struct cyclades_chip {
  31   int filler;
  32 };
  33 
  34 struct cyclades_monitor {
  35         unsigned long           int_count;
  36         unsigned long           char_count;
  37         unsigned long           char_max;
  38         unsigned long           char_last;
  39 };
  40 
  41 /*
  42  * This is our internal structure for each serial port's state.
  43  * 
  44  * Many fields are paralleled by the structure used by the serial_struct
  45  * structure.
  46  *
  47  * For definitions of the flags field, see tty.h
  48  */
  49 
  50 struct cyclades_port {
  51         int                     magic;
  52         int                     type;
  53         int                     card;
  54         int                     line;
  55         int                     flags;          /* defined in tty.h */
  56         struct tty_struct       *tty;
  57         int                     read_status_mask;
  58         int                     timeout;
  59         int                     xmit_fifo_size;
  60         int                     cor1,cor2,cor3,cor4,cor5;
  61         int                     tbpr,tco,rbpr,rco;
  62         int                     ignore_status_mask;
  63         int                     close_delay;
  64         int                     IER;    /* Interrupt Enable Register */
  65         int                     event;
  66         unsigned long           last_active;
  67         int                     count;  /* # of fd on device */
  68         int                     x_char; /* to be pushed out ASAP */
  69         int                     x_break;
  70         int                     blocked_open; /* # of blocked opens */
  71         long                    session; /* Session of opening process */
  72         long                    pgrp; /* pgrp of opening process */
  73         unsigned char           *xmit_buf;
  74         int                     xmit_head;
  75         int                     xmit_tail;
  76         int                     xmit_cnt;
  77         int                     default_threshold;
  78         int                     default_timeout;
  79         struct tq_struct        tqueue;
  80         struct termios          normal_termios;
  81         struct termios          callout_termios;
  82         struct wait_queue       *open_wait;
  83         struct wait_queue       *close_wait;
  84         struct cyclades_monitor mon;
  85 };
  86 
  87 #define CYCLADES_MAGIC  0x4359
  88 
  89 #define CYGETMON                0x435901
  90 #define CYGETTHRESH             0x435902
  91 #define CYSETTHRESH             0x435903
  92 #define CYGETDEFTHRESH          0x435904
  93 #define CYSETDEFTHRESH          0x435905
  94 #define CYGETTIMEOUT            0x435906
  95 #define CYSETTIMEOUT            0x435907
  96 #define CYGETDEFTIMEOUT         0x435908
  97 #define CYSETDEFTIMEOUT         0x435909
  98 
  99 /*
 100  * Events are used to schedule things to happen at timer-interrupt
 101  * time, instead of at cy interrupt time.
 102  */
 103 #define Cy_EVENT_READ_PROCESS   0
 104 #define Cy_EVENT_WRITE_WAKEUP   1
 105 #define Cy_EVENT_HANGUP         2
 106 #define Cy_EVENT_BREAK          3
 107 #define Cy_EVENT_OPEN_WAKEUP    4
 108 
 109 
 110 
 111 #define CyMaxChipsPerCard 8
 112 
 113 /**** CD1400 registers ****/
 114 
 115 #define CyRegSize  0x0400
 116 #define Cy_HwReset 0x1400
 117 #define Cy_ClrIntr 0x1800
 118 #define Cy_EpldRev 0x1e00
 119 
 120 /* Global Registers */
 121 
 122 #define CyGFRCR         (0x40*2)
 123 #define      CyRevE             (44)
 124 #define CyCAR           (0x68*2)
 125 #define      CyCHAN_0           (0x00)
 126 #define      CyCHAN_1           (0x01)
 127 #define      CyCHAN_2           (0x02)
 128 #define      CyCHAN_3           (0x03)
 129 #define CyGCR           (0x4B*2)
 130 #define      CyCH0_SERIAL       (0x00)
 131 #define      CyCH0_PARALLEL     (0x80)
 132 #define CySVRR          (0x67*2)
 133 #define      CySRModem          (0x04)
 134 #define      CySRTransmit       (0x02)
 135 #define      CySRReceive        (0x01)
 136 #define CyRICR          (0x44*2)
 137 #define CyTICR          (0x45*2)
 138 #define CyMICR          (0x46*2)
 139 #define      CyICR0             (0x00)
 140 #define      CyICR1             (0x01)
 141 #define      CyICR2             (0x02)
 142 #define      CyICR3             (0x03)
 143 #define CyRIR           (0x6B*2)
 144 #define CyTIR           (0x6A*2)
 145 #define CyMIR           (0x69*2)
 146 #define      CyIRDirEq          (0x80)
 147 #define      CyIRBusy           (0x40)
 148 #define      CyIRUnfair         (0x20)
 149 #define      CyIRContext        (0x1C)
 150 #define      CyIRChannel        (0x03)
 151 #define CyPPR           (0x7E*2)
 152 #define      CyCLOCK_20_1MS     (0x27)
 153 #define      CyCLOCK_25_1MS     (0x31)
 154 
 155 /* Virtual Registers */
 156 
 157 #define CyRIVR          (0x43*2)
 158 #define CyTIVR          (0x42*2)
 159 #define CyMIVR          (0x41*2)
 160 #define      CyIVRMask (0x07)
 161 #define      CyIVRRxEx (0x07)
 162 #define      CyIVRRxOK (0x03)
 163 #define      CyIVRTxOK (0x02)
 164 #define      CyIVRMdmOK (0x01)
 165 #define CyTDR           (0x63*2)
 166 #define CyRDSR          (0x62*2)
 167 #define      CyTIMEOUT          (0x80)
 168 #define      CySPECHAR          (0x70)
 169 #define      CyBREAK            (0x08)
 170 #define      CyPARITY           (0x04)
 171 #define      CyFRAME            (0x02)
 172 #define      CyOVERRUN          (0x01)
 173 #define CyMISR          (0x4C*2)
 174 /* see CyMCOR_ and CyMSVR_ for bits*/
 175 #define CyEOSRR         (0x60*2)
 176 
 177 /* Channel Registers */
 178 
 179 #define CyLIVR          (0x18*2)
 180 #define      CyMscsr            (0x01)
 181 #define      CyTdsr             (0x02)
 182 #define      CyRgdsr            (0x03)
 183 #define      CyRedsr            (0x07)
 184 #define CyCCR           (0x05*2)
 185 /* Format 1 */
 186 #define      CyCHAN_RESET       (0x80)
 187 #define      CyCHIP_RESET       (0x81)
 188 #define      CyFlushTransFIFO   (0x82)
 189 /* Format 2 */
 190 #define      CyCOR_CHANGE       (0x40)
 191 #define      CyCOR1ch           (0x02)
 192 #define      CyCOR2ch           (0x04)
 193 #define      CyCOR3ch           (0x08)
 194 /* Format 3 */
 195 #define      CySEND_SPEC_1      (0x21)
 196 #define      CySEND_SPEC_2      (0x22)
 197 #define      CySEND_SPEC_3      (0x23)
 198 #define      CySEND_SPEC_4      (0x24)
 199 /* Format 4 */
 200 #define      CyCHAN_CTL         (0x10)
 201 #define      CyDIS_RCVR         (0x01)
 202 #define      CyENB_RCVR         (0x02)
 203 #define      CyDIS_XMTR         (0x04)
 204 #define      CyENB_XMTR         (0x08)
 205 #define CySRER          (0x06*2)
 206 #define      CyMdmCh            (0x80)
 207 #define      CyRxData           (0x10)
 208 #define      CyTxRdy            (0x04)
 209 #define      CyTxMpty           (0x02)
 210 #define      CyNNDT             (0x01)
 211 #define CyCOR1          (0x08*2)
 212 #define      CyPARITY_NONE      (0x00)
 213 #define      CyPARITY_0         (0x20)
 214 #define      CyPARITY_1         (0xA0)
 215 #define      CyPARITY_E         (0x40)
 216 #define      CyPARITY_O         (0xC0)
 217 #define      Cy_1_STOP          (0x00)
 218 #define      Cy_1_5_STOP        (0x04)
 219 #define      Cy_2_STOP          (0x08)
 220 #define      Cy_5_BITS          (0x00)
 221 #define      Cy_6_BITS          (0x01)
 222 #define      Cy_7_BITS          (0x02)
 223 #define      Cy_8_BITS          (0x03)
 224 #define CyCOR2          (0x09*2)
 225 #define      CyIXM              (0x80)
 226 #define      CyTxIBE            (0x40)
 227 #define      CyETC              (0x20)
 228 #define      CyAUTO_TXFL        (0x60)
 229 #define      CyLLM              (0x10)
 230 #define      CyRLM              (0x08)
 231 #define      CyRtsAO            (0x04)
 232 #define      CyCtsAE            (0x02)
 233 #define      CyDsrAE            (0x01)
 234 #define CyCOR3          (0x0A*2)
 235 #define      CySPL_CH_DRANGE    (0x80)  /* special character detect range */
 236 #define      CySPL_CH_DET1      (0x40)  /* enable special character detection
 237                                                                on SCHR4-SCHR3 */
 238 #define      CyFL_CTRL_TRNSP    (0x20)  /* Flow Control Transparency */
 239 #define      CySPL_CH_DET2      (0x10)  /* Enable special character detection
 240                                                                on SCHR2-SCHR1 */
 241 #define      CyREC_FIFO         (0x0F)  /* Receive FIFO threshold */
 242 #define CyCOR4          (0x1E*2)
 243 #define CyCOR5          (0x1F*2)
 244 #define CyCCSR          (0x0B*2)
 245 #define      CyRxEN             (0x80)
 246 #define      CyRxFloff          (0x40)
 247 #define      CyRxFlon           (0x20)
 248 #define      CyTxEN             (0x08)
 249 #define      CyTxFloff          (0x04)
 250 #define      CyTxFlon           (0x02)
 251 #define CyRDCR          (0x0E*2)
 252 #define CySCHR1         (0x1A*2)
 253 #define CySCHR2         (0x1B*2)
 254 #define CySCHR3         (0x1C*2)
 255 #define CySCHR4         (0x1D*2)
 256 #define CySCRL          (0x22*2)
 257 #define CySCRH          (0x23*2)
 258 #define CyLNC           (0x24*2)
 259 #define CyMCOR1         (0x15*2)
 260 #define CyMCOR2         (0x16*2)
 261 #define CyRTPR          (0x21*2)
 262 #define CyMSVR1         (0x6C*2)
 263 #define CyMSVR2         (0x6D*2)
 264 #define      CyDSR              (0x80)
 265 #define      CyCTS              (0x40)
 266 #define      CyRI               (0x20)
 267 #define      CyDCD              (0x10)
 268 #define      CyDTR              (0x02)
 269 #define      CyRTS              (0x01)
 270 #define CyPVSR          (0x6F*2)
 271 #define CyRBPR          (0x78*2)
 272 #define CyRCOR          (0x7C*2)
 273 #define CyTBPR          (0x72*2)
 274 #define CyTCOR          (0x76*2)
 275 
 276 /* max number of chars in the FIFO */
 277 
 278 #define CyMAX_CHAR_FIFO 12
 279 
 280 /***************************************************************************/
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