drivers/pci/pci.c

/* */
This source file includes following definitions.
pci_lookup_dev
pci_strbioserr
pci_strclass
pci_strvendor
pci_strdev
burst_bridge
sprint_dev_config
get_pci_list
pci_malloc
scan_bus
pci_init
   1 /*
   2  * drivers/pci/pci.c
   3  *
   4  * PCI services that are built on top of the BIOS32 service.
   5  *
   6  * Copyright 1993, 1994, 1995 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  */
   9 #include <linux/config.h>
  10 #include <linux/ptrace.h>
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/bios32.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 
  17 #include <asm/page.h>
  18 
  19 struct pci_bus pci_root;
  20 struct pci_dev *pci_devices = 0;
  21 
  22 
  23 /*
  24  * The bridge_id field is an offset of an item into the array
  25  * BRIDGE_MAPPING_TYPE. 0xff indicates that the device is not a PCI
  26  * bridge, or that we don't know for the moment how to configure it.
  27  * I'm trying to do my best so that the kernel stays small.  Different
  28  * chipset can have same optimization structure. i486 and pentium
  29  * chipsets from the same manufacturer usually have the same
  30  * structure.
  31  */
  32 #define DEVICE(vid,did,name) \
  33   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
  34 
  35 #define BRIDGE(vid,did,name,bridge) \
  36   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
  37 
  38 /*
  39  * Sorted in ascending order by vendor and device.
  40  * Use binary search for lookup. If you add a device make sure
  41  * it is sequential by both vendor and device id.
  42  */
  43 struct pci_dev_info dev_info[] = {
  44         DEVICE( NCR,            NCR_53C810,     "53c810"),
  45         DEVICE( NCR,            NCR_53C820,     "53c820"),
  46         DEVICE( NCR,            NCR_53C825,     "53c825"),
  47         DEVICE( NCR,            NCR_53C815,     "53c815"),
  48         DEVICE( ATI,            ATI_68800,      "68800AX"),
  49         DEVICE( ATI,            ATI_215CT222,   "215CT222"),
  50         DEVICE( ATI,            ATI_210888CX,   "210888CX"),
  51         DEVICE( ATI,            ATI_210888GX,   "210888GX"),
  52         DEVICE( VLSI,           VLSI_82C592,    "82C592-FC1"),
  53         DEVICE( VLSI,           VLSI_82C593,    "82C593-FC1"),
  54         DEVICE( ADL,            ADL_2301,       "2301"),
  55         DEVICE( NS,             NS_87410,       "87410"),
  56         DEVICE( TSENG,          TSENG_W32P_2,   "ET4000W32P"),
  57         DEVICE( TSENG,          TSENG_W32P_b,   "ET4000W32P rev B"),
  58         DEVICE( TSENG,          TSENG_W32P_c,   "ET4000W32P rev C"),
  59         DEVICE( TSENG,          TSENG_W32P_d,   "ET4000W32P rev D"),
  60         DEVICE( WEITEK,         WEITEK_P9000,   "P9000"),
  61         DEVICE( WEITEK,         WEITEK_P9100,   "P9100"),
  62         BRIDGE( DEC,            DEC_BRD,        "DC21050",              0x00),
  63         DEVICE( DEC,            DEC_TULIP,      "DC21040"),
  64         DEVICE( DEC,            DEC_TULIP_FAST, "DC21140"),
  65         DEVICE( DEC,            DEC_FDDI,       "DEFPA"),
  66         DEVICE( DEC,            DEC_TULIP_PLUS, "DC21041"),
  67         DEVICE( CIRRUS,         CIRRUS_5430,    "GD 5430"),
  68         DEVICE( CIRRUS,         CIRRUS_5434_4,  "GD 5434"),
  69         DEVICE( CIRRUS,         CIRRUS_5434_8,  "GD 5434"),
  70         DEVICE( CIRRUS,         CIRRUS_6729,    "CL 6729"),
  71         DEVICE( CIRRUS,         CIRRUS_7542,    "CL 7542"),
  72         DEVICE( AMD,            AMD_LANCE,      "79C970"),
  73         DEVICE( AMD,            AMD_SCSI,       "53C974"),
  74         DEVICE( TRIDENT,        TRIDENT_9420,   "TG 9420"),
  75         DEVICE( TRIDENT,        TRIDENT_9440,   "TG 9440"),
  76         DEVICE( AI,             AI_M1435,       "M1435"),
  77         DEVICE( MATROX,         MATROX_MGA_2,   "Atlas PX2085"),
  78         DEVICE( MATROX,         MATROX_MIL     ,"Millenium"),
  79         DEVICE( MATROX,         MATROX_MGA_IMP, "MGA Impression"),
  80         DEVICE( CT,             CT_65545,       "65545"),
  81         DEVICE( FD,             FD_36C70,       "TMC-18C30"),
  82         DEVICE( SI,             SI_503,         "85C503"),
  83         DEVICE( SI,             SI_501,         "85C501"),
  84         DEVICE( SI,             SI_496,         "85C496"),
  85         DEVICE( SI,             SI_601,         "85C601"),
  86         DEVICE( SI,             SI_5511,                "85C5511"),
  87         DEVICE( SI,             SI_5513,                "85C5513"),
  88         DEVICE( HP,             HP_J2585A,      "J2585A"),
  89 #if 0
  90         DEVICE( SMC,            SMC_37C665,     "FDC 37C665"),  /* 1042 ? */
  91         DEVICE( SMC,            SMC_37C922,     "FDC 37C922"),
  92 #else
  93         DEVICE( PCTECH,         PCTECH_RZ1000,  "RZ1000 (buggy)"), /* 1042 */
  94 #endif
  95         DEVICE( DPT,            DPT,            "SmartCache/Raid"),
  96         DEVICE( OPTI,           OPTI_82C557,    "82C557"),
  97         DEVICE( OPTI,           OPTI_82C558,    "82C558"),
  98         DEVICE( OPTI,           OPTI_82C621,    "82C621"),
  99         DEVICE( OPTI,           OPTI_82C822,    "82C822"),
 100         DEVICE( BUSLOGIC,       BUSLOGIC_946C_2,"946C"),
 101         DEVICE( BUSLOGIC,       BUSLOGIC_946C,  "946C"),
 102         DEVICE( PROMISE,        PROMISE_5300,   "DC5030"),
 103         DEVICE( N9,             N9_I128,        "Imagine 128"),
 104         DEVICE( UMC,            UMC_UM8673F,    "UM8673F"),
 105         BRIDGE( UMC,            UMC_UM8891A,    "UM8891A",              0x01),
 106         DEVICE( UMC,            UMC_UM8886A,    "UM8886A"),
 107         BRIDGE( UMC,            UMC_UM8881F,    "UM8881F",              0x02),
 108         DEVICE( UMC,            UMC_UM8886F,    "UM8886F"),
 109         DEVICE( X,              X_AGX016,       "ITT AGX016"),
 110         DEVICE( QLOGIC,         QLOGIC_ISP1020, "ISP1020"),
 111         DEVICE( QLOGIC,         QLOGIC_ISP1022, "ISP1022"),
 112         DEVICE( LEADTEK,        LEADTEK_805,    "S3 805"),
 113         DEVICE( CONTAQ,         CONTAQ_82C599,  "82C599"),
 114         DEVICE( CMD,            CMD_640,        "640 (buggy)"),
 115         DEVICE( CMD,            CMD_646,        "646"),
 116         DEVICE( VISION,         VISION_QD8500,  "QD-8500"),
 117         DEVICE( VISION,         VISION_QD8580,  "QD-8580"),
 118         DEVICE( WINBOND,        WINBOND_83769,  "W83769F"),
 119         DEVICE( 3COM,           3COM_3C590,     "3C590 10bT"),
 120         DEVICE( 3COM,           3COM_3C595TX,   "3C595 100bTX"),
 121         DEVICE( 3COM,           3COM_3C595T4,   "3C595 100bT4"),
 122         DEVICE( 3COM,           3COM_3C595MII,  "3C595 100b-MII"),
 123         DEVICE( AL,             AL_M1445,       "M1445"),
 124         DEVICE( AL,             AL_M1449,       "M1449"),
 125         DEVICE( AL,             AL_M1451,       "M1451"),
 126         DEVICE( AL,             AL_M1461,       "M1461"),
 127         DEVICE( AL,             AL_M4803,       "M4803"),
 128         DEVICE( IMS,            IMS_8849,       "8849"),
 129         DEVICE( REALTEK,        REALTEK_8029,   "8029"),
 130         DEVICE( VIA,            VIA_82C505,     "VT 82C505"),
 131         DEVICE( VIA,            VIA_82C561,     "VT 82C561"),
 132         DEVICE( VIA,            VIA_82C576,     "VT 82C576 3V"),
 133         DEVICE( VORTEX,         VORTEX_GDT,     "GDT 6000b"),
 134         DEVICE( EF,             EF_ATM,         "155P-MF1"),
 135         DEVICE( IMAGINGTECH,    IMAGINGTECH_ICPCI, "MVC IC-PCI"),
 136         DEVICE( PLX,            PLX_9060,       "PCI9060 i960 bridge"),
 137         DEVICE( MUTECH,         MUTECH_MV1000,  "MV-1000"),
 138         DEVICE( ZEINET,         ZEINET_1221,    "1221"),
 139         DEVICE( CYCLADES,       CYCLADES_Y,     "Cyclome-Y"),
 140         DEVICE( SYMPHONY,       SYMPHONY_101,   "82C101"),
 141         DEVICE( TEKRAM,         TEKRAM_DC290,   "DC-290"),
 142         DEVICE( S3,             S3_811,         "Trio32/Trio64"),
 143         DEVICE( S3,             S3_868, "Vision 868"),
 144         DEVICE( S3,             S3_928,         "Vision 928-P"),
 145         DEVICE( S3,             S3_864_1,       "Vision 864-P"),
 146         DEVICE( S3,             S3_864_2,       "Vision 864-P"),
 147         DEVICE( S3,             S3_964_1,       "Vision 964-P"),
 148         DEVICE( S3,             S3_964_2,       "Vision 964-P"),
 149         DEVICE( S3,             S3_968,         "Vision 968"),
 150         DEVICE( INTEL,          INTEL_82375,    "82375EB"),
 151         BRIDGE( INTEL,          INTEL_82424,    "82424ZX Saturn",       0x00),
 152         DEVICE( INTEL,          INTEL_82378,    "82378IB"),
 153         DEVICE( INTEL,          INTEL_82430,    "82430ZX Aries"),
 154         BRIDGE( INTEL,          INTEL_82434,    "82434LX Mercury/Neptune", 0x00),
 155         DEVICE( INTEL,          INTEL_7116,     "SAA7116"),
 156         DEVICE( INTEL,          INTEL_82865,    "82865"),
 157         DEVICE( INTEL,          INTEL_82437,    "82437"),
 158         DEVICE( INTEL,          INTEL_82371_0,  "82371 Triton PIIX"),
 159         DEVICE( INTEL,          INTEL_82371_1,  "82371 Triton PIIX"),
 160         DEVICE( INTEL,          INTEL_P6,       "Experimental P6 bridge"),
 161         DEVICE( ADAPTEC,        ADAPTEC_7850,   "AIC-7850"),
 162         DEVICE( ADAPTEC,        ADAPTEC_294x,   "294x"),
 163         DEVICE( ADAPTEC,        ADAPTEC_2940,   "2940"),
 164         DEVICE( ADAPTEC,        ADAPTEC_7872,   "AIC-7872"),
 165         DEVICE( ATRONICS,       ATRONICS_2015,  "IDE-2015PL"),
 166         DEVICE( HER,            HER_STING,      "Stingray"),
 167         DEVICE( HER,            HER_STINGARK,   "Stingray ARK 2000PV")
 168 };
 169 
 170 
 171 #ifdef CONFIG_PCI_OPTIMIZE
 172 
 173 /*
 174  * An item of this structure has the following meaning:
 175  * for each optimization, the register address, the mask
 176  * and value to write to turn it on.
 177  * There are 5 optimizations for the moment:
 178  * Cache L2 write back best than write through
 179  * Posted Write for CPU to PCI enable
 180  * Posted Write for CPU to MEMORY enable
 181  * Posted Write for PCI to MEMORY enable
 182  * PCI Burst enable
 183  *
 184  * Half of the bios I've meet don't allow you to turn that on, and you
 185  * can gain more than 15% on graphic accesses using those
 186  * optimizations...
 187  */
 188 struct optimization_type {
 189         const char      *type;
 190         const char      *off;
 191         const char      *on;
 192 } bridge_optimization[] = {
 193         {"Cache L2",                    "write trough", "write back"},
 194         {"CPU-PCI posted write",        "off",          "on"},
 195         {"CPU-Memory posted write",     "off",          "on"},
 196         {"PCI-Memory posted write",     "off",          "on"},
 197         {"PCI burst",                   "off",          "on"}
 198 };
 199 
 200 #define NUM_OPTIMIZATIONS \
 201         (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
 202 
 203 struct bridge_mapping_type {
 204         unsigned char   addr;   /* config space address */
 205         unsigned char   mask;
 206         unsigned char   value;
 207 } bridge_mapping[] = {
 208         /*
 209          * Intel Neptune/Mercury/Saturn:
 210          *      If the internal cache is write back,
 211          *      the L2 cache must be write through!
 212          *      I've to check out how to control that
 213          *      for the moment, we won't touch the cache
 214          */
 215         {0x0    ,0x02   ,0x02   },
 216         {0x53   ,0x02   ,0x02   },
 217         {0x53   ,0x01   ,0x01   },
 218         {0x54   ,0x01   ,0x01   },
 219         {0x54   ,0x02   ,0x02   },
 220 
 221         /*
 222          * UMC 8891A Pentium chipset:
 223          *      Why did you think UMC was cheaper ??
 224          */
 225         {0x50   ,0x10   ,0x00   },
 226         {0x51   ,0x40   ,0x40   },
 227         {0x0    ,0x0    ,0x0    },
 228         {0x0    ,0x0    ,0x0    },
 229         {0x0    ,0x0    ,0x0    },
 230 
 231         /*
 232          * UMC UM8881F
 233          *      This is a dummy entry for my tests.
 234          *      I have this chipset and no docs....
 235          */
 236         {0x0    ,0x1    ,0x1    },
 237         {0x0    ,0x2    ,0x0    },
 238         {0x0    ,0x0    ,0x0    },
 239         {0x0    ,0x0    ,0x0    },
 240         {0x0    ,0x0    ,0x0    }
 241 };
 242 
 243 #endif /* CONFIG_PCI_OPTIMIZE */
 244 
 245 
 246 /*
 247  * device_info[] is sorted so we can use binary search
 248  */
 249 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
     /*  */
 250 {
 251         int min = 0,
 252             max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
 253 
 254         for ( ; ; )
 255         {
 256             int i = (min + max) >> 1;
 257             long order;
 258 
 259             order = dev_info[i].vendor - (long) vendor;
 260             if (!order)
 261                 order = dev_info[i].device - (long) dev;
 262         
 263             if (order < 0)
 264             {
 265                     min = i + 1;
 266                     if ( min > max )
 267                        return 0;
 268                     continue;
 269             }
 270 
 271             if (order > 0)
 272             {
 273                     max = i - 1;
 274                     if ( min > max )
 275                        return 0;
 276                     continue;
 277             }
 278 
 279             return & dev_info[ i ];
 280         }
 281 }
 282 
 283 
 284 const char *pci_strbioserr (int error)
     /*  */
 285 {
 286         switch (error) {
 287               case PCIBIOS_SUCCESSFUL:          return "SUCCESSFUL";
 288               case PCIBIOS_FUNC_NOT_SUPPORTED:  return "FUNC_NOT_SUPPORTED";
 289               case PCIBIOS_BAD_VENDOR_ID:       return "SUCCESSFUL";
 290               case PCIBIOS_DEVICE_NOT_FOUND:    return "DEVICE_NOT_FOUND";
 291               case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
 292               case PCIBIOS_SET_FAILED:          return "SET_FAILED";
 293               case PCIBIOS_BUFFER_TOO_SMALL:    return "BUFFER_TOO_SMALL";
 294               default:                          return "Unknown error status";
 295         }
 296 }
 297 
 298 
 299 const char *pci_strclass (unsigned int class)
     /*  */
 300 {
 301         switch (class >> 8) {
 302               case PCI_CLASS_NOT_DEFINED:               return "Non-VGA device";
 303               case PCI_CLASS_NOT_DEFINED_VGA:           return "VGA compatible device";
 304 
 305               case PCI_CLASS_STORAGE_SCSI:              return "SCSI storage controller";
 306               case PCI_CLASS_STORAGE_IDE:               return "IDE interface";
 307               case PCI_CLASS_STORAGE_FLOPPY:            return "Floppy disk controller";
 308               case PCI_CLASS_STORAGE_IPI:               return "IPI bus controller";
 309               case PCI_CLASS_STORAGE_RAID:              return "RAID bus controller";
 310               case PCI_CLASS_STORAGE_OTHER:             return "Unknown mass storage controller";
 311 
 312               case PCI_CLASS_NETWORK_ETHERNET:          return "Ethernet controller";
 313               case PCI_CLASS_NETWORK_TOKEN_RING:        return "Token ring network controller";
 314               case PCI_CLASS_NETWORK_FDDI:              return "FDDI network controller";
 315               case PCI_CLASS_NETWORK_ATM:               return "ATM network controller";
 316               case PCI_CLASS_NETWORK_OTHER:             return "Network controller";
 317 
 318               case PCI_CLASS_DISPLAY_VGA:               return "VGA compatible controller";
 319               case PCI_CLASS_DISPLAY_XGA:               return "XGA compatible controller";
 320               case PCI_CLASS_DISPLAY_OTHER:             return "Display controller";
 321 
 322               case PCI_CLASS_MULTIMEDIA_VIDEO:          return "Multimedia video controller";
 323               case PCI_CLASS_MULTIMEDIA_AUDIO:          return "Multimedia audio controller";
 324               case PCI_CLASS_MULTIMEDIA_OTHER:          return "Multimedia controller";
 325 
 326               case PCI_CLASS_MEMORY_RAM:                return "RAM memory";
 327               case PCI_CLASS_MEMORY_FLASH:              return "FLASH memory";
 328               case PCI_CLASS_MEMORY_OTHER:              return "Memory";
 329 
 330               case PCI_CLASS_BRIDGE_HOST:               return "Host bridge";
 331               case PCI_CLASS_BRIDGE_ISA:                return "ISA bridge";
 332               case PCI_CLASS_BRIDGE_EISA:               return "EISA bridge";
 333               case PCI_CLASS_BRIDGE_MC:                 return "MicroChannel bridge";
 334               case PCI_CLASS_BRIDGE_PCI:                return "PCI bridge";
 335               case PCI_CLASS_BRIDGE_PCMCIA:             return "PCMCIA bridge";
 336               case PCI_CLASS_BRIDGE_NUBUS:              return "NuBus bridge";
 337               case PCI_CLASS_BRIDGE_CARDBUS:            return "CardBus bridge";
 338               case PCI_CLASS_BRIDGE_OTHER:              return "Bridge";
 339 
 340               case PCI_CLASS_COMMUNICATION_SERIAL:      return "Serial controller";
 341               case PCI_CLASS_COMMUNICATION_PARALLEL:    return "Parallel controller";
 342               case PCI_CLASS_COMMUNICATION_OTHER:       return "Communication controller";
 343 
 344               case PCI_CLASS_SYSTEM_PIC:                return "PIC";
 345               case PCI_CLASS_SYSTEM_DMA:                return "DMA controller";
 346               case PCI_CLASS_SYSTEM_TIMER:              return "Timer";
 347               case PCI_CLASS_SYSTEM_RTC:                return "RTC";
 348               case PCI_CLASS_SYSTEM_OTHER:              return "System peripheral";
 349 
 350               case PCI_CLASS_INPUT_KEYBOARD:            return "Keyboard controller";
 351               case PCI_CLASS_INPUT_PEN:                 return "Digitizer Pen";
 352               case PCI_CLASS_INPUT_MOUSE:               return "Mouse controller";
 353               case PCI_CLASS_INPUT_OTHER:               return "Input device controller";
 354 
 355               case PCI_CLASS_DOCKING_GENERIC:           return "Generic Docking Station";
 356               case PCI_CLASS_DOCKING_OTHER:             return "Docking Station";
 357 
 358               case PCI_CLASS_PROCESSOR_386:             return "386";
 359               case PCI_CLASS_PROCESSOR_486:             return "486";
 360               case PCI_CLASS_PROCESSOR_PENTIUM:         return "Pentium";
 361               case PCI_CLASS_PROCESSOR_ALPHA:           return "Alpha";
 362               case PCI_CLASS_PROCESSOR_POWERPC:         return "Power PC";
 363               case PCI_CLASS_PROCESSOR_CO:              return "Co-processor";
 364 
 365               case PCI_CLASS_SERIAL_FIREWIRE:           return "FireWire (IEEE 1394)";
 366               case PCI_CLASS_SERIAL_ACCESS:             return "ACCESS Bus";
 367               case PCI_CLASS_SERIAL_SSA:                return "SSA";
 368               case PCI_CLASS_SERIAL_FIBER:              return "Fiber Channel";
 369 
 370               default:                                  return "Unknown class";
 371         }
 372 }
 373 
 374 
 375 const char *pci_strvendor(unsigned int vendor)
     /*  */
 376 {
 377         switch (vendor) {
 378               case PCI_VENDOR_ID_NCR:           return "NCR";
 379               case PCI_VENDOR_ID_ADAPTEC:       return "Adaptec";
 380               case PCI_VENDOR_ID_DPT:           return "DPT";
 381               case PCI_VENDOR_ID_S3:            return "S3 Inc.";
 382               case PCI_VENDOR_ID_OPTI:          return "OPTI";
 383               case PCI_VENDOR_ID_UMC:           return "UMC";
 384               case PCI_VENDOR_ID_DEC:           return "DEC";
 385               case PCI_VENDOR_ID_MATROX:        return "Matrox";
 386               case PCI_VENDOR_ID_INTEL:         return "Intel";
 387 #if 0
 388               case PCI_VENDOR_ID_SMC:           return "SMC";
 389 #else
 390               case PCI_VENDOR_ID_PCTECH:        return "PCTECH";
 391 #endif
 392               case PCI_VENDOR_ID_ATI:           return "ATI";
 393               case PCI_VENDOR_ID_WEITEK:        return "Weitek";
 394               case PCI_VENDOR_ID_CIRRUS:        return "Cirrus Logic";
 395               case PCI_VENDOR_ID_BUSLOGIC:      return "Bus Logic";
 396               case PCI_VENDOR_ID_N9:            return "Number Nine";
 397               case PCI_VENDOR_ID_AI:            return "Acer Incorporated";
 398               case PCI_VENDOR_ID_AL:            return "Acer Labs";
 399               case PCI_VENDOR_ID_TSENG:         return "Tseng'Lab";
 400               case PCI_VENDOR_ID_CMD:           return "CMD";
 401               case PCI_VENDOR_ID_VISION:        return "Vision";
 402               case PCI_VENDOR_ID_AMD:           return "AMD";
 403               case PCI_VENDOR_ID_VLSI:          return "VLSI";
 404               case PCI_VENDOR_ID_ADL:           return "Advance Logic";
 405               case PCI_VENDOR_ID_SYMPHONY:      return "Symphony";
 406               case PCI_VENDOR_ID_TRIDENT:       return "Trident";
 407               case PCI_VENDOR_ID_CONTAQ:        return "Contaq";
 408               case PCI_VENDOR_ID_NS:            return "NS";
 409               case PCI_VENDOR_ID_VIA:           return "VIA Technologies";
 410               case PCI_VENDOR_ID_SI:            return "Silicon Integrated Systems";
 411               case PCI_VENDOR_ID_LEADTEK:       return "Leadtek Research";
 412               case PCI_VENDOR_ID_IMS:           return "IMS";
 413               case PCI_VENDOR_ID_ZEINET:        return "ZeiNet";
 414               case PCI_VENDOR_ID_EF:            return "Efficient Networks";
 415               case PCI_VENDOR_ID_HER:           return "Hercules";
 416               case PCI_VENDOR_ID_ATRONICS:      return "Atronics";
 417               case PCI_VENDOR_ID_CT:            return "Chips & Technologies";
 418               case PCI_VENDOR_ID_FD:            return "Future Domain";
 419               case PCI_VENDOR_ID_WINBOND:       return "Winbond";
 420               case PCI_VENDOR_ID_3COM:          return "3Com";
 421               case PCI_VENDOR_ID_PROMISE:       return "Promise Technology";
 422               case PCI_VENDOR_ID_QLOGIC:        return "Q Logic";
 423               case PCI_VENDOR_ID_X:             return "X TECHNOLOGY";
 424               case PCI_VENDOR_ID_ACC:           return "ACC MICROELECTRONICS";
 425               case PCI_VENDOR_ID_VORTEX:        return "VORTEX";
 426               case PCI_VENDOR_ID_HP:            return "Hewlett Packard";
 427               case PCI_VENDOR_ID_IMAGINGTECH:   return "Imaging Technology";
 428               case PCI_VENDOR_ID_CYCLADES:      return "Cyclades";
 429               case PCI_VENDOR_ID_OLICOM:        return "Olicom";
 430               default:                          return "Unknown vendor";
 431         }
 432 }
 433 
 434 
 435 const char *pci_strdev(unsigned int vendor, unsigned int device)
     /*  */
 436 {
 437         struct pci_dev_info *info;
 438 
 439         info =  pci_lookup_dev(vendor, device);
 440         return info ? info->name : "Unknown device";
 441 }
 442 
 443 
 444 
 445 /*
 446  * Turn on/off PCI bridge optimization. This should allow benchmarking.
 447  */
 448 static void burst_bridge(unsigned char bus, unsigned char devfn,
     /*  */
 449                          unsigned char pos, int turn_on)
 450 {
 451 #ifdef CONFIG_PCI_OPTIMIZE
 452         struct bridge_mapping_type *bmap;
 453         unsigned char val;
 454         int i;
 455 
 456         pos *= NUM_OPTIMIZATIONS;
 457         printk("PCI bridge optimization.\n");
 458         for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
 459                 printk("    %s: ", bridge_optimization[i].type);
 460                 bmap = &bridge_mapping[pos + i];
 461                 if (!bmap->addr) {
 462                         printk("Not supported.");
 463                 } else {
 464                         pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
 465                         if ((val & bmap->mask) == bmap->value) {
 466                                 printk("%s.", bridge_optimization[i].on);
 467                                 if (!turn_on) {
 468                                         pcibios_write_config_byte(bus, devfn,
 469                                                                   bmap->addr,
 470                                                                   (val | bmap->mask)
 471                                                                   - bmap->value);
 472                                         printk("Changed!  Now %s.", bridge_optimization[i].off);
 473                                 }
 474                         } else {
 475                                 printk("%s.", bridge_optimization[i].off);
 476                                 if (turn_on) {
 477                                         pcibios_write_config_byte(bus, devfn,
 478                                                                   bmap->addr,
 479                                                                   (val & (0xff - bmap->mask))
 480                                                                   + bmap->value);
 481                                         printk("Changed!  Now %s.", bridge_optimization[i].on);
 482                                 }
 483                         }
 484                 }
 485                 printk("\n");
 486         }
 487 #endif /* CONFIG_PCI_OPTIMIZE */
 488 }
 489 
 490 
 491 /*
 492  * Convert some of the configuration space registers of the device at
 493  * address (bus,devfn) into a string (possibly several lines each).
 494  * The configuration string is stored starting at buf[len].  If the
 495  * string would exceed the size of the buffer (SIZE), 0 is returned.
 496  */
 497 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
     /*  */
 498 {
 499         unsigned long base;
 500         unsigned int l, class_rev, bus, devfn;
 501         unsigned short vendor, device, status;
 502         unsigned char bist, latency, min_gnt, max_lat;
 503         int reg, len = 0;
 504         const char *str;
 505 
 506         bus   = dev->bus->number;
 507         devfn = dev->devfn;
 508 
 509         pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
 510         pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
 511         pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
 512         pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
 513         pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
 514         pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
 515         pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
 516         pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
 517         if (len + 80 > size) {
 518                 return -1;
 519         }
 520         len += sprintf(buf + len, "  Bus %2d, device %3d, function %2d:\n",
 521                        bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
 522 
 523         if (len + 80 > size) {
 524                 return -1;
 525         }
 526         len += sprintf(buf + len, "    %s: %s %s (rev %d).\n      ",
 527                        pci_strclass(class_rev >> 8), pci_strvendor(vendor),
 528                        pci_strdev(vendor, device), class_rev & 0xff);
 529 
 530         if (!pci_lookup_dev(vendor, device)) {
 531                 len += sprintf(buf + len,
 532                                "Vendor id=%x. Device id=%x.\n      ",
 533                                vendor, device);
 534         }
 535 
 536         str = 0;        /* to keep gcc shut... */
 537         switch (status & PCI_STATUS_DEVSEL_MASK) {
 538               case PCI_STATUS_DEVSEL_FAST:   str = "Fast devsel.  "; break;
 539               case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel.  "; break;
 540               case PCI_STATUS_DEVSEL_SLOW:   str = "Slow devsel.  "; break;
 541         }
 542         if (len + strlen(str) > size) {
 543                 return -1;
 544         }
 545         len += sprintf(buf + len, str);
 546 
 547         if (status & PCI_STATUS_FAST_BACK) {
 548 #               define fast_b2b_capable "Fast back-to-back capable.  "
 549                 if (len + strlen(fast_b2b_capable) > size) {
 550                         return -1;
 551                 }
 552                 len += sprintf(buf + len, fast_b2b_capable);
 553 #               undef fast_b2b_capable
 554         }
 555 
 556         if (bist & PCI_BIST_CAPABLE) {
 557 #               define BIST_capable     "BIST capable.  "
 558                 if (len + strlen(BIST_capable) > size) {
 559                         return -1;
 560                 }
 561                 len += sprintf(buf + len, BIST_capable);
 562 #               undef BIST_capable
 563         }
 564 
 565         if (dev->irq) {
 566                 if (len + 40 > size) {
 567                         return -1;
 568                 }
 569                 len += sprintf(buf + len, "IRQ %d.  ", dev->irq);
 570         }
 571 
 572         if (dev->master) {
 573                 if (len + 80 > size) {
 574                         return -1;
 575                 }
 576                 len += sprintf(buf + len, "Master Capable.  ");
 577                 if (latency)
 578                   len += sprintf(buf + len, "Latency=%d.  ", latency);
 579                 else
 580                   len += sprintf(buf + len, "No bursts.  ");
 581                 if (min_gnt)
 582                   len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
 583                 if (max_lat)
 584                   len += sprintf(buf + len, "Max Lat=%d.", max_lat);
 585         }
 586 
 587         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 588                 if (len + 40 > size) {
 589                         return -1;
 590                 }
 591                 pcibios_read_config_dword(bus, devfn, reg, &l);
 592                 base = l;
 593                 if (!base) {
 594                         continue;
 595                 }
 596 
 597                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 598                         len += sprintf(buf + len,
 599                                        "\n      I/O at 0x%lx.",
 600                                        base & PCI_BASE_ADDRESS_IO_MASK);
 601                 } else {
 602                         const char *pref, *type = "unknown";
 603 
 604                         if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 605                                 pref = "P";
 606                         } else {
 607                                 pref = "Non-p";
 608                         }
 609                         switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
 610                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 611                                 type = "32 bit"; break;
 612                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 613                                 type = "20 bit"; break;
 614                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 615                                 type = "64 bit";
 616                                 /* read top 32 bit address of base addr: */
 617                                 reg += 4;
 618                                 pcibios_read_config_dword(bus, devfn, reg, &l);
 619                                 base |= ((u64) l) << 32;
 620                                 break;
 621                         }
 622                         len += sprintf(buf + len,
 623                                        "\n      %srefetchable %s memory at "
 624                                        "0x%lx.", pref, type,
 625                                        base & PCI_BASE_ADDRESS_MEM_MASK);
 626                 }
 627         }
 628 
 629         len += sprintf(buf + len, "\n");
 630         return len;
 631 }
 632 
 633 
 634 /*
 635  * Return list of PCI devices as a character string for /proc/pci.
 636  * BUF is a buffer that is PAGE_SIZE bytes long.
 637  */
 638 int get_pci_list(char *buf)
     /*  */
 639 {
 640         int nprinted, len, size;
 641         struct pci_dev *dev;
 642 #       define MSG "\nwarning: page-size limit reached!\n"
 643 
 644         /* reserve same for truncation warning message: */
 645         size  = PAGE_SIZE - (strlen(MSG) + 1);
 646         len   = sprintf(buf, "PCI devices found:\n");
 647 
 648         for (dev = pci_devices; dev; dev = dev->next) {
 649                 nprinted = sprint_dev_config(dev, buf + len, size - len);
 650                 if (nprinted < 0) {
 651                         return len + sprintf(buf + len, MSG);
 652                 }
 653                 len += nprinted;
 654         }
 655         return len;
 656 }
 657 
 658 
 659 /*
 660  * pci_malloc() returns initialized memory of size SIZE.  Can be
 661  * used only while pci_init() is active.
 662  */
 663 static void *pci_malloc(long size, unsigned long *mem_startp)
     /*  */
 664 {
 665         void *mem;
 666 
 667 #ifdef DEBUG
 668         printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
 669 #endif
 670         mem = (void*) *mem_startp;
 671         *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
 672         memset(mem, 0, size);
 673         return mem;
 674 }
 675 
 676 
 677 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
     /*  */
 678 {
 679         unsigned int devfn, l, max;
 680         unsigned char cmd, tmp, hdr_type = 0;
 681         struct pci_dev_info *info;
 682         struct pci_dev *dev;
 683         struct pci_bus *child;
 684 
 685 #ifdef DEBUG
 686         printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
 687 #endif
 688 
 689         max = bus->secondary;
 690         for (devfn = 0; devfn < 0xff; ++devfn) {
 691                 if (PCI_FUNC(devfn) == 0) {
 692                         pcibios_read_config_byte(bus->number, devfn,
 693                                                  PCI_HEADER_TYPE, &hdr_type);
 694                 } else if (!(hdr_type & 0x80)) {
 695                         /* not a multi-function device */
 696                         continue;
 697                 }
 698 
 699                 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
 700                                           &l);
 701                 /* some broken boards return 0 if a slot is empty: */
 702                 if (l == 0xffffffff || l == 0x00000000) {
 703                         hdr_type = 0;
 704                         continue;
 705                 }
 706 
 707                 dev = pci_malloc(sizeof(*dev), mem_startp);
 708                 dev->bus = bus;
 709                 /*
 710                  * Put it into the simple chain of devices on this
 711                  * bus.  It is used to find devices once everything is
 712                  * set up.
 713                  */
 714                 dev->next = pci_devices;
 715                 pci_devices = dev;
 716 
 717                 dev->devfn  = devfn;
 718                 dev->vendor = l & 0xffff;
 719                 dev->device = (l >> 16) & 0xffff;
 720 
 721                 /*
 722                  * Check to see if we now about this device and report
 723                  * a message at boot time.  This is the only way to
 724                  * learn about new hardware...
 725                  */
 726                 info = pci_lookup_dev(dev->vendor, dev->device);
 727                 if (!info) {
 728                         printk("Warning : Unknown PCI device (%x:%x).  Please read include/linux/pci.h \n",
 729                                 dev->vendor, dev->device);
 730                 } else {
 731                         /* Some BIOS' are lazy. Let's do their job: */
 732                         if (info->bridge_type != 0xff) {
 733                                 burst_bridge(bus->number, devfn,
 734                                              info->bridge_type, 1);
 735                         }
 736                 }
 737 
 738                 /* non-destructively determine if device can be a master: */
 739                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 740                                          &cmd);
 741                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 742                                           cmd | PCI_COMMAND_MASTER);
 743                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 744                                          &tmp);
 745                 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
 746                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 747                                           cmd);
 748 
 749                 /* read irq level (may be changed during pcibios_fixup()): */
 750                 pcibios_read_config_byte(bus->number, devfn,
 751                                          PCI_INTERRUPT_LINE, &dev->irq);
 752 
 753                 /* check to see if this device is a PCI-PCI bridge: */
 754                 pcibios_read_config_dword(bus->number, devfn,
 755                                           PCI_CLASS_REVISION, &l);
 756                 l = l >> 8;                     /* upper 3 bytes */
 757                 dev->class = l;
 758                 /*
 759                  * Now insert it into the list of devices held
 760                  * by the parent bus.
 761                  */
 762                 dev->sibling = bus->devices;
 763                 bus->devices = dev;
 764 
 765                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
 766                         unsigned int buses;
 767                         unsigned short cr;
 768 
 769                         /*
 770                          * Insert it into the tree of buses.
 771                          */
 772                         child = pci_malloc(sizeof(*child), mem_startp);
 773                         child->next   = bus->children;
 774                         bus->children = child;
 775                         child->self = dev;
 776                         child->parent = bus;
 777 
 778                         /*
 779                          * Set up the primary, secondary and subordinate
 780                          * bus numbers.
 781                          */
 782                         child->number = child->secondary = ++max;
 783                         child->primary = bus->secondary;
 784                         child->subordinate = 0xff;
 785                         /*
 786                          * Clear all status bits and turn off memory,
 787                          * I/O and master enables.
 788                          */
 789                         pcibios_read_config_word(bus->number, devfn,
 790                                                   PCI_COMMAND, &cr);
 791                         pcibios_write_config_word(bus->number, devfn,
 792                                                   PCI_COMMAND, 0x0000);
 793                         pcibios_write_config_word(bus->number, devfn,
 794                                                   PCI_STATUS, 0xffff);
 795                         /*
 796                          * Configure the bus numbers for this bridge:
 797                          */
 798                         pcibios_read_config_dword(bus->number, devfn, 0x18,
 799                                                   &buses);
 800                         buses &= 0xff000000;
 801                         buses |= (((unsigned int)(child->primary)     <<  0) |
 802                                   ((unsigned int)(child->secondary)   <<  8) |
 803                                   ((unsigned int)(child->subordinate) << 16));
 804                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 805                                                    buses);
 806                         /*
 807                          * Now we can scan all subordinate buses:
 808                          */
 809                         max = scan_bus(child, mem_startp);
 810                         /*
 811                          * Set the subordinate bus number to its real
 812                          * value:
 813                          */
 814                         child->subordinate = max;
 815                         buses = (buses & 0xff00ffff)
 816                           | ((unsigned int)(child->subordinate) << 16);
 817                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 818                                                    buses);
 819                         pcibios_write_config_word(bus->number, devfn,
 820                                                   PCI_COMMAND, cr);
 821                 }
 822         }
 823         /*
 824          * We've scanned the bus and so we know all about what's on
 825          * the other side of any bridges that may be on this bus plus
 826          * any devices.
 827          *
 828          * Return how far we've got finding sub-buses.
 829          */
 830         return max;
 831 }
 832 
 833 
 834 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
     /*  */
 835 {
 836         mem_start = pcibios_init(mem_start, mem_end);
 837 
 838         if (!pcibios_present()) {
 839                 printk("pci_init: no BIOS32 detected\n");
 840                 return mem_start;
 841         }
 842 
 843         printk("Probing PCI hardware.\n");
 844 
 845         memset(&pci_root, 0, sizeof(pci_root));
 846         pci_root.subordinate = scan_bus(&pci_root, &mem_start);
 847 
 848         /* give BIOS a chance to apply platform specific fixes: */
 849         mem_start = pcibios_fixup(mem_start, mem_end);
 850 
 851 #ifdef DEBUG
 852         {
 853                 int len = get_pci_list((char*)mem_start);
 854                 if (len) {
 855                         ((char *) mem_start)[len] = '\0';
 856                         printk("%s\n", (char *) mem_start);
 857                 }
 858         }
 859 #endif
 860         return mem_start;
 861 }
/* */
root/drivers/pci/pci.c

DEFINITIONS
