include/linux/pci.h

/* */
   1 /*
   2  * PCI defines and function prototypes
   3  * Copyright 1994, Drew Eckhardt
   4  *
   5  * For more information, please consult 
   6  * 
   7  * PCI BIOS Specification Revision
   8  * PCI Local Bus Specification
   9  * PCI System Design Guide
  10  *
  11  * PCI Special Interest Group
  12  * M/S HF3-15A
  13  * 5200 N.E. Elam Young Parkway
  14  * Hillsboro, Oregon 97124-6497
  15  * +1 (503) 696-2000 
  16  * +1 (800) 433-5177
  17  * 
  18  * Manuals are $25 each or $50 for all three, plus $7 shipping 
  19  * within the United States, $35 abroad.
  20  */
  21 
  22 
  23 
  24 /*      PROCEDURE TO REPORT NEW PCI DEVICES
  25  * We are trying to collect informations on new PCI devices, using
  26  * the standart PCI identification procedure. If some warning is
  27  * displayed at boot time, please report 
  28  *      - /proc/pci
  29  *      - your exact hardware description. Try to find out
  30  *        which device is unknown. It may be you mainboard chipset.
  31  *        PCI-CPU bridge or PCI-ISA bridge.
  32  *      - If you can't find the actual information in your hardware
  33  *        booklet, try to read the references of the chip on the board.
  34  *      - Send all that, with the word PCIPROBE in the subject,
  35  *        to frederic@cao-vlsi.ibp.fr, and I'll add your device to 
  36  *        the list as soon as possible
  37  *              fred.
  38  */
  39 
  40 
  41 
  42 #ifndef PCI_H
  43 #define PCI_H
  44 
  45 /*
  46  * Under PCI, each device has 256 bytes of configuration address space,
  47  * of which the first 64 bytes are standardized as follows:
  48  */
  49 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  50 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  51 #define PCI_COMMAND             0x04    /* 16 bits */
  52 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  53 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  54 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  55 #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  56 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  57 #define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
  58 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  59 #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  60 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  61 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  62 
  63 #define PCI_STATUS              0x06    /* 16 bits */
  64 #define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
  65 #define  PCI_STATUS_UDF         0x40    /* Support User Definable Features */
  66 
  67 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  68 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  69 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  70 #define  PCI_STATUS_DEVSEL_FAST 0x000   
  71 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  72 #define  PCI_STATUS_DEVSEL_SLOW 0x400
  73 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  74 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  75 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  76 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  77 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  78 
  79 #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
  80                                            revision */
  81 #define PCI_REVISION_ID         0x08    /* Revision ID */
  82 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  83 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  84 
  85 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  86 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  87 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  88 #define PCI_BIST                0x0f    /* 8 bits */
  89 #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
  90 #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
  91 #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
  92 
  93 /*
  94  * Base addresses specify locations in memory or I/O space.
  95  * Decoded size can be determined by writing a value of 
  96  * 0xffffffff to the register, and reading it back.  Only 
  97  * 1 bits are decoded.
  98  */
  99 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
 100 #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
 101 #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
 102 #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
 103 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
 104 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
 105 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
 106 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
 107 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
 108 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 109 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
 110 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
 111 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 112 #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
 113 #define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0f)
 114 #define  PCI_BASE_ADDRESS_IO_MASK       (~0x03)
 115 /* bit 1 is reserved if address_space = 1 */
 116 
 117 #define PCI_CARDBUS_CIS         0x28
 118 #define PCI_SUBSYSTEM_ID        0x2c
 119 #define PCI_SUBSYSTEM_VENDOR_ID 0x2e  
 120 #define PCI_ROM_ADDRESS         0x30    /* 32 bits */
 121 #define  PCI_ROM_ADDRESS_ENABLE 0x01    /* Write 1 to enable ROM,
 122                                            bits 31..11 are address,
 123                                            10..2 are reserved */
 124 /* 0x34-0x3b are reserved */
 125 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 126 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 127 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 128 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 129 
 130 #define PCI_CLASS_NOT_DEFINED           0x0000
 131 #define PCI_CLASS_NOT_DEFINED_VGA       0x0001
 132 
 133 #define PCI_BASE_CLASS_STORAGE          0x01
 134 #define PCI_CLASS_STORAGE_SCSI          0x0100
 135 #define PCI_CLASS_STORAGE_IDE           0x0101
 136 #define PCI_CLASS_STORAGE_FLOPPY        0x0102
 137 #define PCI_CLASS_STORAGE_IPI           0x0103
 138 #define PCI_CLASS_STORAGE_RAID          0x0104
 139 #define PCI_CLASS_STORAGE_OTHER         0x0180
 140 
 141 #define PCI_BASE_CLASS_NETWORK          0x02
 142 #define PCI_CLASS_NETWORK_ETHERNET      0x0200
 143 #define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
 144 #define PCI_CLASS_NETWORK_FDDI          0x0202
 145 #define PCI_CLASS_NETWORK_ATM           0x0203
 146 #define PCI_CLASS_NETWORK_OTHER         0x0280
 147 
 148 #define PCI_BASE_CLASS_DISPLAY          0x03
 149 #define PCI_CLASS_DISPLAY_VGA           0x0300
 150 #define PCI_CLASS_DISPLAY_XGA           0x0301
 151 #define PCI_CLASS_DISPLAY_OTHER         0x0380
 152 
 153 #define PCI_BASE_CLASS_MULTIMEDIA       0x04
 154 #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
 155 #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
 156 #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
 157 
 158 #define PCI_BASE_CLASS_MEMORY           0x05
 159 #define  PCI_CLASS_MEMORY_RAM           0x0500
 160 #define  PCI_CLASS_MEMORY_FLASH         0x0501
 161 #define  PCI_CLASS_MEMORY_OTHER         0x0580
 162 
 163 #define PCI_BASE_CLASS_BRIDGE           0x06
 164 #define  PCI_CLASS_BRIDGE_HOST          0x0600
 165 #define  PCI_CLASS_BRIDGE_ISA           0x0601
 166 #define  PCI_CLASS_BRIDGE_EISA          0x0602
 167 #define  PCI_CLASS_BRIDGE_MC            0x0603
 168 #define  PCI_CLASS_BRIDGE_PCI           0x0604
 169 #define  PCI_CLASS_BRIDGE_PCMCIA        0x0605
 170 #define  PCI_CLASS_BRIDGE_NUBUS         0x0606
 171 #define  PCI_CLASS_BRIDGE_CARDBUS       0x0607
 172 #define  PCI_CLASS_BRIDGE_OTHER         0x0680
 173 
 174 
 175 #define PCI_BASE_CLASS_COMMUNICATION    0x07
 176 #define PCI_CLASS_COMMUNICATION_SERIAL  0x0700
 177 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
 178 #define PCI_CLASS_COMMUNICATION_OTHER   0x0780
 179 
 180 #define PCI_BASE_CLASS_SYSTEM           0x08
 181 #define PCI_CLASS_SYSTEM_PIC            0x0800
 182 #define PCI_CLASS_SYSTEM_DMA            0x0801
 183 #define PCI_CLASS_SYSTEM_TIMER          0x0802
 184 #define PCI_CLASS_SYSTEM_RTC            0x0803
 185 #define PCI_CLASS_SYSTEM_OTHER          0x0880
 186 
 187 #define PCI_BASE_CLASS_INPUT            0x09
 188 #define PCI_CLASS_INPUT_KEYBOARD        0x0900
 189 #define PCI_CLASS_INPUT_PEN             0x0901
 190 #define PCI_CLASS_INPUT_MOUSE           0x0902
 191 #define PCI_CLASS_INPUT_OTHER           0x0980
 192 
 193 #define PCI_BASE_CLASS_DOCKING          0x0a
 194 #define PCI_CLASS_DOCKING_GENERIC       0x0a00
 195 #define PCI_CLASS_DOCKING_OTHER         0x0a01
 196 
 197 #define PCI_BASE_CLASS_PROCESSOR        0x0b
 198 #define PCI_CLASS_PROCESSOR_386         0x0b00
 199 #define PCI_CLASS_PROCESSOR_486         0x0b01
 200 #define PCI_CLASS_PROCESSOR_PENTIUM     0x0b02
 201 #define PCI_CLASS_PROCESSOR_ALPHA       0x0b10
 202 #define PCI_CLASS_PROCESSOR_POWERPC     0x0b20
 203 #define PCI_CLASS_PROCESSOR_CO          0x0b40
 204 
 205 #define PCI_BASE_CLASS_SERIAL           0x0c
 206 #define PCI_CLASS_SERIAL_FIREWIRE       0x0c00
 207 #define PCI_CLASS_SERIAL_ACCESS         0x0c01
 208 #define PCI_CLASS_SERIAL_SSA            0x0c02
 209 #define PCI_CLASS_SERIAL_USB            0x0c03
 210 #define PCI_CLASS_SERIAL_FIBER          0x0c04
 211 
 212 #define PCI_CLASS_OTHERS                0xff
 213 
 214 /*
 215  * Vendor and card ID's: sort these numerically according to vendor
 216  * (and according to card ID within vendor)
 217  */
 218 #define PCI_VENDOR_ID_NCR               0x1000
 219 #define PCI_DEVICE_ID_NCR_53C810        0x0001
 220 #define PCI_DEVICE_ID_NCR_53C820        0x0002
 221 #define PCI_DEVICE_ID_NCR_53C825        0x0003
 222 #define PCI_DEVICE_ID_NCR_53C815        0x0004
 223 
 224 #define PCI_VENDOR_ID_ATI               0x1002
 225 #define PCI_DEVICE_ID_ATI_68800         0x4158
 226 #define PCI_DEVICE_ID_ATI_215CT222      0x4354
 227 #define PCI_DEVICE_ID_ATI_210888CX      0x4358
 228 #define PCI_DEVICE_ID_ATI_210888GX      0x4758
 229 
 230 #define PCI_VENDOR_ID_VLSI              0x1004
 231 #define PCI_DEVICE_ID_VLSI_82C592       0x0005
 232 #define PCI_DEVICE_ID_VLSI_82C593       0x0006
 233 
 234 #define PCI_VENDOR_ID_ADL               0x1005
 235 #define PCI_DEVICE_ID_ADL_2301          0x2301
 236 
 237 #define PCI_VENDOR_ID_NS                0x100b
 238 #define PCI_DEVICE_ID_NS_87410          0xd001
 239 
 240 #define PCI_VENDOR_ID_TSENG             0x100c
 241 #define PCI_DEVICE_ID_TSENG_W32P_2      0x3202
 242 #define PCI_DEVICE_ID_TSENG_W32P_b      0x3205
 243 #define PCI_DEVICE_ID_TSENG_W32P_c      0x3206
 244 #define PCI_DEVICE_ID_TSENG_W32P_d      0x3207
 245 
 246 #define PCI_VENDOR_ID_WEITEK            0x100e
 247 #define PCI_DEVICE_ID_WEITEK_P9000      0x9001
 248 #define PCI_DEVICE_ID_WEITEK_P9100      0x9100
 249 
 250 #define PCI_VENDOR_ID_DEC               0x1011
 251 #define PCI_DEVICE_ID_DEC_BRD           0x0001
 252 #define PCI_DEVICE_ID_DEC_TULIP         0x0002
 253 #define PCI_DEVICE_ID_DEC_TULIP_FAST    0x0009
 254 #define PCI_DEVICE_ID_DEC_FDDI          0x000F
 255 #define PCI_DEVICE_ID_DEC_TULIP_PLUS    0x0014
 256 
 257 #define PCI_VENDOR_ID_CIRRUS            0x1013
 258 #define PCI_DEVICE_ID_CIRRUS_5430       0x00A0
 259 #define PCI_DEVICE_ID_CIRRUS_5434_4     0x00A4
 260 #define PCI_DEVICE_ID_CIRRUS_5434_8     0x00A8
 261 #define PCI_DEVICE_ID_CIRRUS_6729       0x1100
 262 #define PCI_DEVICE_ID_CIRRUS_7542       0x1200
 263 
 264 #define PCI_VENDOR_ID_IBM               0x1014
 265 
 266 #define PCI_VENDOR_ID_AMD               0x1022
 267 #define PCI_DEVICE_ID_AMD_LANCE         0x2000
 268 #define PCI_DEVICE_ID_AMD_SCSI          0x2020
 269 
 270 #define PCI_VENDOR_ID_TRIDENT           0x1023
 271 #define PCI_DEVICE_ID_TRIDENT_9420      0x9420
 272 #define PCI_DEVICE_ID_TRIDENT_9440      0x9440
 273 #define PCI_DEVICE_ID_TRIDENT_9660      0x9660
 274 
 275 #define PCI_VENDOR_ID_AI                0x1025
 276 #define PCI_DEVICE_ID_AI_M1435          0x1435
 277 
 278 #define PCI_VENDOR_ID_MATROX            0x102B
 279 #define PCI_DEVICE_ID_MATROX_MGA_2      0x0518
 280 #define PCI_DEVICE_ID_MATROX_MIL        0x0519
 281 #define PCI_DEVICE_ID_MATROX_MGA_IMP    0x0d10
 282 
 283 #define PCI_VENDOR_ID_CT                0x102c
 284 #define PCI_DEVICE_ID_CT_65545          0x00d8
 285 
 286 #define PCI_VENDOR_ID_FD                0x1036
 287 #define PCI_DEVICE_ID_FD_36C70          0x0000
 288 
 289 #define PCI_VENDOR_ID_SI                0x1039
 290 #define PCI_DEVICE_ID_SI_503            0x0008
 291 #define PCI_DEVICE_ID_SI_501            0x0406
 292 #define PCI_DEVICE_ID_SI_496            0x0496
 293 #define PCI_DEVICE_ID_SI_601            0x0601
 294 #define PCI_DEVICE_ID_SI_5511           0x5511
 295 #define PCI_DEVICE_ID_SI_5513           0x5513
 296 
 297 #define PCI_VENDOR_ID_HP                0x103c
 298 #define PCI_DEVICE_ID_HP_J2585A         0x1030
 299 
 300 #if 0
 301 
 302 #define PCI_VENDOR_ID_SMC               0x1042  /* Is this really correct?? */
 303 #define PCI_DEVICE_ID_SMC_37C665        0x1000
 304 #define PCI_DEVICE_ID_SMC_37C922        0x1001
 305 
 306 #else
 307 
 308 #define PCI_VENDOR_ID_PCTECH            0x1042  /* Known to be correct */
 309 #define PCI_DEVICE_ID_PCTECH_RZ1000     0x1000
 310 
 311 #endif
 312 
 313 #define PCI_VENDOR_ID_DPT               0x1044   
 314 #define PCI_DEVICE_ID_DPT               0xa400  
 315 
 316 #define PCI_VENDOR_ID_OPTI              0x1045
 317 #define PCI_DEVICE_ID_OPTI_82C557       0xc557
 318 #define PCI_DEVICE_ID_OPTI_82C558       0xc558
 319 #define PCI_DEVICE_ID_OPTI_82C621       0xc621
 320 #define PCI_DEVICE_ID_OPTI_82C822       0xc822
 321 
 322 #define PCI_VENDOR_ID_BUSLOGIC          0x104B
 323 #define PCI_DEVICE_ID_BUSLOGIC_946C_2   0x0140
 324 #define PCI_DEVICE_ID_BUSLOGIC_946C     0x1040
 325 
 326 #define PCI_VENDOR_ID_PROMISE           0x105a
 327 #define PCI_DEVICE_ID_PROMISE_5300      0x5300
 328 
 329 #define PCI_VENDOR_ID_N9                0x105D
 330 #define PCI_DEVICE_ID_N9_I128           0x2309
 331 
 332 #define PCI_VENDOR_ID_UMC               0x1060
 333 #define PCI_DEVICE_ID_UMC_UM8673F       0x0101
 334 #define PCI_DEVICE_ID_UMC_UM8891A       0x0891
 335 #define PCI_DEVICE_ID_UMC_UM8886A       0x886a
 336 #define PCI_DEVICE_ID_UMC_UM8881F       0x8881
 337 #define PCI_DEVICE_ID_UMC_UM8886F       0x8886
 338 #define PCI_DEVICE_ID_UMC_UM9017F       0x9017
 339 
 340 #define PCI_VENDOR_ID_X                 0x1061
 341 #define PCI_DEVICE_ID_X_AGX016          0x0001
 342 
 343 #define PCI_VENDOR_ID_QLOGIC            0x1077
 344 #define PCI_DEVICE_ID_QLOGIC_ISP1020    0x1020
 345 #define PCI_DEVICE_ID_QLOGIC_ISP1022    0x1022
 346 
 347 #define PCI_VENDOR_ID_LEADTEK           0x107d
 348 #define PCI_DEVICE_ID_LEADTEK_805       0x0000
 349 
 350 #define PCI_VENDOR_ID_CONTAQ            0x1080
 351 #define PCI_DEVICE_ID_CONTAQ_82C599     0x0600
 352 
 353 #define PCI_VENDOR_ID_OLICOM            0x108d
 354 
 355 #define PCI_VENDOR_ID_CMD               0x1095
 356 #define PCI_DEVICE_ID_CMD_640           0x0640
 357 #define PCI_DEVICE_ID_CMD_646           0x0646
 358 
 359 #define PCI_VENDOR_ID_VISION            0x1098
 360 #define PCI_DEVICE_ID_VISION_QD8500     0x0001
 361 #define PCI_DEVICE_ID_VISION_QD8580     0x0002
 362 
 363 #define PCI_VENDOR_ID_ACC               0x10aa
 364 
 365 #define PCI_VENDOR_ID_WINBOND           0x10ad
 366 #define PCI_DEVICE_ID_WINBOND_83769     0x0001
 367 
 368 #define PCI_VENDOR_ID_3COM              0x10b7
 369 #define PCI_DEVICE_ID_3COM_3C590        0x5900
 370 #define PCI_DEVICE_ID_3COM_3C595TX      0x5950
 371 #define PCI_DEVICE_ID_3COM_3C595T4      0x5951
 372 #define PCI_DEVICE_ID_3COM_3C595MII     0x5952
 373 
 374 #define PCI_VENDOR_ID_AL                0x10b9
 375 #define PCI_DEVICE_ID_AL_M1445          0x1445
 376 #define PCI_DEVICE_ID_AL_M1449          0x1449
 377 #define PCI_DEVICE_ID_AL_M1451          0x1451
 378 #define PCI_DEVICE_ID_AL_M1461          0x1461
 379 #define PCI_DEVICE_ID_AL_M4803          0x5215
 380 
 381 #define PCI_VENDOR_ID_IMS               0x10e0
 382 #define PCI_DEVICE_ID_IMS_8849          0x8849
 383 
 384 #define PCI_VENDOR_ID_REALTEK           0x10ec
 385 #define PCI_DEVICE_ID_REALTEK_8029      0x8029
 386 
 387 #define PCI_VENDOR_ID_VIA               0x1106
 388 #define PCI_DEVICE_ID_VIA_82C505        0x0505
 389 #define PCI_DEVICE_ID_VIA_82C561        0x0561
 390 #define PCI_DEVICE_ID_VIA_82C576        0x0576
 391 
 392 #define PCI_VENDOR_ID_VORTEX            0x1119
 393 #define PCI_DEVICE_ID_VORTEX_GDT        0x0001
 394 
 395 #define PCI_VENDOR_ID_EF                0x111a
 396 #define PCI_DEVICE_ID_EF_ATM            0x0000
 397 
 398 #define PCI_VENDOR_ID_IMAGINGTECH       0x112f
 399 #define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000
 400 
 401 #define PCI_VENDOR_ID_PLX               0x113c
 402 #define PCI_DEVICE_ID_PLX_9060          0x0001
 403 
 404 #define PCI_VENDOR_ID_ALLIANCE          0x1142
 405 #define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422
 406 
 407 #define PCI_VENDOR_ID_MUTECH            0x1159
 408 #define PCI_DEVICE_ID_MUTECH_MV1000     0x0001
 409 
 410 #define PCI_VENDOR_ID_ZEINET            0x1193
 411 #define PCI_DEVICE_ID_ZEINET_1221       0x0001
 412 
 413 #define PCI_VENDOR_ID_CYCLADES          0x120e
 414 #define PCI_DEVICE_ID_CYCLADES_Y        0x0100
 415 
 416 #define PCI_VENDOR_ID_SYMPHONY          0x1c1c
 417 #define PCI_DEVICE_ID_SYMPHONY_101      0x0001
 418 
 419 #define PCI_VENDOR_ID_TEKRAM            0x1de1
 420 #define PCI_DEVICE_ID_TEKRAM_DC290      0xdc29
 421 
 422 #define PCI_VENDOR_ID_AVANCE            0x4005
 423 #define PCI_DEVICE_ID_AVANCE_2302       0x2302
 424 
 425 #define PCI_VENDOR_ID_S3                0x5333
 426 #define PCI_DEVICE_ID_S3_811            0x8811
 427 #define PCI_DEVICE_ID_S3_868            0x8880
 428 #define PCI_DEVICE_ID_S3_928            0x88b0
 429 #define PCI_DEVICE_ID_S3_864_1          0x88c0
 430 #define PCI_DEVICE_ID_S3_864_2          0x88c1
 431 #define PCI_DEVICE_ID_S3_964_1          0x88d0
 432 #define PCI_DEVICE_ID_S3_964_2          0x88d1
 433 #define PCI_DEVICE_ID_S3_968            0x88f0
 434 
 435 #define PCI_VENDOR_ID_INTEL             0x8086
 436 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 437 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 438 #define PCI_DEVICE_ID_INTEL_82378       0x0484
 439 #define PCI_DEVICE_ID_INTEL_82430       0x0486
 440 #define PCI_DEVICE_ID_INTEL_82434       0x04a3
 441 #define PCI_DEVICE_ID_INTEL_7116        0x1223
 442 #define PCI_DEVICE_ID_INTEL_82596       0x1226
 443 #define PCI_DEVICE_ID_INTEL_82865       0x1227
 444 #define PCI_DEVICE_ID_INTEL_82437       0x122d
 445 #define PCI_DEVICE_ID_INTEL_82371_0     0x122e
 446 #define PCI_DEVICE_ID_INTEL_82371_1     0x1230
 447 #define PCI_DEVICE_ID_INTEL_P6          0x84c4
 448 
 449 #define PCI_VENDOR_ID_ADAPTEC           0x9004
 450 #define PCI_DEVICE_ID_ADAPTEC_7850      0x5078
 451 #define PCI_DEVICE_ID_ADAPTEC_7870      0x7078
 452 #define PCI_DEVICE_ID_ADAPTEC_7871      0x7178
 453 #define PCI_DEVICE_ID_ADAPTEC_7872      0x7278
 454 #define PCI_DEVICE_ID_ADAPTEC_7880      0x8078
 455 #define PCI_DEVICE_ID_ADAPTEC_7881      0x8178
 456 
 457 #define PCI_VENDOR_ID_ATRONICS          0x907f
 458 #define PCI_DEVICE_ID_ATRONICS_2015     0x2015
 459 
 460 #define PCI_VENDOR_ID_HER               0xedd8
 461 #define PCI_DEVICE_ID_HER_STING         0xa091
 462 #define PCI_DEVICE_ID_HER_STINGARK      0xa099
 463 
 464 /*
 465  * The PCI interface treats multi-function devices as independent
 466  * devices.  The slot/function address of each device is encoded
 467  * in a single byte as follows:
 468  *
 469  *      7:4 = slot
 470  *      3:0 = function
 471  */
 472 #define PCI_DEVFN(slot,func)    ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 473 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
 474 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
 475 
 476 /*
 477  * There is one pci_dev structure for each slot-number/function-number
 478  * combination:
 479  */
 480 struct pci_dev {
 481         struct pci_bus  *bus;           /* bus this device is on */
 482         struct pci_dev  *sibling;       /* next device on this bus */
 483         struct pci_dev  *next;          /* chain of all devices */
 484 
 485         void            *sysdata;       /* hook for sys-specific extension */
 486 
 487         unsigned int    devfn;          /* encoded device & function index */
 488         unsigned short  vendor;
 489         unsigned short  device;
 490         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
 491         unsigned int    master : 1;     /* set if device is master capable */
 492         /*
 493          * In theory, the irq level can be read from configuration
 494          * space and all would be fine.  However, old PCI chips don't
 495          * support these registers and return 0 instead.  For example,
 496          * the Vision864-P rev 0 chip can uses INTA, but returns 0 in
 497          * the interrupt line and pin registers.  pci_init()
 498          * initializes this field with the value at PCI_INTERRUPT_LINE
 499          * and it is the job of pcibios_fixup() to change it if
 500          * necessary.  The field must not be 0 unless the device
 501          * cannot generate interrupts at all.
 502          */
 503         unsigned char   irq;            /* irq generated by this device */
 504 };
 505 
 506 struct pci_bus {
 507         struct pci_bus  *parent;        /* parent bus this bridge is on */
 508         struct pci_bus  *children;      /* chain of P2P bridges on this bus */
 509         struct pci_bus  *next;          /* chain of all PCI buses */
 510 
 511         struct pci_dev  *self;          /* bridge device as seen by parent */
 512         struct pci_dev  *devices;       /* devices behind this bridge */
 513 
 514         void            *sysdata;       /* hook for sys-specific extension */
 515 
 516         unsigned char   number;         /* bus number */
 517         unsigned char   primary;        /* number of primary bridge */
 518         unsigned char   secondary;      /* number of secondary bridge */
 519         unsigned char   subordinate;    /* max number of subordinate buses */
 520 };
 521 
 522 /*
 523  * This is used to map a vendor-id/device-id pair into device-specific
 524  * information.
 525  */
 526 struct pci_dev_info {
 527         unsigned short  vendor;         /* vendor id */
 528         unsigned short  device;         /* device id */
 529 
 530         const char      *name;          /* device name */
 531         unsigned char   bridge_type;    /* bridge type or 0xff */
 532 };
 533 
 534 extern struct pci_bus   pci_root;       /* root bus */
 535 extern struct pci_dev   *pci_devices;   /* list of all devices */
 536 
 537 
 538 extern unsigned long pci_init (unsigned long mem_start, unsigned long mem_end);
 539 
 540 extern struct pci_dev_info *pci_lookup_dev (unsigned int vendor,
 541                                             unsigned int dev);
 542 extern const char *pci_strbioserr (int error);
 543 extern const char *pci_strclass (unsigned int class);
 544 extern const char *pci_strvendor (unsigned int vendor);
 545 extern const char *pci_strdev (unsigned int vendor, unsigned int device);
 546 
 547 extern int get_pci_list (char *buf);
 548 
 549 #endif /* PCI_H */
/* */
root/include/linux/pci.h

INCLUDED FROM
