1 #ifndef _SPARC_MEMERR_H 2 #define _SPARC_MEMERR_H 3 4 /* memerr.h: Bit fields in the asynchronous and synchronous memory error 5 * registers used to determine what 'type' of error has just 6 * induced a trap. 7 * 8 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu) 9 */ 10 11 /* synchronous error register fields come first... */ 12 13 #define SYNCER_WRITE 0x8000 /* write error... */ 14 #define SYNCER_INVAL 0x0080 /* invalid page access was attempted */ 15 #define SYNCER_PROT 0x0040 /* protection violation */ 16 #define SYNCER_TIMEOUT 0x0020 /* mem-bus access timeout (mem does not exist). */ 17 #define SYNCER_SBUSERR 0x0010 /* same as above, but for an SBUS access */ 18 #define SYNCER_MEMERR 0x0008 /* Bus parity error, lose lose... panic time */ 19 #define SYNCER_SZERR 0x0002 /* an attempted access was of BAD size, whoops */ 20 #define SYNCER_WATCHDOG 0x0001 /* although we never see these, the prom will.. */ 21 22 /* asynchronous error bits go here */ 23 24 #define ASYNCER_WBINVAL 0x80 /* situation arose where the cache tried to write 25 * back a page for which the valid bit was not set 26 * within the mmu. This is due to bad mm kernel bugs. 27 */ 28 29 #define ASYNCER_TIMEOUT 0x20 /* mem-access bus timeout... */ 30 #define ASYNCER_DVMAERR 0x10 /* dvma transfer to/from memory bombed... */ 31 32 #endif /* _SPARC_MEMERR_H */