include/asm-sparc/dma.h

/* */
This source file includes following definitions.
sparc_dma_pause
sparc_dma_enable_interrupts
sparc_dma_disable_interrupts
sparc_dma_reset
   1 /*
   2  * include/asm-sparc/dma.h
   3  *
   4  * Don't even ask, I am figuring out how this crap works
   5  * on the Sparc. It may end up being real hairy to plug
   6  * into this code, maybe not, we'll see.
   7  *
   8  * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
   9  */
  10 
  11 #ifndef _ASM_SPARC_DMA_H
  12 #define _ASM_SPARC_DMA_H
  13 
  14 #include <asm/vac-ops.h>  /* for invalidate's, etc. */
  15 #include <asm/sbus.h>
  16 #include <asm/delay.h>
  17 #include <asm/oplib.h>
  18 
  19 /* DMA probing routine */
  20 extern unsigned long probe_dma(unsigned long);
  21 
  22 /* These are irrelevant for Sparc DMA, but we leave it in so that
  23  * things can compile.
  24  */
  25 #define MAX_DMA_CHANNELS 8
  26 #define MAX_DMA_ADDRESS  0x0
  27 
  28 /* Structure to describe the current status of DMA registers on the Sparc */
  29 struct sparc_dma_registers {
  30   volatile unsigned long cond_reg;   /* DMA condition register */
  31   volatile char * st_addr;           /* Start address of this transfer */
  32   volatile unsigned long cnt;        /* How many bytes to transfer */
  33   volatile unsigned long dma_test;   /* DMA test register */
  34 };
  35 
  36 /* Linux DMA information structure, filled during probe. */
  37 struct Linux_SBus_DMA {
  38   struct linux_sbus_device *SBus_dev;   /* pointer to sbus device struct */
  39   struct sparc_dma_registers *DMA_regs; /* Pointer to DMA regs in IO space */
  40 
  41   /* Status, misc info */
  42   int node;                /* Prom node for this DMA device */
  43   int dma_running;         /* Are we using the DMA now? */
  44 
  45   /* DMA revision: 0=REV0 1=REV1 2=REV2 3=DMA_PLUS */
  46   int dma_rev;
  47 };
  48 
  49 extern struct Linux_SBus_DMA Sparc_DMA;
  50 
  51 /* Main routines in dma.c */
  52 extern void dump_dma_regs(struct sparc_dma_registers *);
  53 extern unsigned long probe_dma(unsigned long);
  54 extern void sparc_dma_init_transfer(struct sparc_dma_registers *,
  55                                     unsigned long, int, int);
  56 extern int sparc_dma_interrupt(struct sparc_dma_registers *);
  57 
  58 /* Fields in the cond_reg register */
  59 /* First, the version identification bits */
  60 #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
  61 #define DMA_VERS0        0x00000000        /* Sunray DMA version */
  62 #define DMA_VERS1        0x80000000        /* DMA rev 1 */
  63 #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
  64 #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
  65 
  66 #define DMA_HNDL_INTR    0x00000001        /* An interrupt needs to be handled */
  67 #define DMA_HNDL_ERROR   0x00000002        /* We need to take care of an error */
  68 #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
  69 #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
  70 #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
  71 #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
  72 #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
  73 #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
  74 #define DMA_ST_WRITE     0x00000100        /* If set, write from device to memory */
  75 #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
  76 #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Read is pending */
  77 #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
  78 #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
  79 #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
  80 #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
  81 #define DMA_BRST_SZ      0x000c0000        /* SBUS transfer r/w burst size */
  82 #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
  83 #define DMA_2CLKS        0x00200000        /* Each transfer equals 2 clock ticks */
  84 #define DMA_3CLKS        0x00400000        /* Each transfer equals 3 clock ticks */
  85 #define DMA_CNTR_DISAB   0x00800000        /* No intr's when DMA_TERM_CNTR is set */
  86 #define DMA_AUTO_NADDR   0x01000000        /* Use "auto next address" feature */
  87 #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
  88 #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
  89 #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
  90 
  91 /* Only 24-bits of the byte count are significant */
  92 #define DMA_BYTE_CNT_MASK  0x00ffffff
  93 
  94 /* Pause until counter runs out or BIT isn't set in the DMA condition
  95  * register.
  96  */
  97 extern inline void sparc_dma_pause(struct sparc_dma_registers *dma_regs,
     /*  */
  98                                    unsigned long bit)
  99 {
 100   int ctr = 50000;   /* Let's find some bugs ;) */
 101 
 102   /* Busy wait until the bit is not set any more */
 103   while((dma_regs->cond_reg&bit) && (ctr>0)) {
 104     ctr--;
 105     __delay(1);
 106   }
 107 
 108   /* Check for bogus outcome. */
 109   if(ctr==0) {
 110     printk("DMA Grrr:  I tried for wait for the assertion of bit %08xl to clear",
 111            (unsigned int) bit);
 112     printk("           in the DMA condition register and it did not!\n");
 113     printk("Cannot continue, halting...\n");
 114     prom_halt();
 115   }
 116 
 117   return;
 118 }
 119 
 120 /* Enable DMA interrupts */
 121 extern inline void sparc_dma_enable_interrupts(struct sparc_dma_registers *dma_regs)
     /*  */
 122 {
 123   dma_regs->cond_reg |= DMA_INT_ENAB;
 124 }
 125 
 126 /* Disable DMA interrupts from coming in */
 127 extern inline void sparc_dma_disable_interrupts(struct sparc_dma_registers *dma_regs)
     /*  */
 128 {
 129   dma_regs->cond_reg &= ~(DMA_INT_ENAB);
 130 }
 131 
 132 /* Reset the DMA module. */
 133 extern inline void sparc_dma_reset(struct sparc_dma_registers *dma_regs)
     /*  */
 134 {
 135   /* Let the current FIFO drain itself */
 136   sparc_dma_pause(dma_regs, (DMA_FIFO_ISDRAIN));
 137 
 138   /* Reset the logic */
 139   dma_regs->cond_reg |= (DMA_RST_SCSI);     /* assert */
 140   __delay(400);                             /* let the bits set ;) */
 141   dma_regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */
 142 
 143   sparc_dma_enable_interrupts(dma_regs);    /* Re-enable interrupts */
 144 
 145   /* Enable FAST transfers if available */
 146   if(Sparc_DMA.dma_rev>1) { dma_regs->cond_reg |= DMA_3CLKS; }
 147   Sparc_DMA.dma_running = 0;
 148 
 149   return;
 150 }
 151 
 152 #endif /* !(_ASM_SPARC_DMA_H) */
/* */
root/include/asm-sparc/dma.h

INCLUDED FROM

DEFINITIONS
