drivers/net/8390.h

/* */
   1 /* Generic NS8390 register definitions. */
   2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
   3    under the same license.
   4    Some of these names and comments originated from the Crynwr
   5    packet drivers, which are distributed under the GPL. */
   6 
   7 #ifndef _8390_h
   8 #define _8390_h
   9 
  10 #include <linux/if_ether.h>
  11 #include <linux/ioport.h>
  12 #include <linux/skbuff.h>
  13 
  14 #define TX_2X_PAGES 12
  15 #define TX_1X_PAGES 6
  16 #define TX_PAGES (ei_status.pingpong ? TX_2X_PAGES : TX_1X_PAGES)
  17 
  18 #define ETHER_ADDR_LEN 6
  19 
  20 /* The 8390 specific per-packet-header format. */
  21 struct e8390_pkt_hdr {
  22   unsigned char status; /* status */
  23   unsigned char next;   /* pointer to next packet. */
  24   unsigned short count; /* header + packet length in bytes */
  25 };
  26 
  27 /* From 8390.c */
  28 extern int ei_debug;
  29 extern struct sigaction ei_sigaction;
  30 
  31 extern int ethif_init(struct device *dev);
  32 extern int ethdev_init(struct device *dev);
  33 extern void NS8390_init(struct device *dev, int startp);
  34 extern int ei_open(struct device *dev);
  35 extern void ei_interrupt(int irq, struct pt_regs *regs);
  36 
  37 #ifndef HAVE_AUTOIRQ
  38 /* From auto_irq.c */
  39 extern struct device *irq2dev_map[16];
  40 extern void autoirq_setup(int waittime);
  41 extern int autoirq_report(int waittime);
  42 #endif
  43 
  44 /* Most of these entries should be in 'struct device' (or most of the
  45    things in there should be here!) */
  46 /* You have one of these per-board */
  47 struct ei_device {
  48   const char *name;
  49   void (*reset_8390)(struct device *);
  50   void (*get_8390_hdr)(struct device *, struct e8390_pkt_hdr *, int);
  51   void (*block_output)(struct device *, int, const unsigned char *, int);
  52   void (*block_input)(struct device *, int, struct sk_buff *, int);
  53   unsigned open:1;
  54   unsigned word16:1;  /* We have the 16-bit (vs 8-bit) version of the card. */
  55   unsigned txing:1;             /* Transmit Active */
  56   unsigned irqlock:1;           /* 8390's intrs disabled when '1'. */
  57   unsigned dmaing:1;            /* Remote DMA Active */
  58   unsigned pingpong:1;          /* Using the ping-pong driver */
  59   unsigned char tx_start_page, rx_start_page, stop_page;
  60   unsigned char current_page;   /* Read pointer in buffer  */
  61   unsigned char interface_num;  /* Net port (AUI, 10bT.) to use. */
  62   unsigned char txqueue;        /* Tx Packet buffer queue length. */
  63   short tx1, tx2;               /* Packet lengths for ping-pong tx. */
  64   short lasttx;                 /* Alpha version consistency check. */
  65   unsigned char reg0;           /* Register '0' in a WD8013 */
  66   unsigned char reg5;           /* Register '5' in a WD8013 */
  67   unsigned char saved_irq;      /* Original dev->irq value. */
  68   /* The new statistics table. */
  69   struct enet_statistics stat;
  70 };
  71 
  72 /* The maximum number of 8390 interrupt service routines called per IRQ. */
  73 #define MAX_SERVICE 12
  74 
  75 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
  76 #define TX_TIMEOUT (20*HZ/100)
  77 
  78 #define ei_status (*(struct ei_device *)(dev->priv))
  79 
  80 /* Some generic ethernet register configurations. */
  81 #define E8390_TX_IRQ_MASK 0xa   /* For register EN0_ISR */
  82 #define E8390_RX_IRQ_MASK  0x5
  83 #define E8390_RXCONFIG 0x4      /* EN0_RXCR: broadcasts, no multicast,errors */
  84 #define E8390_RXOFF 0x20        /* EN0_RXCR: Accept no packets */
  85 #define E8390_TXCONFIG 0x00     /* EN0_TXCR: Normal transmit mode */
  86 #define E8390_TXOFF 0x02        /* EN0_TXCR: Transmitter off */
  87 
  88 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  89 #define E8390_STOP      0x01    /* Stop and reset the chip */
  90 #define E8390_START     0x02    /* Start the chip, clear reset */
  91 #define E8390_TRANS     0x04    /* Transmit a frame */
  92 #define E8390_RREAD     0x08    /* Remote read */
  93 #define E8390_RWRITE    0x10    /* Remote write  */
  94 #define E8390_NODMA     0x20    /* Remote DMA */
  95 #define E8390_PAGE0     0x00    /* Select page chip registers */
  96 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  97 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  98 
  99 #define E8390_CMD       0x00    /* The command register (for all pages) */
 100 /* Page 0 register offsets. */
 101 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
 102 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
 103 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
 104 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
 105 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
 106 #define EN0_TSR         0x04    /* Transmit status reg RD */
 107 #define EN0_TPSR        0x04    /* Transmit starting page WR */
 108 #define EN0_NCR         0x05    /* Number of collision reg RD */
 109 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
 110 #define EN0_FIFO        0x06    /* FIFO RD */
 111 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
 112 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
 113 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
 114 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
 115 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
 116 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
 117 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
 118 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
 119 #define EN0_RSR         0x0c    /* rx status reg RD */
 120 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
 121 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
 122 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
 123 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
 124 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
 125 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
 126 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
 127 
 128 /* Bits in EN0_ISR - Interrupt status register */
 129 #define ENISR_RX        0x01    /* Receiver, no error */
 130 #define ENISR_TX        0x02    /* Transmitter, no error */
 131 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
 132 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
 133 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
 134 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
 135 #define ENISR_RDC       0x40    /* remote dma complete */
 136 #define ENISR_RESET     0x80    /* Reset completed */
 137 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 138 
 139 /* Bits in EN0_DCFG - Data config register */
 140 #define ENDCFG_WTS      0x01    /* word transfer mode selection */
 141 
 142 /* Page 1 register offsets. */
 143 #define EN1_PHYS   0x01 /* This board's physical enet addr RD WR */
 144 #define EN1_CURPAG 0x07 /* Current memory page RD WR */
 145 #define EN1_MULT   0x08 /* Multicast filter mask array (8 bytes) RD WR */
 146 
 147 /* Bits in received packet status byte and EN0_RSR*/
 148 #define ENRSR_RXOK      0x01    /* Received a good packet */
 149 #define ENRSR_CRC       0x02    /* CRC error */
 150 #define ENRSR_FAE       0x04    /* frame alignment error */
 151 #define ENRSR_FO        0x08    /* FIFO overrun */
 152 #define ENRSR_MPA       0x10    /* missed pkt */
 153 #define ENRSR_PHY       0x20    /* physical/multicase address */
 154 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 155 #define ENRSR_DEF       0x80    /* deferring */
 156 
 157 /* Transmitted packet status, EN0_TSR. */
 158 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 159 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 160 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 161 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 162 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 163 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 164 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 165 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 166 
 167 #endif /* _8390_h */
/* */
root/drivers/net/8390.h

INCLUDED FROM
